1 /*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014-2017 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) "bcmgenet: " fmt
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/fcntl.h>
18 #include <linux/interrupt.h>
19 #include <linux/string.h>
20 #include <linux/if_ether.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm.h>
27 #include <linux/clk.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
33 #include <net/arp.h>
34
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
37 #include <linux/netdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
41 #include <linux/in.h>
42 #include <linux/ip.h>
43 #include <linux/ipv6.h>
44 #include <linux/phy.h>
45 #include <linux/platform_data/bcmgenet.h>
46
47 #include <asm/unaligned.h>
48
49 #include "bcmgenet.h"
50
51 /* Maximum number of hardware queues, downsized if needed */
52 #define GENET_MAX_MQ_CNT 4
53
54 /* Default highest priority queue for multi queue support */
55 #define GENET_Q0_PRIORITY 0
56
57 #define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
59 #define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
61
62 #define RX_BUF_LENGTH 2048
63 #define SKB_ALIGNMENT 32
64
65 /* Tx/Rx DMA register offset, skip 256 descriptors */
66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
dmadesc_set_length_status(struct bcmgenet_priv * priv,void __iomem * d,u32 value)75 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
76 void __iomem *d, u32 value)
77 {
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79 }
80
dmadesc_get_length_status(struct bcmgenet_priv * priv,void __iomem * d)81 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
82 void __iomem *d)
83 {
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85 }
86
dmadesc_set_addr(struct bcmgenet_priv * priv,void __iomem * d,dma_addr_t addr)87 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90 {
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
95 * the platform is explicitly configured for 64-bits/LPAE.
96 */
97 #ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100 #endif
101 }
102
103 /* Combined address + length/status setter */
dmadesc_set(struct bcmgenet_priv * priv,void __iomem * d,dma_addr_t addr,u32 val)104 static inline void dmadesc_set(struct bcmgenet_priv *priv,
105 void __iomem *d, dma_addr_t addr, u32 val)
106 {
107 dmadesc_set_length_status(priv, d, val);
108 dmadesc_set_addr(priv, d, addr);
109 }
110
dmadesc_get_addr(struct bcmgenet_priv * priv,void __iomem * d)111 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113 {
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
120 * the platform is explicitly configured for 64-bits/LPAE.
121 */
122 #ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125 #endif
126 return addr;
127 }
128
129 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv * priv)134 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135 {
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140 }
141
bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv * priv,u32 val)142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143 {
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148 }
149
150 /* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv * priv)154 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155 {
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161 }
162
bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv * priv,u32 val)163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164 {
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170 }
171
bcmgenet_bp_mc_get(struct bcmgenet_priv * priv)172 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173 {
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179 }
180
bcmgenet_bp_mc_set(struct bcmgenet_priv * priv,u32 val)181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182 {
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188 }
189
190 /* RX/TX DMA register accessors */
191 enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
200 DMA_INDEX2RING_0,
201 DMA_INDEX2RING_1,
202 DMA_INDEX2RING_2,
203 DMA_INDEX2RING_3,
204 DMA_INDEX2RING_4,
205 DMA_INDEX2RING_5,
206 DMA_INDEX2RING_6,
207 DMA_INDEX2RING_7,
208 DMA_RING0_TIMEOUT,
209 DMA_RING1_TIMEOUT,
210 DMA_RING2_TIMEOUT,
211 DMA_RING3_TIMEOUT,
212 DMA_RING4_TIMEOUT,
213 DMA_RING5_TIMEOUT,
214 DMA_RING6_TIMEOUT,
215 DMA_RING7_TIMEOUT,
216 DMA_RING8_TIMEOUT,
217 DMA_RING9_TIMEOUT,
218 DMA_RING10_TIMEOUT,
219 DMA_RING11_TIMEOUT,
220 DMA_RING12_TIMEOUT,
221 DMA_RING13_TIMEOUT,
222 DMA_RING14_TIMEOUT,
223 DMA_RING15_TIMEOUT,
224 DMA_RING16_TIMEOUT,
225 };
226
227 static const u8 bcmgenet_dma_regs_v3plus[] = {
228 [DMA_RING_CFG] = 0x00,
229 [DMA_CTRL] = 0x04,
230 [DMA_STATUS] = 0x08,
231 [DMA_SCB_BURST_SIZE] = 0x0C,
232 [DMA_ARB_CTRL] = 0x2C,
233 [DMA_PRIORITY_0] = 0x30,
234 [DMA_PRIORITY_1] = 0x34,
235 [DMA_PRIORITY_2] = 0x38,
236 [DMA_RING0_TIMEOUT] = 0x2C,
237 [DMA_RING1_TIMEOUT] = 0x30,
238 [DMA_RING2_TIMEOUT] = 0x34,
239 [DMA_RING3_TIMEOUT] = 0x38,
240 [DMA_RING4_TIMEOUT] = 0x3c,
241 [DMA_RING5_TIMEOUT] = 0x40,
242 [DMA_RING6_TIMEOUT] = 0x44,
243 [DMA_RING7_TIMEOUT] = 0x48,
244 [DMA_RING8_TIMEOUT] = 0x4c,
245 [DMA_RING9_TIMEOUT] = 0x50,
246 [DMA_RING10_TIMEOUT] = 0x54,
247 [DMA_RING11_TIMEOUT] = 0x58,
248 [DMA_RING12_TIMEOUT] = 0x5c,
249 [DMA_RING13_TIMEOUT] = 0x60,
250 [DMA_RING14_TIMEOUT] = 0x64,
251 [DMA_RING15_TIMEOUT] = 0x68,
252 [DMA_RING16_TIMEOUT] = 0x6C,
253 [DMA_INDEX2RING_0] = 0x70,
254 [DMA_INDEX2RING_1] = 0x74,
255 [DMA_INDEX2RING_2] = 0x78,
256 [DMA_INDEX2RING_3] = 0x7C,
257 [DMA_INDEX2RING_4] = 0x80,
258 [DMA_INDEX2RING_5] = 0x84,
259 [DMA_INDEX2RING_6] = 0x88,
260 [DMA_INDEX2RING_7] = 0x8C,
261 };
262
263 static const u8 bcmgenet_dma_regs_v2[] = {
264 [DMA_RING_CFG] = 0x00,
265 [DMA_CTRL] = 0x04,
266 [DMA_STATUS] = 0x08,
267 [DMA_SCB_BURST_SIZE] = 0x0C,
268 [DMA_ARB_CTRL] = 0x30,
269 [DMA_PRIORITY_0] = 0x34,
270 [DMA_PRIORITY_1] = 0x38,
271 [DMA_PRIORITY_2] = 0x3C,
272 [DMA_RING0_TIMEOUT] = 0x2C,
273 [DMA_RING1_TIMEOUT] = 0x30,
274 [DMA_RING2_TIMEOUT] = 0x34,
275 [DMA_RING3_TIMEOUT] = 0x38,
276 [DMA_RING4_TIMEOUT] = 0x3c,
277 [DMA_RING5_TIMEOUT] = 0x40,
278 [DMA_RING6_TIMEOUT] = 0x44,
279 [DMA_RING7_TIMEOUT] = 0x48,
280 [DMA_RING8_TIMEOUT] = 0x4c,
281 [DMA_RING9_TIMEOUT] = 0x50,
282 [DMA_RING10_TIMEOUT] = 0x54,
283 [DMA_RING11_TIMEOUT] = 0x58,
284 [DMA_RING12_TIMEOUT] = 0x5c,
285 [DMA_RING13_TIMEOUT] = 0x60,
286 [DMA_RING14_TIMEOUT] = 0x64,
287 [DMA_RING15_TIMEOUT] = 0x68,
288 [DMA_RING16_TIMEOUT] = 0x6C,
289 };
290
291 static const u8 bcmgenet_dma_regs_v1[] = {
292 [DMA_CTRL] = 0x00,
293 [DMA_STATUS] = 0x04,
294 [DMA_SCB_BURST_SIZE] = 0x0C,
295 [DMA_ARB_CTRL] = 0x30,
296 [DMA_PRIORITY_0] = 0x34,
297 [DMA_PRIORITY_1] = 0x38,
298 [DMA_PRIORITY_2] = 0x3C,
299 [DMA_RING0_TIMEOUT] = 0x2C,
300 [DMA_RING1_TIMEOUT] = 0x30,
301 [DMA_RING2_TIMEOUT] = 0x34,
302 [DMA_RING3_TIMEOUT] = 0x38,
303 [DMA_RING4_TIMEOUT] = 0x3c,
304 [DMA_RING5_TIMEOUT] = 0x40,
305 [DMA_RING6_TIMEOUT] = 0x44,
306 [DMA_RING7_TIMEOUT] = 0x48,
307 [DMA_RING8_TIMEOUT] = 0x4c,
308 [DMA_RING9_TIMEOUT] = 0x50,
309 [DMA_RING10_TIMEOUT] = 0x54,
310 [DMA_RING11_TIMEOUT] = 0x58,
311 [DMA_RING12_TIMEOUT] = 0x5c,
312 [DMA_RING13_TIMEOUT] = 0x60,
313 [DMA_RING14_TIMEOUT] = 0x64,
314 [DMA_RING15_TIMEOUT] = 0x68,
315 [DMA_RING16_TIMEOUT] = 0x6C,
316 };
317
318 /* Set at runtime once bcmgenet version is known */
319 static const u8 *bcmgenet_dma_regs;
320
dev_to_priv(struct device * dev)321 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
322 {
323 return netdev_priv(dev_get_drvdata(dev));
324 }
325
bcmgenet_tdma_readl(struct bcmgenet_priv * priv,enum dma_reg r)326 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
327 enum dma_reg r)
328 {
329 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
330 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
331 }
332
bcmgenet_tdma_writel(struct bcmgenet_priv * priv,u32 val,enum dma_reg r)333 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
334 u32 val, enum dma_reg r)
335 {
336 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
337 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
338 }
339
bcmgenet_rdma_readl(struct bcmgenet_priv * priv,enum dma_reg r)340 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
341 enum dma_reg r)
342 {
343 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
344 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
345 }
346
bcmgenet_rdma_writel(struct bcmgenet_priv * priv,u32 val,enum dma_reg r)347 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
348 u32 val, enum dma_reg r)
349 {
350 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
351 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
352 }
353
354 /* RDMA/TDMA ring registers and accessors
355 * we merge the common fields and just prefix with T/D the registers
356 * having different meaning depending on the direction
357 */
358 enum dma_ring_reg {
359 TDMA_READ_PTR = 0,
360 RDMA_WRITE_PTR = TDMA_READ_PTR,
361 TDMA_READ_PTR_HI,
362 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
363 TDMA_CONS_INDEX,
364 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
365 TDMA_PROD_INDEX,
366 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
367 DMA_RING_BUF_SIZE,
368 DMA_START_ADDR,
369 DMA_START_ADDR_HI,
370 DMA_END_ADDR,
371 DMA_END_ADDR_HI,
372 DMA_MBUF_DONE_THRESH,
373 TDMA_FLOW_PERIOD,
374 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
375 TDMA_WRITE_PTR,
376 RDMA_READ_PTR = TDMA_WRITE_PTR,
377 TDMA_WRITE_PTR_HI,
378 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
379 };
380
381 /* GENET v4 supports 40-bits pointer addressing
382 * for obvious reasons the LO and HI word parts
383 * are contiguous, but this offsets the other
384 * registers.
385 */
386 static const u8 genet_dma_ring_regs_v4[] = {
387 [TDMA_READ_PTR] = 0x00,
388 [TDMA_READ_PTR_HI] = 0x04,
389 [TDMA_CONS_INDEX] = 0x08,
390 [TDMA_PROD_INDEX] = 0x0C,
391 [DMA_RING_BUF_SIZE] = 0x10,
392 [DMA_START_ADDR] = 0x14,
393 [DMA_START_ADDR_HI] = 0x18,
394 [DMA_END_ADDR] = 0x1C,
395 [DMA_END_ADDR_HI] = 0x20,
396 [DMA_MBUF_DONE_THRESH] = 0x24,
397 [TDMA_FLOW_PERIOD] = 0x28,
398 [TDMA_WRITE_PTR] = 0x2C,
399 [TDMA_WRITE_PTR_HI] = 0x30,
400 };
401
402 static const u8 genet_dma_ring_regs_v123[] = {
403 [TDMA_READ_PTR] = 0x00,
404 [TDMA_CONS_INDEX] = 0x04,
405 [TDMA_PROD_INDEX] = 0x08,
406 [DMA_RING_BUF_SIZE] = 0x0C,
407 [DMA_START_ADDR] = 0x10,
408 [DMA_END_ADDR] = 0x14,
409 [DMA_MBUF_DONE_THRESH] = 0x18,
410 [TDMA_FLOW_PERIOD] = 0x1C,
411 [TDMA_WRITE_PTR] = 0x20,
412 };
413
414 /* Set at runtime once GENET version is known */
415 static const u8 *genet_dma_ring_regs;
416
bcmgenet_tdma_ring_readl(struct bcmgenet_priv * priv,unsigned int ring,enum dma_ring_reg r)417 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
418 unsigned int ring,
419 enum dma_ring_reg r)
420 {
421 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
422 (DMA_RING_SIZE * ring) +
423 genet_dma_ring_regs[r]);
424 }
425
bcmgenet_tdma_ring_writel(struct bcmgenet_priv * priv,unsigned int ring,u32 val,enum dma_ring_reg r)426 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
427 unsigned int ring, u32 val,
428 enum dma_ring_reg r)
429 {
430 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
431 (DMA_RING_SIZE * ring) +
432 genet_dma_ring_regs[r]);
433 }
434
bcmgenet_rdma_ring_readl(struct bcmgenet_priv * priv,unsigned int ring,enum dma_ring_reg r)435 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
436 unsigned int ring,
437 enum dma_ring_reg r)
438 {
439 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
440 (DMA_RING_SIZE * ring) +
441 genet_dma_ring_regs[r]);
442 }
443
bcmgenet_rdma_ring_writel(struct bcmgenet_priv * priv,unsigned int ring,u32 val,enum dma_ring_reg r)444 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
445 unsigned int ring, u32 val,
446 enum dma_ring_reg r)
447 {
448 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
449 (DMA_RING_SIZE * ring) +
450 genet_dma_ring_regs[r]);
451 }
452
bcmgenet_get_settings(struct net_device * dev,struct ethtool_cmd * cmd)453 static int bcmgenet_get_settings(struct net_device *dev,
454 struct ethtool_cmd *cmd)
455 {
456 struct bcmgenet_priv *priv = netdev_priv(dev);
457
458 if (!netif_running(dev))
459 return -EINVAL;
460
461 if (!priv->phydev)
462 return -ENODEV;
463
464 return phy_ethtool_gset(priv->phydev, cmd);
465 }
466
bcmgenet_set_settings(struct net_device * dev,struct ethtool_cmd * cmd)467 static int bcmgenet_set_settings(struct net_device *dev,
468 struct ethtool_cmd *cmd)
469 {
470 struct bcmgenet_priv *priv = netdev_priv(dev);
471
472 if (!netif_running(dev))
473 return -EINVAL;
474
475 if (!priv->phydev)
476 return -ENODEV;
477
478 return phy_ethtool_sset(priv->phydev, cmd);
479 }
480
bcmgenet_set_rx_csum(struct net_device * dev,netdev_features_t wanted)481 static int bcmgenet_set_rx_csum(struct net_device *dev,
482 netdev_features_t wanted)
483 {
484 struct bcmgenet_priv *priv = netdev_priv(dev);
485 u32 rbuf_chk_ctrl;
486 bool rx_csum_en;
487
488 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
489
490 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
491
492 /* enable rx checksumming */
493 if (rx_csum_en)
494 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
495 else
496 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
497 priv->desc_rxchk_en = rx_csum_en;
498
499 /* If UniMAC forwards CRC, we need to skip over it to get
500 * a valid CHK bit to be set in the per-packet status word
501 */
502 if (rx_csum_en && priv->crc_fwd_en)
503 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
504 else
505 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
506
507 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
508
509 return 0;
510 }
511
bcmgenet_set_tx_csum(struct net_device * dev,netdev_features_t wanted)512 static int bcmgenet_set_tx_csum(struct net_device *dev,
513 netdev_features_t wanted)
514 {
515 struct bcmgenet_priv *priv = netdev_priv(dev);
516 bool desc_64b_en;
517 u32 tbuf_ctrl, rbuf_ctrl;
518
519 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
520 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
521
522 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
523
524 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
525 if (desc_64b_en) {
526 tbuf_ctrl |= RBUF_64B_EN;
527 rbuf_ctrl |= RBUF_64B_EN;
528 } else {
529 tbuf_ctrl &= ~RBUF_64B_EN;
530 rbuf_ctrl &= ~RBUF_64B_EN;
531 }
532 priv->desc_64b_en = desc_64b_en;
533
534 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
535 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
536
537 return 0;
538 }
539
bcmgenet_set_features(struct net_device * dev,netdev_features_t features)540 static int bcmgenet_set_features(struct net_device *dev,
541 netdev_features_t features)
542 {
543 netdev_features_t changed = features ^ dev->features;
544 netdev_features_t wanted = dev->wanted_features;
545 int ret = 0;
546
547 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
548 ret = bcmgenet_set_tx_csum(dev, wanted);
549 if (changed & (NETIF_F_RXCSUM))
550 ret = bcmgenet_set_rx_csum(dev, wanted);
551
552 return ret;
553 }
554
bcmgenet_get_msglevel(struct net_device * dev)555 static u32 bcmgenet_get_msglevel(struct net_device *dev)
556 {
557 struct bcmgenet_priv *priv = netdev_priv(dev);
558
559 return priv->msg_enable;
560 }
561
bcmgenet_set_msglevel(struct net_device * dev,u32 level)562 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
563 {
564 struct bcmgenet_priv *priv = netdev_priv(dev);
565
566 priv->msg_enable = level;
567 }
568
bcmgenet_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec)569 static int bcmgenet_get_coalesce(struct net_device *dev,
570 struct ethtool_coalesce *ec)
571 {
572 struct bcmgenet_priv *priv = netdev_priv(dev);
573
574 ec->tx_max_coalesced_frames =
575 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
576 DMA_MBUF_DONE_THRESH);
577 ec->rx_max_coalesced_frames =
578 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
579 DMA_MBUF_DONE_THRESH);
580 ec->rx_coalesce_usecs =
581 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
582
583 return 0;
584 }
585
bcmgenet_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec)586 static int bcmgenet_set_coalesce(struct net_device *dev,
587 struct ethtool_coalesce *ec)
588 {
589 struct bcmgenet_priv *priv = netdev_priv(dev);
590 unsigned int i;
591 u32 reg;
592
593 /* Base system clock is 125Mhz, DMA timeout is this reference clock
594 * divided by 1024, which yields roughly 8.192us, our maximum value
595 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
596 */
597 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
598 ec->tx_max_coalesced_frames == 0 ||
599 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
600 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
601 return -EINVAL;
602
603 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
604 return -EINVAL;
605
606 /* GENET TDMA hardware does not support a configurable timeout, but will
607 * always generate an interrupt either after MBDONE packets have been
608 * transmitted, or when the ring is emtpy.
609 */
610 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
611 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
612 return -EOPNOTSUPP;
613
614 /* Program all TX queues with the same values, as there is no
615 * ethtool knob to do coalescing on a per-queue basis
616 */
617 for (i = 0; i < priv->hw_params->tx_queues; i++)
618 bcmgenet_tdma_ring_writel(priv, i,
619 ec->tx_max_coalesced_frames,
620 DMA_MBUF_DONE_THRESH);
621 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
622 ec->tx_max_coalesced_frames,
623 DMA_MBUF_DONE_THRESH);
624
625 for (i = 0; i < priv->hw_params->rx_queues; i++) {
626 bcmgenet_rdma_ring_writel(priv, i,
627 ec->rx_max_coalesced_frames,
628 DMA_MBUF_DONE_THRESH);
629
630 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
631 reg &= ~DMA_TIMEOUT_MASK;
632 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
633 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
634 }
635
636 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
637 ec->rx_max_coalesced_frames,
638 DMA_MBUF_DONE_THRESH);
639
640 reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
641 reg &= ~DMA_TIMEOUT_MASK;
642 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
643 bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
644
645 return 0;
646 }
647
648 /* standard ethtool support functions. */
649 enum bcmgenet_stat_type {
650 BCMGENET_STAT_NETDEV = -1,
651 BCMGENET_STAT_MIB_RX,
652 BCMGENET_STAT_MIB_TX,
653 BCMGENET_STAT_RUNT,
654 BCMGENET_STAT_MISC,
655 BCMGENET_STAT_SOFT,
656 };
657
658 struct bcmgenet_stats {
659 char stat_string[ETH_GSTRING_LEN];
660 int stat_sizeof;
661 int stat_offset;
662 enum bcmgenet_stat_type type;
663 /* reg offset from UMAC base for misc counters */
664 u16 reg_offset;
665 };
666
667 #define STAT_NETDEV(m) { \
668 .stat_string = __stringify(m), \
669 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
670 .stat_offset = offsetof(struct net_device_stats, m), \
671 .type = BCMGENET_STAT_NETDEV, \
672 }
673
674 #define STAT_GENET_MIB(str, m, _type) { \
675 .stat_string = str, \
676 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
677 .stat_offset = offsetof(struct bcmgenet_priv, m), \
678 .type = _type, \
679 }
680
681 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
682 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
683 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
684 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
685
686 #define STAT_GENET_MISC(str, m, offset) { \
687 .stat_string = str, \
688 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
689 .stat_offset = offsetof(struct bcmgenet_priv, m), \
690 .type = BCMGENET_STAT_MISC, \
691 .reg_offset = offset, \
692 }
693
694
695 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
696 * between the end of TX stats and the beginning of the RX RUNT
697 */
698 #define BCMGENET_STAT_OFFSET 0xc
699
700 /* Hardware counters must be kept in sync because the order/offset
701 * is important here (order in structure declaration = order in hardware)
702 */
703 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
704 /* general stats */
705 STAT_NETDEV(rx_packets),
706 STAT_NETDEV(tx_packets),
707 STAT_NETDEV(rx_bytes),
708 STAT_NETDEV(tx_bytes),
709 STAT_NETDEV(rx_errors),
710 STAT_NETDEV(tx_errors),
711 STAT_NETDEV(rx_dropped),
712 STAT_NETDEV(tx_dropped),
713 STAT_NETDEV(multicast),
714 /* UniMAC RSV counters */
715 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
716 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
717 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
718 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
719 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
720 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
721 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
722 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
723 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
724 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
725 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
726 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
727 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
728 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
729 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
730 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
731 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
732 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
733 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
734 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
735 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
736 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
737 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
738 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
739 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
740 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
741 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
742 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
743 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
744 /* UniMAC TSV counters */
745 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
746 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
747 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
748 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
749 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
750 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
751 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
752 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
753 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
754 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
755 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
756 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
757 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
758 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
759 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
760 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
761 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
762 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
763 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
764 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
765 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
766 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
767 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
768 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
769 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
770 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
771 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
772 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
773 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
774 /* UniMAC RUNT counters */
775 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
776 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
777 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
778 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
779 /* Misc UniMAC counters */
780 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
781 UMAC_RBUF_OVFL_CNT_V1),
782 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
783 UMAC_RBUF_ERR_CNT_V1),
784 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
785 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
786 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
787 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
788 };
789
790 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
791
bcmgenet_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)792 static void bcmgenet_get_drvinfo(struct net_device *dev,
793 struct ethtool_drvinfo *info)
794 {
795 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
796 strlcpy(info->version, "v2.0", sizeof(info->version));
797 }
798
bcmgenet_get_sset_count(struct net_device * dev,int string_set)799 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
800 {
801 switch (string_set) {
802 case ETH_SS_STATS:
803 return BCMGENET_STATS_LEN;
804 default:
805 return -EOPNOTSUPP;
806 }
807 }
808
bcmgenet_get_strings(struct net_device * dev,u32 stringset,u8 * data)809 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
810 u8 *data)
811 {
812 int i;
813
814 switch (stringset) {
815 case ETH_SS_STATS:
816 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
817 memcpy(data + i * ETH_GSTRING_LEN,
818 bcmgenet_gstrings_stats[i].stat_string,
819 ETH_GSTRING_LEN);
820 }
821 break;
822 }
823 }
824
bcmgenet_update_stat_misc(struct bcmgenet_priv * priv,u16 offset)825 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
826 {
827 u16 new_offset;
828 u32 val;
829
830 switch (offset) {
831 case UMAC_RBUF_OVFL_CNT_V1:
832 if (GENET_IS_V2(priv))
833 new_offset = RBUF_OVFL_CNT_V2;
834 else
835 new_offset = RBUF_OVFL_CNT_V3PLUS;
836
837 val = bcmgenet_rbuf_readl(priv, new_offset);
838 /* clear if overflowed */
839 if (val == ~0)
840 bcmgenet_rbuf_writel(priv, 0, new_offset);
841 break;
842 case UMAC_RBUF_ERR_CNT_V1:
843 if (GENET_IS_V2(priv))
844 new_offset = RBUF_ERR_CNT_V2;
845 else
846 new_offset = RBUF_ERR_CNT_V3PLUS;
847
848 val = bcmgenet_rbuf_readl(priv, new_offset);
849 /* clear if overflowed */
850 if (val == ~0)
851 bcmgenet_rbuf_writel(priv, 0, new_offset);
852 break;
853 default:
854 val = bcmgenet_umac_readl(priv, offset);
855 /* clear if overflowed */
856 if (val == ~0)
857 bcmgenet_umac_writel(priv, 0, offset);
858 break;
859 }
860
861 return val;
862 }
863
bcmgenet_update_mib_counters(struct bcmgenet_priv * priv)864 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
865 {
866 int i, j = 0;
867
868 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
869 const struct bcmgenet_stats *s;
870 u8 offset = 0;
871 u32 val = 0;
872 char *p;
873
874 s = &bcmgenet_gstrings_stats[i];
875 switch (s->type) {
876 case BCMGENET_STAT_NETDEV:
877 case BCMGENET_STAT_SOFT:
878 continue;
879 case BCMGENET_STAT_RUNT:
880 offset += BCMGENET_STAT_OFFSET;
881 /* fall through */
882 case BCMGENET_STAT_MIB_TX:
883 offset += BCMGENET_STAT_OFFSET;
884 /* fall through */
885 case BCMGENET_STAT_MIB_RX:
886 val = bcmgenet_umac_readl(priv,
887 UMAC_MIB_START + j + offset);
888 offset = 0; /* Reset Offset */
889 break;
890 case BCMGENET_STAT_MISC:
891 if (GENET_IS_V1(priv)) {
892 val = bcmgenet_umac_readl(priv, s->reg_offset);
893 /* clear if overflowed */
894 if (val == ~0)
895 bcmgenet_umac_writel(priv, 0,
896 s->reg_offset);
897 } else {
898 val = bcmgenet_update_stat_misc(priv,
899 s->reg_offset);
900 }
901 break;
902 }
903
904 j += s->stat_sizeof;
905 p = (char *)priv + s->stat_offset;
906 *(u32 *)p = val;
907 }
908 }
909
bcmgenet_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)910 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
911 struct ethtool_stats *stats,
912 u64 *data)
913 {
914 struct bcmgenet_priv *priv = netdev_priv(dev);
915 int i;
916
917 if (netif_running(dev))
918 bcmgenet_update_mib_counters(priv);
919
920 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
921 const struct bcmgenet_stats *s;
922 char *p;
923
924 s = &bcmgenet_gstrings_stats[i];
925 if (s->type == BCMGENET_STAT_NETDEV)
926 p = (char *)&dev->stats;
927 else
928 p = (char *)priv;
929 p += s->stat_offset;
930 if (sizeof(unsigned long) != sizeof(u32) &&
931 s->stat_sizeof == sizeof(unsigned long))
932 data[i] = *(unsigned long *)p;
933 else
934 data[i] = *(u32 *)p;
935 }
936 }
937
bcmgenet_eee_enable_set(struct net_device * dev,bool enable)938 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
939 {
940 struct bcmgenet_priv *priv = netdev_priv(dev);
941 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
942 u32 reg;
943
944 if (enable && !priv->clk_eee_enabled) {
945 clk_prepare_enable(priv->clk_eee);
946 priv->clk_eee_enabled = true;
947 }
948
949 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
950 if (enable)
951 reg |= EEE_EN;
952 else
953 reg &= ~EEE_EN;
954 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
955
956 /* Enable EEE and switch to a 27Mhz clock automatically */
957 reg = __raw_readl(priv->base + off);
958 if (enable)
959 reg |= TBUF_EEE_EN | TBUF_PM_EN;
960 else
961 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
962 __raw_writel(reg, priv->base + off);
963
964 /* Do the same for thing for RBUF */
965 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
966 if (enable)
967 reg |= RBUF_EEE_EN | RBUF_PM_EN;
968 else
969 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
970 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
971
972 if (!enable && priv->clk_eee_enabled) {
973 clk_disable_unprepare(priv->clk_eee);
974 priv->clk_eee_enabled = false;
975 }
976
977 priv->eee.eee_enabled = enable;
978 priv->eee.eee_active = enable;
979 }
980
bcmgenet_get_eee(struct net_device * dev,struct ethtool_eee * e)981 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
982 {
983 struct bcmgenet_priv *priv = netdev_priv(dev);
984 struct ethtool_eee *p = &priv->eee;
985
986 if (GENET_IS_V1(priv))
987 return -EOPNOTSUPP;
988
989 e->eee_enabled = p->eee_enabled;
990 e->eee_active = p->eee_active;
991 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
992
993 return phy_ethtool_get_eee(priv->phydev, e);
994 }
995
bcmgenet_set_eee(struct net_device * dev,struct ethtool_eee * e)996 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
997 {
998 struct bcmgenet_priv *priv = netdev_priv(dev);
999 struct ethtool_eee *p = &priv->eee;
1000 int ret = 0;
1001
1002 if (GENET_IS_V1(priv))
1003 return -EOPNOTSUPP;
1004
1005 p->eee_enabled = e->eee_enabled;
1006
1007 if (!p->eee_enabled) {
1008 bcmgenet_eee_enable_set(dev, false);
1009 } else {
1010 ret = phy_init_eee(priv->phydev, 0);
1011 if (ret) {
1012 netif_err(priv, hw, dev, "EEE initialization failed\n");
1013 return ret;
1014 }
1015
1016 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1017 bcmgenet_eee_enable_set(dev, true);
1018 }
1019
1020 return phy_ethtool_set_eee(priv->phydev, e);
1021 }
1022
bcmgenet_nway_reset(struct net_device * dev)1023 static int bcmgenet_nway_reset(struct net_device *dev)
1024 {
1025 struct bcmgenet_priv *priv = netdev_priv(dev);
1026
1027 return genphy_restart_aneg(priv->phydev);
1028 }
1029
1030 /* standard ethtool support functions. */
1031 static struct ethtool_ops bcmgenet_ethtool_ops = {
1032 .get_strings = bcmgenet_get_strings,
1033 .get_sset_count = bcmgenet_get_sset_count,
1034 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1035 .get_settings = bcmgenet_get_settings,
1036 .set_settings = bcmgenet_set_settings,
1037 .get_drvinfo = bcmgenet_get_drvinfo,
1038 .get_link = ethtool_op_get_link,
1039 .get_msglevel = bcmgenet_get_msglevel,
1040 .set_msglevel = bcmgenet_set_msglevel,
1041 .get_wol = bcmgenet_get_wol,
1042 .set_wol = bcmgenet_set_wol,
1043 .get_eee = bcmgenet_get_eee,
1044 .set_eee = bcmgenet_set_eee,
1045 .nway_reset = bcmgenet_nway_reset,
1046 .get_coalesce = bcmgenet_get_coalesce,
1047 .set_coalesce = bcmgenet_set_coalesce,
1048 };
1049
1050 /* Power down the unimac, based on mode. */
bcmgenet_power_down(struct bcmgenet_priv * priv,enum bcmgenet_power_mode mode)1051 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1052 enum bcmgenet_power_mode mode)
1053 {
1054 int ret = 0;
1055 u32 reg;
1056
1057 switch (mode) {
1058 case GENET_POWER_CABLE_SENSE:
1059 phy_detach(priv->phydev);
1060 break;
1061
1062 case GENET_POWER_WOL_MAGIC:
1063 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1064 break;
1065
1066 case GENET_POWER_PASSIVE:
1067 /* Power down LED */
1068 if (priv->hw_params->flags & GENET_HAS_EXT) {
1069 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1070 reg |= (EXT_PWR_DOWN_PHY |
1071 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1072 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1073
1074 bcmgenet_phy_power_set(priv->dev, false);
1075 }
1076 break;
1077 default:
1078 break;
1079 }
1080
1081 return ret;
1082 }
1083
bcmgenet_power_up(struct bcmgenet_priv * priv,enum bcmgenet_power_mode mode)1084 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1085 enum bcmgenet_power_mode mode)
1086 {
1087 u32 reg;
1088
1089 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1090 return;
1091
1092 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1093
1094 switch (mode) {
1095 case GENET_POWER_PASSIVE:
1096 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
1097 EXT_PWR_DOWN_BIAS | EXT_ENERGY_DET_MASK);
1098 /* fallthrough */
1099 case GENET_POWER_CABLE_SENSE:
1100 /* enable APD */
1101 reg |= EXT_PWR_DN_EN_LD;
1102 break;
1103 case GENET_POWER_WOL_MAGIC:
1104 bcmgenet_wol_power_up_cfg(priv, mode);
1105 return;
1106 default:
1107 break;
1108 }
1109
1110 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1111 if (mode == GENET_POWER_PASSIVE) {
1112 bcmgenet_phy_power_set(priv->dev, true);
1113 bcmgenet_mii_reset(priv->dev);
1114 }
1115 }
1116
1117 /* ioctl handle special commands that are not present in ethtool. */
bcmgenet_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1118 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1119 {
1120 struct bcmgenet_priv *priv = netdev_priv(dev);
1121 int val = 0;
1122
1123 if (!netif_running(dev))
1124 return -EINVAL;
1125
1126 switch (cmd) {
1127 case SIOCGMIIPHY:
1128 case SIOCGMIIREG:
1129 case SIOCSMIIREG:
1130 if (!priv->phydev)
1131 val = -ENODEV;
1132 else
1133 val = phy_mii_ioctl(priv->phydev, rq, cmd);
1134 break;
1135
1136 default:
1137 val = -EINVAL;
1138 break;
1139 }
1140
1141 return val;
1142 }
1143
bcmgenet_get_txcb(struct bcmgenet_priv * priv,struct bcmgenet_tx_ring * ring)1144 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1145 struct bcmgenet_tx_ring *ring)
1146 {
1147 struct enet_cb *tx_cb_ptr;
1148
1149 tx_cb_ptr = ring->cbs;
1150 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1151
1152 /* Advancing local write pointer */
1153 if (ring->write_ptr == ring->end_ptr)
1154 ring->write_ptr = ring->cb_ptr;
1155 else
1156 ring->write_ptr++;
1157
1158 return tx_cb_ptr;
1159 }
1160
1161 /* Simple helper to free a control block's resources */
bcmgenet_free_cb(struct enet_cb * cb)1162 static void bcmgenet_free_cb(struct enet_cb *cb)
1163 {
1164 dev_kfree_skb_any(cb->skb);
1165 cb->skb = NULL;
1166 dma_unmap_addr_set(cb, dma_addr, 0);
1167 }
1168
bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring * ring)1169 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1170 {
1171 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1172 INTRL2_CPU_MASK_SET);
1173 }
1174
bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring * ring)1175 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1176 {
1177 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1178 INTRL2_CPU_MASK_CLEAR);
1179 }
1180
bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring * ring)1181 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1182 {
1183 bcmgenet_intrl2_1_writel(ring->priv,
1184 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1185 INTRL2_CPU_MASK_SET);
1186 }
1187
bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring * ring)1188 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1189 {
1190 bcmgenet_intrl2_1_writel(ring->priv,
1191 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1192 INTRL2_CPU_MASK_CLEAR);
1193 }
1194
bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring * ring)1195 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1196 {
1197 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1198 INTRL2_CPU_MASK_SET);
1199 }
1200
bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring * ring)1201 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1202 {
1203 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1204 INTRL2_CPU_MASK_CLEAR);
1205 }
1206
bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring * ring)1207 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1208 {
1209 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1210 INTRL2_CPU_MASK_CLEAR);
1211 }
1212
bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring * ring)1213 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1214 {
1215 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1216 INTRL2_CPU_MASK_SET);
1217 }
1218
1219 /* Unlocked version of the reclaim routine */
__bcmgenet_tx_reclaim(struct net_device * dev,struct bcmgenet_tx_ring * ring)1220 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1221 struct bcmgenet_tx_ring *ring)
1222 {
1223 struct bcmgenet_priv *priv = netdev_priv(dev);
1224 struct device *kdev = &priv->pdev->dev;
1225 struct enet_cb *tx_cb_ptr;
1226 struct netdev_queue *txq;
1227 unsigned int pkts_compl = 0;
1228 unsigned int c_index;
1229 unsigned int txbds_ready;
1230 unsigned int txbds_processed = 0;
1231
1232 /* Compute how many buffers are transmitted since last xmit call */
1233 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
1234 c_index &= DMA_C_INDEX_MASK;
1235
1236 if (likely(c_index >= ring->c_index))
1237 txbds_ready = c_index - ring->c_index;
1238 else
1239 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1240
1241 netif_dbg(priv, tx_done, dev,
1242 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1243 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1244
1245 /* Reclaim transmitted buffers */
1246 while (txbds_processed < txbds_ready) {
1247 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1248 if (tx_cb_ptr->skb) {
1249 pkts_compl++;
1250 dev->stats.tx_packets++;
1251 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1252 dma_unmap_single(kdev,
1253 dma_unmap_addr(tx_cb_ptr, dma_addr),
1254 dma_unmap_len(tx_cb_ptr, dma_len),
1255 DMA_TO_DEVICE);
1256 bcmgenet_free_cb(tx_cb_ptr);
1257 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1258 dev->stats.tx_bytes +=
1259 dma_unmap_len(tx_cb_ptr, dma_len);
1260 dma_unmap_page(kdev,
1261 dma_unmap_addr(tx_cb_ptr, dma_addr),
1262 dma_unmap_len(tx_cb_ptr, dma_len),
1263 DMA_TO_DEVICE);
1264 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1265 }
1266
1267 txbds_processed++;
1268 if (likely(ring->clean_ptr < ring->end_ptr))
1269 ring->clean_ptr++;
1270 else
1271 ring->clean_ptr = ring->cb_ptr;
1272 }
1273
1274 ring->free_bds += txbds_processed;
1275 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1276
1277 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1278 txq = netdev_get_tx_queue(dev, ring->queue);
1279 if (netif_tx_queue_stopped(txq))
1280 netif_tx_wake_queue(txq);
1281 }
1282
1283 return pkts_compl;
1284 }
1285
bcmgenet_tx_reclaim(struct net_device * dev,struct bcmgenet_tx_ring * ring)1286 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1287 struct bcmgenet_tx_ring *ring)
1288 {
1289 unsigned int released;
1290 unsigned long flags;
1291
1292 spin_lock_irqsave(&ring->lock, flags);
1293 released = __bcmgenet_tx_reclaim(dev, ring);
1294 spin_unlock_irqrestore(&ring->lock, flags);
1295
1296 return released;
1297 }
1298
bcmgenet_tx_poll(struct napi_struct * napi,int budget)1299 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1300 {
1301 struct bcmgenet_tx_ring *ring =
1302 container_of(napi, struct bcmgenet_tx_ring, napi);
1303 unsigned int work_done = 0;
1304
1305 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1306
1307 if (work_done == 0) {
1308 napi_complete(napi);
1309 ring->int_enable(ring);
1310
1311 return 0;
1312 }
1313
1314 return budget;
1315 }
1316
bcmgenet_tx_reclaim_all(struct net_device * dev)1317 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1318 {
1319 struct bcmgenet_priv *priv = netdev_priv(dev);
1320 int i;
1321
1322 if (netif_is_multiqueue(dev)) {
1323 for (i = 0; i < priv->hw_params->tx_queues; i++)
1324 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1325 }
1326
1327 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1328 }
1329
1330 /* Transmits a single SKB (either head of a fragment or a single SKB)
1331 * caller must hold priv->lock
1332 */
bcmgenet_xmit_single(struct net_device * dev,struct sk_buff * skb,u16 dma_desc_flags,struct bcmgenet_tx_ring * ring)1333 static int bcmgenet_xmit_single(struct net_device *dev,
1334 struct sk_buff *skb,
1335 u16 dma_desc_flags,
1336 struct bcmgenet_tx_ring *ring)
1337 {
1338 struct bcmgenet_priv *priv = netdev_priv(dev);
1339 struct device *kdev = &priv->pdev->dev;
1340 struct enet_cb *tx_cb_ptr;
1341 unsigned int skb_len;
1342 dma_addr_t mapping;
1343 u32 length_status;
1344 int ret;
1345
1346 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1347
1348 if (unlikely(!tx_cb_ptr))
1349 BUG();
1350
1351 tx_cb_ptr->skb = skb;
1352
1353 skb_len = skb_headlen(skb);
1354
1355 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1356 ret = dma_mapping_error(kdev, mapping);
1357 if (ret) {
1358 priv->mib.tx_dma_failed++;
1359 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1360 dev_kfree_skb(skb);
1361 return ret;
1362 }
1363
1364 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1365 dma_unmap_len_set(tx_cb_ptr, dma_len, skb_len);
1366 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1367 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1368 DMA_TX_APPEND_CRC;
1369
1370 if (skb->ip_summed == CHECKSUM_PARTIAL)
1371 length_status |= DMA_TX_DO_CSUM;
1372
1373 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1374
1375 return 0;
1376 }
1377
1378 /* Transmit a SKB fragment */
bcmgenet_xmit_frag(struct net_device * dev,skb_frag_t * frag,u16 dma_desc_flags,struct bcmgenet_tx_ring * ring)1379 static int bcmgenet_xmit_frag(struct net_device *dev,
1380 skb_frag_t *frag,
1381 u16 dma_desc_flags,
1382 struct bcmgenet_tx_ring *ring)
1383 {
1384 struct bcmgenet_priv *priv = netdev_priv(dev);
1385 struct device *kdev = &priv->pdev->dev;
1386 struct enet_cb *tx_cb_ptr;
1387 dma_addr_t mapping;
1388 int ret;
1389
1390 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1391
1392 if (unlikely(!tx_cb_ptr))
1393 BUG();
1394 tx_cb_ptr->skb = NULL;
1395
1396 mapping = skb_frag_dma_map(kdev, frag, 0,
1397 skb_frag_size(frag), DMA_TO_DEVICE);
1398 ret = dma_mapping_error(kdev, mapping);
1399 if (ret) {
1400 priv->mib.tx_dma_failed++;
1401 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1402 __func__);
1403 return ret;
1404 }
1405
1406 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1407 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1408
1409 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1410 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1411 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1412
1413 return 0;
1414 }
1415
1416 /* Reallocate the SKB to put enough headroom in front of it and insert
1417 * the transmit checksum offsets in the descriptors
1418 */
bcmgenet_put_tx_csum(struct net_device * dev,struct sk_buff * skb)1419 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1420 struct sk_buff *skb)
1421 {
1422 struct status_64 *status = NULL;
1423 struct sk_buff *new_skb;
1424 u16 offset;
1425 u8 ip_proto;
1426 u16 ip_ver;
1427 u32 tx_csum_info;
1428
1429 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1430 /* If 64 byte status block enabled, must make sure skb has
1431 * enough headroom for us to insert 64B status block.
1432 */
1433 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1434 dev_kfree_skb(skb);
1435 if (!new_skb) {
1436 dev->stats.tx_dropped++;
1437 return NULL;
1438 }
1439 skb = new_skb;
1440 }
1441
1442 skb_push(skb, sizeof(*status));
1443 status = (struct status_64 *)skb->data;
1444
1445 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1446 ip_ver = htons(skb->protocol);
1447 switch (ip_ver) {
1448 case ETH_P_IP:
1449 ip_proto = ip_hdr(skb)->protocol;
1450 break;
1451 case ETH_P_IPV6:
1452 ip_proto = ipv6_hdr(skb)->nexthdr;
1453 break;
1454 default:
1455 return skb;
1456 }
1457
1458 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1459 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1460 (offset + skb->csum_offset);
1461
1462 /* Set the length valid bit for TCP and UDP and just set
1463 * the special UDP flag for IPv4, else just set to 0.
1464 */
1465 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1466 tx_csum_info |= STATUS_TX_CSUM_LV;
1467 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1468 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1469 } else {
1470 tx_csum_info = 0;
1471 }
1472
1473 status->tx_csum_info = tx_csum_info;
1474 }
1475
1476 return skb;
1477 }
1478
bcmgenet_xmit(struct sk_buff * skb,struct net_device * dev)1479 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1480 {
1481 struct bcmgenet_priv *priv = netdev_priv(dev);
1482 struct bcmgenet_tx_ring *ring = NULL;
1483 struct netdev_queue *txq;
1484 unsigned long flags = 0;
1485 int nr_frags, index;
1486 u16 dma_desc_flags;
1487 int ret;
1488 int i;
1489
1490 index = skb_get_queue_mapping(skb);
1491 /* Mapping strategy:
1492 * queue_mapping = 0, unclassified, packet xmited through ring16
1493 * queue_mapping = 1, goes to ring 0. (highest priority queue
1494 * queue_mapping = 2, goes to ring 1.
1495 * queue_mapping = 3, goes to ring 2.
1496 * queue_mapping = 4, goes to ring 3.
1497 */
1498 if (index == 0)
1499 index = DESC_INDEX;
1500 else
1501 index -= 1;
1502
1503 nr_frags = skb_shinfo(skb)->nr_frags;
1504 ring = &priv->tx_rings[index];
1505 txq = netdev_get_tx_queue(dev, ring->queue);
1506
1507 spin_lock_irqsave(&ring->lock, flags);
1508 if (ring->free_bds <= nr_frags + 1) {
1509 netif_tx_stop_queue(txq);
1510 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1511 __func__, index, ring->queue);
1512 ret = NETDEV_TX_BUSY;
1513 goto out;
1514 }
1515
1516 if (skb_padto(skb, ETH_ZLEN)) {
1517 ret = NETDEV_TX_OK;
1518 goto out;
1519 }
1520
1521 /* set the SKB transmit checksum */
1522 if (priv->desc_64b_en) {
1523 skb = bcmgenet_put_tx_csum(dev, skb);
1524 if (!skb) {
1525 ret = NETDEV_TX_OK;
1526 goto out;
1527 }
1528 }
1529
1530 dma_desc_flags = DMA_SOP;
1531 if (nr_frags == 0)
1532 dma_desc_flags |= DMA_EOP;
1533
1534 /* Transmit single SKB or head of fragment list */
1535 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1536 if (ret) {
1537 ret = NETDEV_TX_OK;
1538 goto out;
1539 }
1540
1541 /* xmit fragment */
1542 for (i = 0; i < nr_frags; i++) {
1543 ret = bcmgenet_xmit_frag(dev,
1544 &skb_shinfo(skb)->frags[i],
1545 (i == nr_frags - 1) ? DMA_EOP : 0,
1546 ring);
1547 if (ret) {
1548 ret = NETDEV_TX_OK;
1549 goto out;
1550 }
1551 }
1552
1553 skb_tx_timestamp(skb);
1554
1555 /* Decrement total BD count and advance our write pointer */
1556 ring->free_bds -= nr_frags + 1;
1557 ring->prod_index += nr_frags + 1;
1558 ring->prod_index &= DMA_P_INDEX_MASK;
1559
1560 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1561 netif_tx_stop_queue(txq);
1562
1563 if (!skb->xmit_more || netif_xmit_stopped(txq))
1564 /* Packets are ready, update producer index */
1565 bcmgenet_tdma_ring_writel(priv, ring->index,
1566 ring->prod_index, TDMA_PROD_INDEX);
1567 out:
1568 spin_unlock_irqrestore(&ring->lock, flags);
1569
1570 return ret;
1571 }
1572
bcmgenet_rx_refill(struct bcmgenet_priv * priv,struct enet_cb * cb)1573 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1574 struct enet_cb *cb)
1575 {
1576 struct device *kdev = &priv->pdev->dev;
1577 struct sk_buff *skb;
1578 struct sk_buff *rx_skb;
1579 dma_addr_t mapping;
1580
1581 /* Allocate a new Rx skb */
1582 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
1583 GFP_ATOMIC | __GFP_NOWARN);
1584 if (!skb) {
1585 priv->mib.alloc_rx_buff_failed++;
1586 netif_err(priv, rx_err, priv->dev,
1587 "%s: Rx skb allocation failed\n", __func__);
1588 return NULL;
1589 }
1590
1591 /* DMA-map the new Rx skb */
1592 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1593 DMA_FROM_DEVICE);
1594 if (dma_mapping_error(kdev, mapping)) {
1595 priv->mib.rx_dma_failed++;
1596 dev_kfree_skb_any(skb);
1597 netif_err(priv, rx_err, priv->dev,
1598 "%s: Rx skb DMA mapping failed\n", __func__);
1599 return NULL;
1600 }
1601
1602 /* Grab the current Rx skb from the ring and DMA-unmap it */
1603 rx_skb = cb->skb;
1604 if (likely(rx_skb))
1605 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1606 priv->rx_buf_len, DMA_FROM_DEVICE);
1607
1608 /* Put the new Rx skb on the ring */
1609 cb->skb = skb;
1610 dma_unmap_addr_set(cb, dma_addr, mapping);
1611 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1612
1613 /* Return the current Rx skb to caller */
1614 return rx_skb;
1615 }
1616
1617 /* bcmgenet_desc_rx - descriptor based rx process.
1618 * this could be called from bottom half, or from NAPI polling method.
1619 */
bcmgenet_desc_rx(struct bcmgenet_rx_ring * ring,unsigned int budget)1620 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1621 unsigned int budget)
1622 {
1623 struct bcmgenet_priv *priv = ring->priv;
1624 struct net_device *dev = priv->dev;
1625 struct enet_cb *cb;
1626 struct sk_buff *skb;
1627 u32 dma_length_status;
1628 unsigned long dma_flag;
1629 int len;
1630 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1631 unsigned int p_index;
1632 unsigned int discards;
1633 unsigned int chksum_ok = 0;
1634
1635 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1636
1637 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1638 DMA_P_INDEX_DISCARD_CNT_MASK;
1639 if (discards > ring->old_discards) {
1640 discards = discards - ring->old_discards;
1641 dev->stats.rx_missed_errors += discards;
1642 dev->stats.rx_errors += discards;
1643 ring->old_discards += discards;
1644
1645 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1646 if (ring->old_discards >= 0xC000) {
1647 ring->old_discards = 0;
1648 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1649 RDMA_PROD_INDEX);
1650 }
1651 }
1652
1653 p_index &= DMA_P_INDEX_MASK;
1654
1655 if (likely(p_index >= ring->c_index))
1656 rxpkttoprocess = p_index - ring->c_index;
1657 else
1658 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1659 p_index;
1660
1661 netif_dbg(priv, rx_status, dev,
1662 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1663
1664 while ((rxpktprocessed < rxpkttoprocess) &&
1665 (rxpktprocessed < budget)) {
1666 cb = &priv->rx_cbs[ring->read_ptr];
1667 skb = bcmgenet_rx_refill(priv, cb);
1668
1669 if (unlikely(!skb)) {
1670 dev->stats.rx_dropped++;
1671 goto next;
1672 }
1673
1674 if (!priv->desc_64b_en) {
1675 dma_length_status =
1676 dmadesc_get_length_status(priv, cb->bd_addr);
1677 } else {
1678 struct status_64 *status;
1679
1680 status = (struct status_64 *)skb->data;
1681 dma_length_status = status->length_status;
1682 }
1683
1684 /* DMA flags and length are still valid no matter how
1685 * we got the Receive Status Vector (64B RSB or register)
1686 */
1687 dma_flag = dma_length_status & 0xffff;
1688 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1689
1690 netif_dbg(priv, rx_status, dev,
1691 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1692 __func__, p_index, ring->c_index,
1693 ring->read_ptr, dma_length_status);
1694
1695 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1696 netif_err(priv, rx_status, dev,
1697 "dropping fragmented packet!\n");
1698 dev->stats.rx_errors++;
1699 dev_kfree_skb_any(skb);
1700 goto next;
1701 }
1702
1703 /* report errors */
1704 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1705 DMA_RX_OV |
1706 DMA_RX_NO |
1707 DMA_RX_LG |
1708 DMA_RX_RXER))) {
1709 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1710 (unsigned int)dma_flag);
1711 if (dma_flag & DMA_RX_CRC_ERROR)
1712 dev->stats.rx_crc_errors++;
1713 if (dma_flag & DMA_RX_OV)
1714 dev->stats.rx_over_errors++;
1715 if (dma_flag & DMA_RX_NO)
1716 dev->stats.rx_frame_errors++;
1717 if (dma_flag & DMA_RX_LG)
1718 dev->stats.rx_length_errors++;
1719 dev->stats.rx_errors++;
1720 dev_kfree_skb_any(skb);
1721 goto next;
1722 } /* error packet */
1723
1724 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1725 priv->desc_rxchk_en;
1726
1727 skb_put(skb, len);
1728 if (priv->desc_64b_en) {
1729 skb_pull(skb, 64);
1730 len -= 64;
1731 }
1732
1733 if (likely(chksum_ok))
1734 skb->ip_summed = CHECKSUM_UNNECESSARY;
1735
1736 /* remove hardware 2bytes added for IP alignment */
1737 skb_pull(skb, 2);
1738 len -= 2;
1739
1740 if (priv->crc_fwd_en) {
1741 skb_trim(skb, len - ETH_FCS_LEN);
1742 len -= ETH_FCS_LEN;
1743 }
1744
1745 /*Finish setting up the received SKB and send it to the kernel*/
1746 skb->protocol = eth_type_trans(skb, priv->dev);
1747 dev->stats.rx_packets++;
1748 dev->stats.rx_bytes += len;
1749 if (dma_flag & DMA_RX_MULT)
1750 dev->stats.multicast++;
1751
1752 /* Notify kernel */
1753 napi_gro_receive(&ring->napi, skb);
1754 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1755
1756 next:
1757 rxpktprocessed++;
1758 if (likely(ring->read_ptr < ring->end_ptr))
1759 ring->read_ptr++;
1760 else
1761 ring->read_ptr = ring->cb_ptr;
1762
1763 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1764 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1765 }
1766
1767 return rxpktprocessed;
1768 }
1769
1770 /* Rx NAPI polling method */
bcmgenet_rx_poll(struct napi_struct * napi,int budget)1771 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1772 {
1773 struct bcmgenet_rx_ring *ring = container_of(napi,
1774 struct bcmgenet_rx_ring, napi);
1775 unsigned int work_done;
1776
1777 work_done = bcmgenet_desc_rx(ring, budget);
1778
1779 if (work_done < budget) {
1780 napi_complete(napi);
1781 ring->int_enable(ring);
1782 }
1783
1784 return work_done;
1785 }
1786
1787 /* Assign skb to RX DMA descriptor. */
bcmgenet_alloc_rx_buffers(struct bcmgenet_priv * priv,struct bcmgenet_rx_ring * ring)1788 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1789 struct bcmgenet_rx_ring *ring)
1790 {
1791 struct enet_cb *cb;
1792 struct sk_buff *skb;
1793 int i;
1794
1795 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1796
1797 /* loop here for each buffer needing assign */
1798 for (i = 0; i < ring->size; i++) {
1799 cb = ring->cbs + i;
1800 skb = bcmgenet_rx_refill(priv, cb);
1801 if (skb)
1802 dev_kfree_skb_any(skb);
1803 if (!cb->skb)
1804 return -ENOMEM;
1805 }
1806
1807 return 0;
1808 }
1809
bcmgenet_free_rx_buffers(struct bcmgenet_priv * priv)1810 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1811 {
1812 struct device *kdev = &priv->pdev->dev;
1813 struct enet_cb *cb;
1814 int i;
1815
1816 for (i = 0; i < priv->num_rx_bds; i++) {
1817 cb = &priv->rx_cbs[i];
1818
1819 if (dma_unmap_addr(cb, dma_addr)) {
1820 dma_unmap_single(kdev,
1821 dma_unmap_addr(cb, dma_addr),
1822 priv->rx_buf_len, DMA_FROM_DEVICE);
1823 dma_unmap_addr_set(cb, dma_addr, 0);
1824 }
1825
1826 if (cb->skb)
1827 bcmgenet_free_cb(cb);
1828 }
1829 }
1830
umac_enable_set(struct bcmgenet_priv * priv,u32 mask,bool enable)1831 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1832 {
1833 u32 reg;
1834
1835 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1836 if (enable)
1837 reg |= mask;
1838 else
1839 reg &= ~mask;
1840 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1841
1842 /* UniMAC stops on a packet boundary, wait for a full-size packet
1843 * to be processed
1844 */
1845 if (enable == 0)
1846 usleep_range(1000, 2000);
1847 }
1848
reset_umac(struct bcmgenet_priv * priv)1849 static int reset_umac(struct bcmgenet_priv *priv)
1850 {
1851 struct device *kdev = &priv->pdev->dev;
1852 unsigned int timeout = 0;
1853 u32 reg;
1854
1855 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1856 bcmgenet_rbuf_ctrl_set(priv, 0);
1857 udelay(10);
1858
1859 /* disable MAC while updating its registers */
1860 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1861
1862 /* issue soft reset, wait for it to complete */
1863 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1864 while (timeout++ < 1000) {
1865 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1866 if (!(reg & CMD_SW_RESET))
1867 return 0;
1868
1869 udelay(1);
1870 }
1871
1872 if (timeout == 1000) {
1873 dev_err(kdev,
1874 "timeout waiting for MAC to come out of reset\n");
1875 return -ETIMEDOUT;
1876 }
1877
1878 return 0;
1879 }
1880
bcmgenet_intr_disable(struct bcmgenet_priv * priv)1881 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1882 {
1883 /* Mask all interrupts.*/
1884 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1885 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1886 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1887 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1888 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1889 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1890 }
1891
bcmgenet_link_intr_enable(struct bcmgenet_priv * priv)1892 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1893 {
1894 u32 int0_enable = 0;
1895
1896 /* Monitor cable plug/unplugged event for internal PHY, external PHY
1897 * and MoCA PHY
1898 */
1899 if (priv->internal_phy) {
1900 int0_enable |= UMAC_IRQ_LINK_EVENT;
1901 } else if (priv->ext_phy) {
1902 int0_enable |= UMAC_IRQ_LINK_EVENT;
1903 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1904 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1905 int0_enable |= UMAC_IRQ_LINK_EVENT;
1906 }
1907 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1908 }
1909
init_umac(struct bcmgenet_priv * priv)1910 static int init_umac(struct bcmgenet_priv *priv)
1911 {
1912 struct device *kdev = &priv->pdev->dev;
1913 int ret;
1914 u32 reg;
1915 u32 int0_enable = 0;
1916 u32 int1_enable = 0;
1917 int i;
1918
1919 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1920
1921 ret = reset_umac(priv);
1922 if (ret)
1923 return ret;
1924
1925 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1926 /* clear tx/rx counter */
1927 bcmgenet_umac_writel(priv,
1928 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1929 UMAC_MIB_CTRL);
1930 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1931
1932 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1933
1934 /* init rx registers, enable ip header optimization */
1935 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1936 reg |= RBUF_ALIGN_2B;
1937 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1938
1939 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1940 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1941
1942 bcmgenet_intr_disable(priv);
1943
1944 /* Enable Rx default queue 16 interrupts */
1945 int0_enable |= UMAC_IRQ_RXDMA_DONE;
1946
1947 /* Enable Tx default queue 16 interrupts */
1948 int0_enable |= UMAC_IRQ_TXDMA_DONE;
1949
1950 /* Configure backpressure vectors for MoCA */
1951 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1952 reg = bcmgenet_bp_mc_get(priv);
1953 reg |= BIT(priv->hw_params->bp_in_en_shift);
1954
1955 /* bp_mask: back pressure mask */
1956 if (netif_is_multiqueue(priv->dev))
1957 reg |= priv->hw_params->bp_in_mask;
1958 else
1959 reg &= ~priv->hw_params->bp_in_mask;
1960 bcmgenet_bp_mc_set(priv, reg);
1961 }
1962
1963 /* Enable MDIO interrupts on GENET v3+ */
1964 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1965 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1966
1967 /* Enable Rx priority queue interrupts */
1968 for (i = 0; i < priv->hw_params->rx_queues; ++i)
1969 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1970
1971 /* Enable Tx priority queue interrupts */
1972 for (i = 0; i < priv->hw_params->tx_queues; ++i)
1973 int1_enable |= (1 << i);
1974
1975 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1976 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
1977
1978 /* Enable rx/tx engine.*/
1979 dev_dbg(kdev, "done init umac\n");
1980
1981 return 0;
1982 }
1983
1984 /* Initialize a Tx ring along with corresponding hardware registers */
bcmgenet_init_tx_ring(struct bcmgenet_priv * priv,unsigned int index,unsigned int size,unsigned int start_ptr,unsigned int end_ptr)1985 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1986 unsigned int index, unsigned int size,
1987 unsigned int start_ptr, unsigned int end_ptr)
1988 {
1989 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1990 u32 words_per_bd = WORDS_PER_BD(priv);
1991 u32 flow_period_val = 0;
1992
1993 spin_lock_init(&ring->lock);
1994 ring->priv = priv;
1995 ring->index = index;
1996 if (index == DESC_INDEX) {
1997 ring->queue = 0;
1998 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1999 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2000 } else {
2001 ring->queue = index + 1;
2002 ring->int_enable = bcmgenet_tx_ring_int_enable;
2003 ring->int_disable = bcmgenet_tx_ring_int_disable;
2004 }
2005 ring->cbs = priv->tx_cbs + start_ptr;
2006 ring->size = size;
2007 ring->clean_ptr = start_ptr;
2008 ring->c_index = 0;
2009 ring->free_bds = size;
2010 ring->write_ptr = start_ptr;
2011 ring->cb_ptr = start_ptr;
2012 ring->end_ptr = end_ptr - 1;
2013 ring->prod_index = 0;
2014
2015 /* Set flow period for ring != 16 */
2016 if (index != DESC_INDEX)
2017 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2018
2019 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2020 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2021 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2022 /* Disable rate control for now */
2023 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2024 TDMA_FLOW_PERIOD);
2025 bcmgenet_tdma_ring_writel(priv, index,
2026 ((size << DMA_RING_SIZE_SHIFT) |
2027 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2028
2029 /* Set start and end address, read and write pointers */
2030 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2031 DMA_START_ADDR);
2032 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2033 TDMA_READ_PTR);
2034 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2035 TDMA_WRITE_PTR);
2036 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2037 DMA_END_ADDR);
2038 }
2039
2040 /* Initialize a RDMA ring */
bcmgenet_init_rx_ring(struct bcmgenet_priv * priv,unsigned int index,unsigned int size,unsigned int start_ptr,unsigned int end_ptr)2041 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2042 unsigned int index, unsigned int size,
2043 unsigned int start_ptr, unsigned int end_ptr)
2044 {
2045 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2046 u32 words_per_bd = WORDS_PER_BD(priv);
2047 int ret;
2048
2049 ring->priv = priv;
2050 ring->index = index;
2051 if (index == DESC_INDEX) {
2052 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2053 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2054 } else {
2055 ring->int_enable = bcmgenet_rx_ring_int_enable;
2056 ring->int_disable = bcmgenet_rx_ring_int_disable;
2057 }
2058 ring->cbs = priv->rx_cbs + start_ptr;
2059 ring->size = size;
2060 ring->c_index = 0;
2061 ring->read_ptr = start_ptr;
2062 ring->cb_ptr = start_ptr;
2063 ring->end_ptr = end_ptr - 1;
2064
2065 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2066 if (ret)
2067 return ret;
2068
2069 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2070 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2071 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2072 bcmgenet_rdma_ring_writel(priv, index,
2073 ((size << DMA_RING_SIZE_SHIFT) |
2074 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2075 bcmgenet_rdma_ring_writel(priv, index,
2076 (DMA_FC_THRESH_LO <<
2077 DMA_XOFF_THRESHOLD_SHIFT) |
2078 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2079
2080 /* Set start and end address, read and write pointers */
2081 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2082 DMA_START_ADDR);
2083 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2084 RDMA_READ_PTR);
2085 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2086 RDMA_WRITE_PTR);
2087 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2088 DMA_END_ADDR);
2089
2090 return ret;
2091 }
2092
bcmgenet_init_tx_napi(struct bcmgenet_priv * priv)2093 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2094 {
2095 unsigned int i;
2096 struct bcmgenet_tx_ring *ring;
2097
2098 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2099 ring = &priv->tx_rings[i];
2100 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2101 }
2102
2103 ring = &priv->tx_rings[DESC_INDEX];
2104 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2105 }
2106
bcmgenet_enable_tx_napi(struct bcmgenet_priv * priv)2107 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2108 {
2109 unsigned int i;
2110 struct bcmgenet_tx_ring *ring;
2111
2112 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2113 ring = &priv->tx_rings[i];
2114 napi_enable(&ring->napi);
2115 }
2116
2117 ring = &priv->tx_rings[DESC_INDEX];
2118 napi_enable(&ring->napi);
2119 }
2120
bcmgenet_disable_tx_napi(struct bcmgenet_priv * priv)2121 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2122 {
2123 unsigned int i;
2124 struct bcmgenet_tx_ring *ring;
2125
2126 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2127 ring = &priv->tx_rings[i];
2128 napi_disable(&ring->napi);
2129 }
2130
2131 ring = &priv->tx_rings[DESC_INDEX];
2132 napi_disable(&ring->napi);
2133 }
2134
bcmgenet_fini_tx_napi(struct bcmgenet_priv * priv)2135 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2136 {
2137 unsigned int i;
2138 struct bcmgenet_tx_ring *ring;
2139
2140 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2141 ring = &priv->tx_rings[i];
2142 netif_napi_del(&ring->napi);
2143 }
2144
2145 ring = &priv->tx_rings[DESC_INDEX];
2146 netif_napi_del(&ring->napi);
2147 }
2148
2149 /* Initialize Tx queues
2150 *
2151 * Queues 0-3 are priority-based, each one has 32 descriptors,
2152 * with queue 0 being the highest priority queue.
2153 *
2154 * Queue 16 is the default Tx queue with
2155 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2156 *
2157 * The transmit control block pool is then partitioned as follows:
2158 * - Tx queue 0 uses tx_cbs[0..31]
2159 * - Tx queue 1 uses tx_cbs[32..63]
2160 * - Tx queue 2 uses tx_cbs[64..95]
2161 * - Tx queue 3 uses tx_cbs[96..127]
2162 * - Tx queue 16 uses tx_cbs[128..255]
2163 */
bcmgenet_init_tx_queues(struct net_device * dev)2164 static void bcmgenet_init_tx_queues(struct net_device *dev)
2165 {
2166 struct bcmgenet_priv *priv = netdev_priv(dev);
2167 u32 i, dma_enable;
2168 u32 dma_ctrl, ring_cfg;
2169 u32 dma_priority[3] = {0, 0, 0};
2170
2171 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2172 dma_enable = dma_ctrl & DMA_EN;
2173 dma_ctrl &= ~DMA_EN;
2174 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2175
2176 dma_ctrl = 0;
2177 ring_cfg = 0;
2178
2179 /* Enable strict priority arbiter mode */
2180 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2181
2182 /* Initialize Tx priority queues */
2183 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2184 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2185 i * priv->hw_params->tx_bds_per_q,
2186 (i + 1) * priv->hw_params->tx_bds_per_q);
2187 ring_cfg |= (1 << i);
2188 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2189 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2190 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2191 }
2192
2193 /* Initialize Tx default queue 16 */
2194 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2195 priv->hw_params->tx_queues *
2196 priv->hw_params->tx_bds_per_q,
2197 TOTAL_DESC);
2198 ring_cfg |= (1 << DESC_INDEX);
2199 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2200 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2201 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2202 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2203
2204 /* Set Tx queue priorities */
2205 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2206 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2207 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2208
2209 /* Initialize Tx NAPI */
2210 bcmgenet_init_tx_napi(priv);
2211
2212 /* Enable Tx queues */
2213 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2214
2215 /* Enable Tx DMA */
2216 if (dma_enable)
2217 dma_ctrl |= DMA_EN;
2218 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2219 }
2220
bcmgenet_init_rx_napi(struct bcmgenet_priv * priv)2221 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2222 {
2223 unsigned int i;
2224 struct bcmgenet_rx_ring *ring;
2225
2226 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2227 ring = &priv->rx_rings[i];
2228 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2229 }
2230
2231 ring = &priv->rx_rings[DESC_INDEX];
2232 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2233 }
2234
bcmgenet_enable_rx_napi(struct bcmgenet_priv * priv)2235 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2236 {
2237 unsigned int i;
2238 struct bcmgenet_rx_ring *ring;
2239
2240 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2241 ring = &priv->rx_rings[i];
2242 napi_enable(&ring->napi);
2243 }
2244
2245 ring = &priv->rx_rings[DESC_INDEX];
2246 napi_enable(&ring->napi);
2247 }
2248
bcmgenet_disable_rx_napi(struct bcmgenet_priv * priv)2249 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2250 {
2251 unsigned int i;
2252 struct bcmgenet_rx_ring *ring;
2253
2254 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2255 ring = &priv->rx_rings[i];
2256 napi_disable(&ring->napi);
2257 }
2258
2259 ring = &priv->rx_rings[DESC_INDEX];
2260 napi_disable(&ring->napi);
2261 }
2262
bcmgenet_fini_rx_napi(struct bcmgenet_priv * priv)2263 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2264 {
2265 unsigned int i;
2266 struct bcmgenet_rx_ring *ring;
2267
2268 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2269 ring = &priv->rx_rings[i];
2270 netif_napi_del(&ring->napi);
2271 }
2272
2273 ring = &priv->rx_rings[DESC_INDEX];
2274 netif_napi_del(&ring->napi);
2275 }
2276
2277 /* Initialize Rx queues
2278 *
2279 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2280 * used to direct traffic to these queues.
2281 *
2282 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2283 */
bcmgenet_init_rx_queues(struct net_device * dev)2284 static int bcmgenet_init_rx_queues(struct net_device *dev)
2285 {
2286 struct bcmgenet_priv *priv = netdev_priv(dev);
2287 u32 i;
2288 u32 dma_enable;
2289 u32 dma_ctrl;
2290 u32 ring_cfg;
2291 int ret;
2292
2293 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2294 dma_enable = dma_ctrl & DMA_EN;
2295 dma_ctrl &= ~DMA_EN;
2296 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2297
2298 dma_ctrl = 0;
2299 ring_cfg = 0;
2300
2301 /* Initialize Rx priority queues */
2302 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2303 ret = bcmgenet_init_rx_ring(priv, i,
2304 priv->hw_params->rx_bds_per_q,
2305 i * priv->hw_params->rx_bds_per_q,
2306 (i + 1) *
2307 priv->hw_params->rx_bds_per_q);
2308 if (ret)
2309 return ret;
2310
2311 ring_cfg |= (1 << i);
2312 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2313 }
2314
2315 /* Initialize Rx default queue 16 */
2316 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2317 priv->hw_params->rx_queues *
2318 priv->hw_params->rx_bds_per_q,
2319 TOTAL_DESC);
2320 if (ret)
2321 return ret;
2322
2323 ring_cfg |= (1 << DESC_INDEX);
2324 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2325
2326 /* Initialize Rx NAPI */
2327 bcmgenet_init_rx_napi(priv);
2328
2329 /* Enable rings */
2330 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2331
2332 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2333 if (dma_enable)
2334 dma_ctrl |= DMA_EN;
2335 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2336
2337 return 0;
2338 }
2339
bcmgenet_dma_teardown(struct bcmgenet_priv * priv)2340 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2341 {
2342 int ret = 0;
2343 int timeout = 0;
2344 u32 reg;
2345 u32 dma_ctrl;
2346 int i;
2347
2348 /* Disable TDMA to stop add more frames in TX DMA */
2349 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2350 reg &= ~DMA_EN;
2351 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2352
2353 /* Check TDMA status register to confirm TDMA is disabled */
2354 while (timeout++ < DMA_TIMEOUT_VAL) {
2355 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2356 if (reg & DMA_DISABLED)
2357 break;
2358
2359 udelay(1);
2360 }
2361
2362 if (timeout == DMA_TIMEOUT_VAL) {
2363 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2364 ret = -ETIMEDOUT;
2365 }
2366
2367 /* Wait 10ms for packet drain in both tx and rx dma */
2368 usleep_range(10000, 20000);
2369
2370 /* Disable RDMA */
2371 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2372 reg &= ~DMA_EN;
2373 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2374
2375 timeout = 0;
2376 /* Check RDMA status register to confirm RDMA is disabled */
2377 while (timeout++ < DMA_TIMEOUT_VAL) {
2378 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2379 if (reg & DMA_DISABLED)
2380 break;
2381
2382 udelay(1);
2383 }
2384
2385 if (timeout == DMA_TIMEOUT_VAL) {
2386 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2387 ret = -ETIMEDOUT;
2388 }
2389
2390 dma_ctrl = 0;
2391 for (i = 0; i < priv->hw_params->rx_queues; i++)
2392 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2393 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2394 reg &= ~dma_ctrl;
2395 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2396
2397 dma_ctrl = 0;
2398 for (i = 0; i < priv->hw_params->tx_queues; i++)
2399 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2400 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2401 reg &= ~dma_ctrl;
2402 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2403
2404 return ret;
2405 }
2406
bcmgenet_fini_dma(struct bcmgenet_priv * priv)2407 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2408 {
2409 int i;
2410
2411 bcmgenet_fini_rx_napi(priv);
2412 bcmgenet_fini_tx_napi(priv);
2413
2414 /* disable DMA */
2415 bcmgenet_dma_teardown(priv);
2416
2417 for (i = 0; i < priv->num_tx_bds; i++) {
2418 if (priv->tx_cbs[i].skb != NULL) {
2419 dev_kfree_skb(priv->tx_cbs[i].skb);
2420 priv->tx_cbs[i].skb = NULL;
2421 }
2422 }
2423
2424 bcmgenet_free_rx_buffers(priv);
2425 kfree(priv->rx_cbs);
2426 kfree(priv->tx_cbs);
2427 }
2428
2429 /* init_edma: Initialize DMA control register */
bcmgenet_init_dma(struct bcmgenet_priv * priv)2430 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2431 {
2432 int ret;
2433 unsigned int i;
2434 struct enet_cb *cb;
2435
2436 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2437
2438 /* Initialize common Rx ring structures */
2439 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2440 priv->num_rx_bds = TOTAL_DESC;
2441 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2442 GFP_KERNEL);
2443 if (!priv->rx_cbs)
2444 return -ENOMEM;
2445
2446 for (i = 0; i < priv->num_rx_bds; i++) {
2447 cb = priv->rx_cbs + i;
2448 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2449 }
2450
2451 /* Initialize common TX ring structures */
2452 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2453 priv->num_tx_bds = TOTAL_DESC;
2454 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2455 GFP_KERNEL);
2456 if (!priv->tx_cbs) {
2457 kfree(priv->rx_cbs);
2458 return -ENOMEM;
2459 }
2460
2461 for (i = 0; i < priv->num_tx_bds; i++) {
2462 cb = priv->tx_cbs + i;
2463 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2464 }
2465
2466 /* Init rDma */
2467 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2468
2469 /* Initialize Rx queues */
2470 ret = bcmgenet_init_rx_queues(priv->dev);
2471 if (ret) {
2472 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2473 bcmgenet_free_rx_buffers(priv);
2474 kfree(priv->rx_cbs);
2475 kfree(priv->tx_cbs);
2476 return ret;
2477 }
2478
2479 /* Init tDma */
2480 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2481
2482 /* Initialize Tx queues */
2483 bcmgenet_init_tx_queues(priv->dev);
2484
2485 return 0;
2486 }
2487
2488 /* Interrupt bottom half */
bcmgenet_irq_task(struct work_struct * work)2489 static void bcmgenet_irq_task(struct work_struct *work)
2490 {
2491 struct bcmgenet_priv *priv = container_of(
2492 work, struct bcmgenet_priv, bcmgenet_irq_work);
2493
2494 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2495
2496 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2497 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2498 netif_dbg(priv, wol, priv->dev,
2499 "magic packet detected, waking up\n");
2500 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2501 }
2502
2503 /* Link UP/DOWN event */
2504 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2505 (priv->irq0_stat & UMAC_IRQ_LINK_EVENT)) {
2506 phy_mac_interrupt(priv->phydev,
2507 !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
2508 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
2509 }
2510 }
2511
2512 /* bcmgenet_isr1: handle Rx and Tx priority queues */
bcmgenet_isr1(int irq,void * dev_id)2513 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2514 {
2515 struct bcmgenet_priv *priv = dev_id;
2516 struct bcmgenet_rx_ring *rx_ring;
2517 struct bcmgenet_tx_ring *tx_ring;
2518 unsigned int index;
2519
2520 /* Save irq status for bottom-half processing. */
2521 priv->irq1_stat =
2522 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2523 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2524
2525 /* clear interrupts */
2526 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2527
2528 netif_dbg(priv, intr, priv->dev,
2529 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
2530
2531 /* Check Rx priority queue interrupts */
2532 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2533 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2534 continue;
2535
2536 rx_ring = &priv->rx_rings[index];
2537
2538 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2539 rx_ring->int_disable(rx_ring);
2540 __napi_schedule(&rx_ring->napi);
2541 }
2542 }
2543
2544 /* Check Tx priority queue interrupts */
2545 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2546 if (!(priv->irq1_stat & BIT(index)))
2547 continue;
2548
2549 tx_ring = &priv->tx_rings[index];
2550
2551 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2552 tx_ring->int_disable(tx_ring);
2553 __napi_schedule(&tx_ring->napi);
2554 }
2555 }
2556
2557 return IRQ_HANDLED;
2558 }
2559
2560 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
bcmgenet_isr0(int irq,void * dev_id)2561 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2562 {
2563 struct bcmgenet_priv *priv = dev_id;
2564 struct bcmgenet_rx_ring *rx_ring;
2565 struct bcmgenet_tx_ring *tx_ring;
2566
2567 /* Save irq status for bottom-half processing. */
2568 priv->irq0_stat =
2569 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2570 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2571
2572 /* clear interrupts */
2573 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2574
2575 netif_dbg(priv, intr, priv->dev,
2576 "IRQ=0x%x\n", priv->irq0_stat);
2577
2578 if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
2579 rx_ring = &priv->rx_rings[DESC_INDEX];
2580
2581 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2582 rx_ring->int_disable(rx_ring);
2583 __napi_schedule(&rx_ring->napi);
2584 }
2585 }
2586
2587 if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
2588 tx_ring = &priv->tx_rings[DESC_INDEX];
2589
2590 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2591 tx_ring->int_disable(tx_ring);
2592 __napi_schedule(&tx_ring->napi);
2593 }
2594 }
2595
2596 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2597 UMAC_IRQ_PHY_DET_F |
2598 UMAC_IRQ_LINK_EVENT |
2599 UMAC_IRQ_HFB_SM |
2600 UMAC_IRQ_HFB_MM |
2601 UMAC_IRQ_MPD_R)) {
2602 /* all other interested interrupts handled in bottom half */
2603 schedule_work(&priv->bcmgenet_irq_work);
2604 }
2605
2606 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2607 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2608 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2609 wake_up(&priv->wq);
2610 }
2611
2612 return IRQ_HANDLED;
2613 }
2614
bcmgenet_wol_isr(int irq,void * dev_id)2615 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2616 {
2617 struct bcmgenet_priv *priv = dev_id;
2618
2619 pm_wakeup_event(&priv->pdev->dev, 0);
2620
2621 return IRQ_HANDLED;
2622 }
2623
2624 #ifdef CONFIG_NET_POLL_CONTROLLER
bcmgenet_poll_controller(struct net_device * dev)2625 static void bcmgenet_poll_controller(struct net_device *dev)
2626 {
2627 struct bcmgenet_priv *priv = netdev_priv(dev);
2628
2629 /* Invoke the main RX/TX interrupt handler */
2630 disable_irq(priv->irq0);
2631 bcmgenet_isr0(priv->irq0, priv);
2632 enable_irq(priv->irq0);
2633
2634 /* And the interrupt handler for RX/TX priority queues */
2635 disable_irq(priv->irq1);
2636 bcmgenet_isr1(priv->irq1, priv);
2637 enable_irq(priv->irq1);
2638 }
2639 #endif
2640
bcmgenet_umac_reset(struct bcmgenet_priv * priv)2641 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2642 {
2643 u32 reg;
2644
2645 reg = bcmgenet_rbuf_ctrl_get(priv);
2646 reg |= BIT(1);
2647 bcmgenet_rbuf_ctrl_set(priv, reg);
2648 udelay(10);
2649
2650 reg &= ~BIT(1);
2651 bcmgenet_rbuf_ctrl_set(priv, reg);
2652 udelay(10);
2653 }
2654
bcmgenet_set_hw_addr(struct bcmgenet_priv * priv,unsigned char * addr)2655 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2656 unsigned char *addr)
2657 {
2658 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2659 (addr[2] << 8) | addr[3], UMAC_MAC0);
2660 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2661 }
2662
2663 /* Returns a reusable dma control register value */
bcmgenet_dma_disable(struct bcmgenet_priv * priv)2664 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2665 {
2666 unsigned int i;
2667 u32 reg;
2668 u32 dma_ctrl;
2669
2670 /* disable DMA */
2671 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2672 for (i = 0; i < priv->hw_params->tx_queues; i++)
2673 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2674 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2675 reg &= ~dma_ctrl;
2676 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2677
2678 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2679 for (i = 0; i < priv->hw_params->rx_queues; i++)
2680 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2681 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2682 reg &= ~dma_ctrl;
2683 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2684
2685 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2686 udelay(10);
2687 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2688
2689 return dma_ctrl;
2690 }
2691
bcmgenet_enable_dma(struct bcmgenet_priv * priv,u32 dma_ctrl)2692 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2693 {
2694 u32 reg;
2695
2696 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2697 reg |= dma_ctrl;
2698 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2699
2700 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2701 reg |= dma_ctrl;
2702 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2703 }
2704
bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv * priv,u32 f_index)2705 static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2706 u32 f_index)
2707 {
2708 u32 offset;
2709 u32 reg;
2710
2711 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2712 reg = bcmgenet_hfb_reg_readl(priv, offset);
2713 return !!(reg & (1 << (f_index % 32)));
2714 }
2715
bcmgenet_hfb_enable_filter(struct bcmgenet_priv * priv,u32 f_index)2716 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2717 {
2718 u32 offset;
2719 u32 reg;
2720
2721 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2722 reg = bcmgenet_hfb_reg_readl(priv, offset);
2723 reg |= (1 << (f_index % 32));
2724 bcmgenet_hfb_reg_writel(priv, reg, offset);
2725 }
2726
bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv * priv,u32 f_index,u32 rx_queue)2727 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2728 u32 f_index, u32 rx_queue)
2729 {
2730 u32 offset;
2731 u32 reg;
2732
2733 offset = f_index / 8;
2734 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2735 reg &= ~(0xF << (4 * (f_index % 8)));
2736 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2737 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2738 }
2739
bcmgenet_hfb_set_filter_length(struct bcmgenet_priv * priv,u32 f_index,u32 f_length)2740 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2741 u32 f_index, u32 f_length)
2742 {
2743 u32 offset;
2744 u32 reg;
2745
2746 offset = HFB_FLT_LEN_V3PLUS +
2747 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2748 sizeof(u32);
2749 reg = bcmgenet_hfb_reg_readl(priv, offset);
2750 reg &= ~(0xFF << (8 * (f_index % 4)));
2751 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2752 bcmgenet_hfb_reg_writel(priv, reg, offset);
2753 }
2754
bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv * priv)2755 static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2756 {
2757 u32 f_index;
2758
2759 for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2760 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2761 return f_index;
2762
2763 return -ENOMEM;
2764 }
2765
2766 /* bcmgenet_hfb_add_filter
2767 *
2768 * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2769 * desired Rx queue.
2770 *
2771 * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2772 * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2773 *
2774 * bits 31:20 - unused
2775 * bit 19 - nibble 0 match enable
2776 * bit 18 - nibble 1 match enable
2777 * bit 17 - nibble 2 match enable
2778 * bit 16 - nibble 3 match enable
2779 * bits 15:12 - nibble 0 data
2780 * bits 11:8 - nibble 1 data
2781 * bits 7:4 - nibble 2 data
2782 * bits 3:0 - nibble 3 data
2783 *
2784 * Example:
2785 * In order to match:
2786 * - Ethernet frame type = 0x0800 (IP)
2787 * - IP version field = 4
2788 * - IP protocol field = 0x11 (UDP)
2789 *
2790 * The following filter is needed:
2791 * u32 hfb_filter_ipv4_udp[] = {
2792 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2793 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2794 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2795 * };
2796 *
2797 * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2798 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2799 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2800 */
bcmgenet_hfb_add_filter(struct bcmgenet_priv * priv,u32 * f_data,u32 f_length,u32 rx_queue)2801 int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2802 u32 f_length, u32 rx_queue)
2803 {
2804 int f_index;
2805 u32 i;
2806
2807 f_index = bcmgenet_hfb_find_unused_filter(priv);
2808 if (f_index < 0)
2809 return -ENOMEM;
2810
2811 if (f_length > priv->hw_params->hfb_filter_size)
2812 return -EINVAL;
2813
2814 for (i = 0; i < f_length; i++)
2815 bcmgenet_hfb_writel(priv, f_data[i],
2816 (f_index * priv->hw_params->hfb_filter_size + i) *
2817 sizeof(u32));
2818
2819 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2820 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2821 bcmgenet_hfb_enable_filter(priv, f_index);
2822 bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2823
2824 return 0;
2825 }
2826
2827 /* bcmgenet_hfb_clear
2828 *
2829 * Clear Hardware Filter Block and disable all filtering.
2830 */
bcmgenet_hfb_clear(struct bcmgenet_priv * priv)2831 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2832 {
2833 u32 i;
2834
2835 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2836 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2837 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2838
2839 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2840 bcmgenet_rdma_writel(priv, 0x0, i);
2841
2842 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2843 bcmgenet_hfb_reg_writel(priv, 0x0,
2844 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2845
2846 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2847 priv->hw_params->hfb_filter_size; i++)
2848 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2849 }
2850
bcmgenet_hfb_init(struct bcmgenet_priv * priv)2851 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2852 {
2853 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2854 return;
2855
2856 bcmgenet_hfb_clear(priv);
2857 }
2858
bcmgenet_netif_start(struct net_device * dev)2859 static void bcmgenet_netif_start(struct net_device *dev)
2860 {
2861 struct bcmgenet_priv *priv = netdev_priv(dev);
2862
2863 /* Start the network engine */
2864 bcmgenet_enable_rx_napi(priv);
2865 bcmgenet_enable_tx_napi(priv);
2866
2867 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2868
2869 netif_tx_start_all_queues(dev);
2870
2871 /* Monitor link interrupts now */
2872 bcmgenet_link_intr_enable(priv);
2873
2874 phy_start(priv->phydev);
2875 }
2876
bcmgenet_open(struct net_device * dev)2877 static int bcmgenet_open(struct net_device *dev)
2878 {
2879 struct bcmgenet_priv *priv = netdev_priv(dev);
2880 unsigned long dma_ctrl;
2881 u32 reg;
2882 int ret;
2883
2884 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2885
2886 /* Turn on the clock */
2887 clk_prepare_enable(priv->clk);
2888
2889 /* If this is an internal GPHY, power it back on now, before UniMAC is
2890 * brought out of reset as absolutely no UniMAC activity is allowed
2891 */
2892 if (priv->internal_phy)
2893 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2894
2895 /* take MAC out of reset */
2896 bcmgenet_umac_reset(priv);
2897
2898 ret = init_umac(priv);
2899 if (ret)
2900 goto err_clk_disable;
2901
2902 /* disable ethernet MAC while updating its registers */
2903 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2904
2905 /* Make sure we reflect the value of CRC_CMD_FWD */
2906 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2907 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2908
2909 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2910
2911 /* Disable RX/TX DMA and flush TX queues */
2912 dma_ctrl = bcmgenet_dma_disable(priv);
2913
2914 /* Reinitialize TDMA and RDMA and SW housekeeping */
2915 ret = bcmgenet_init_dma(priv);
2916 if (ret) {
2917 netdev_err(dev, "failed to initialize DMA\n");
2918 goto err_clk_disable;
2919 }
2920
2921 /* Always enable ring 16 - descriptor ring */
2922 bcmgenet_enable_dma(priv, dma_ctrl);
2923
2924 /* HFB init */
2925 bcmgenet_hfb_init(priv);
2926
2927 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2928 dev->name, priv);
2929 if (ret < 0) {
2930 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2931 goto err_fini_dma;
2932 }
2933
2934 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2935 dev->name, priv);
2936 if (ret < 0) {
2937 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2938 goto err_irq0;
2939 }
2940
2941 ret = bcmgenet_mii_probe(dev);
2942 if (ret) {
2943 netdev_err(dev, "failed to connect to PHY\n");
2944 goto err_irq1;
2945 }
2946
2947 bcmgenet_netif_start(dev);
2948
2949 return 0;
2950
2951 err_irq1:
2952 free_irq(priv->irq1, priv);
2953 err_irq0:
2954 free_irq(priv->irq0, priv);
2955 err_fini_dma:
2956 bcmgenet_fini_dma(priv);
2957 err_clk_disable:
2958 if (priv->internal_phy)
2959 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2960 clk_disable_unprepare(priv->clk);
2961 return ret;
2962 }
2963
bcmgenet_netif_stop(struct net_device * dev)2964 static void bcmgenet_netif_stop(struct net_device *dev)
2965 {
2966 struct bcmgenet_priv *priv = netdev_priv(dev);
2967
2968 netif_tx_stop_all_queues(dev);
2969 phy_stop(priv->phydev);
2970 bcmgenet_intr_disable(priv);
2971 bcmgenet_disable_rx_napi(priv);
2972 bcmgenet_disable_tx_napi(priv);
2973
2974 /* Wait for pending work items to complete. Since interrupts are
2975 * disabled no new work will be scheduled.
2976 */
2977 cancel_work_sync(&priv->bcmgenet_irq_work);
2978
2979 priv->old_link = -1;
2980 priv->old_speed = -1;
2981 priv->old_duplex = -1;
2982 priv->old_pause = -1;
2983 }
2984
bcmgenet_close(struct net_device * dev)2985 static int bcmgenet_close(struct net_device *dev)
2986 {
2987 struct bcmgenet_priv *priv = netdev_priv(dev);
2988 int ret;
2989
2990 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2991
2992 bcmgenet_netif_stop(dev);
2993
2994 /* Really kill the PHY state machine and disconnect from it */
2995 phy_disconnect(priv->phydev);
2996
2997 /* Disable MAC receive */
2998 umac_enable_set(priv, CMD_RX_EN, false);
2999
3000 ret = bcmgenet_dma_teardown(priv);
3001 if (ret)
3002 return ret;
3003
3004 /* Disable MAC transmit. TX DMA disabled have to done before this */
3005 umac_enable_set(priv, CMD_TX_EN, false);
3006
3007 /* tx reclaim */
3008 bcmgenet_tx_reclaim_all(dev);
3009 bcmgenet_fini_dma(priv);
3010
3011 free_irq(priv->irq0, priv);
3012 free_irq(priv->irq1, priv);
3013
3014 if (priv->internal_phy)
3015 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3016
3017 clk_disable_unprepare(priv->clk);
3018
3019 return ret;
3020 }
3021
bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring * ring)3022 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3023 {
3024 struct bcmgenet_priv *priv = ring->priv;
3025 u32 p_index, c_index, intsts, intmsk;
3026 struct netdev_queue *txq;
3027 unsigned int free_bds;
3028 unsigned long flags;
3029 bool txq_stopped;
3030
3031 if (!netif_msg_tx_err(priv))
3032 return;
3033
3034 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3035
3036 spin_lock_irqsave(&ring->lock, flags);
3037 if (ring->index == DESC_INDEX) {
3038 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3039 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3040 } else {
3041 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3042 intmsk = 1 << ring->index;
3043 }
3044 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3045 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3046 txq_stopped = netif_tx_queue_stopped(txq);
3047 free_bds = ring->free_bds;
3048 spin_unlock_irqrestore(&ring->lock, flags);
3049
3050 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3051 "TX queue status: %s, interrupts: %s\n"
3052 "(sw)free_bds: %d (sw)size: %d\n"
3053 "(sw)p_index: %d (hw)p_index: %d\n"
3054 "(sw)c_index: %d (hw)c_index: %d\n"
3055 "(sw)clean_p: %d (sw)write_p: %d\n"
3056 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3057 ring->index, ring->queue,
3058 txq_stopped ? "stopped" : "active",
3059 intsts & intmsk ? "enabled" : "disabled",
3060 free_bds, ring->size,
3061 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3062 ring->c_index, c_index & DMA_C_INDEX_MASK,
3063 ring->clean_ptr, ring->write_ptr,
3064 ring->cb_ptr, ring->end_ptr);
3065 }
3066
bcmgenet_timeout(struct net_device * dev)3067 static void bcmgenet_timeout(struct net_device *dev)
3068 {
3069 struct bcmgenet_priv *priv = netdev_priv(dev);
3070 u32 int0_enable = 0;
3071 u32 int1_enable = 0;
3072 unsigned int q;
3073
3074 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3075
3076 for (q = 0; q < priv->hw_params->tx_queues; q++)
3077 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3078 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3079
3080 bcmgenet_tx_reclaim_all(dev);
3081
3082 for (q = 0; q < priv->hw_params->tx_queues; q++)
3083 int1_enable |= (1 << q);
3084
3085 int0_enable = UMAC_IRQ_TXDMA_DONE;
3086
3087 /* Re-enable TX interrupts if disabled */
3088 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3089 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3090
3091 dev->trans_start = jiffies;
3092
3093 dev->stats.tx_errors++;
3094
3095 netif_tx_wake_all_queues(dev);
3096 }
3097
3098 #define MAX_MDF_FILTER 17
3099
bcmgenet_set_mdf_addr(struct bcmgenet_priv * priv,unsigned char * addr,int * i)3100 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3101 unsigned char *addr,
3102 int *i)
3103 {
3104 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3105 UMAC_MDF_ADDR + (*i * 4));
3106 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3107 addr[4] << 8 | addr[5],
3108 UMAC_MDF_ADDR + ((*i + 1) * 4));
3109 *i += 2;
3110 }
3111
bcmgenet_set_rx_mode(struct net_device * dev)3112 static void bcmgenet_set_rx_mode(struct net_device *dev)
3113 {
3114 struct bcmgenet_priv *priv = netdev_priv(dev);
3115 struct netdev_hw_addr *ha;
3116 int i, nfilter;
3117 u32 reg;
3118
3119 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3120
3121 /* Number of filters needed */
3122 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3123
3124 /*
3125 * Turn on promicuous mode for three scenarios
3126 * 1. IFF_PROMISC flag is set
3127 * 2. IFF_ALLMULTI flag is set
3128 * 3. The number of filters needed exceeds the number filters
3129 * supported by the hardware.
3130 */
3131 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3132 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3133 (nfilter > MAX_MDF_FILTER)) {
3134 reg |= CMD_PROMISC;
3135 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3136 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3137 return;
3138 } else {
3139 reg &= ~CMD_PROMISC;
3140 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3141 }
3142
3143 /* update MDF filter */
3144 i = 0;
3145 /* Broadcast */
3146 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3147 /* my own address.*/
3148 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3149
3150 /* Unicast */
3151 netdev_for_each_uc_addr(ha, dev)
3152 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3153
3154 /* Multicast */
3155 netdev_for_each_mc_addr(ha, dev)
3156 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3157
3158 /* Enable filters */
3159 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3160 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3161 }
3162
3163 /* Set the hardware MAC address. */
bcmgenet_set_mac_addr(struct net_device * dev,void * p)3164 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3165 {
3166 struct sockaddr *addr = p;
3167
3168 /* Setting the MAC address at the hardware level is not possible
3169 * without disabling the UniMAC RX/TX enable bits.
3170 */
3171 if (netif_running(dev))
3172 return -EBUSY;
3173
3174 ether_addr_copy(dev->dev_addr, addr->sa_data);
3175
3176 return 0;
3177 }
3178
3179 static const struct net_device_ops bcmgenet_netdev_ops = {
3180 .ndo_open = bcmgenet_open,
3181 .ndo_stop = bcmgenet_close,
3182 .ndo_start_xmit = bcmgenet_xmit,
3183 .ndo_tx_timeout = bcmgenet_timeout,
3184 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3185 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3186 .ndo_do_ioctl = bcmgenet_ioctl,
3187 .ndo_set_features = bcmgenet_set_features,
3188 #ifdef CONFIG_NET_POLL_CONTROLLER
3189 .ndo_poll_controller = bcmgenet_poll_controller,
3190 #endif
3191 };
3192
3193 /* Array of GENET hardware parameters/characteristics */
3194 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3195 [GENET_V1] = {
3196 .tx_queues = 0,
3197 .tx_bds_per_q = 0,
3198 .rx_queues = 0,
3199 .rx_bds_per_q = 0,
3200 .bp_in_en_shift = 16,
3201 .bp_in_mask = 0xffff,
3202 .hfb_filter_cnt = 16,
3203 .qtag_mask = 0x1F,
3204 .hfb_offset = 0x1000,
3205 .rdma_offset = 0x2000,
3206 .tdma_offset = 0x3000,
3207 .words_per_bd = 2,
3208 },
3209 [GENET_V2] = {
3210 .tx_queues = 4,
3211 .tx_bds_per_q = 32,
3212 .rx_queues = 0,
3213 .rx_bds_per_q = 0,
3214 .bp_in_en_shift = 16,
3215 .bp_in_mask = 0xffff,
3216 .hfb_filter_cnt = 16,
3217 .qtag_mask = 0x1F,
3218 .tbuf_offset = 0x0600,
3219 .hfb_offset = 0x1000,
3220 .hfb_reg_offset = 0x2000,
3221 .rdma_offset = 0x3000,
3222 .tdma_offset = 0x4000,
3223 .words_per_bd = 2,
3224 .flags = GENET_HAS_EXT,
3225 },
3226 [GENET_V3] = {
3227 .tx_queues = 4,
3228 .tx_bds_per_q = 32,
3229 .rx_queues = 0,
3230 .rx_bds_per_q = 0,
3231 .bp_in_en_shift = 17,
3232 .bp_in_mask = 0x1ffff,
3233 .hfb_filter_cnt = 48,
3234 .hfb_filter_size = 128,
3235 .qtag_mask = 0x3F,
3236 .tbuf_offset = 0x0600,
3237 .hfb_offset = 0x8000,
3238 .hfb_reg_offset = 0xfc00,
3239 .rdma_offset = 0x10000,
3240 .tdma_offset = 0x11000,
3241 .words_per_bd = 2,
3242 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3243 GENET_HAS_MOCA_LINK_DET,
3244 },
3245 [GENET_V4] = {
3246 .tx_queues = 4,
3247 .tx_bds_per_q = 32,
3248 .rx_queues = 0,
3249 .rx_bds_per_q = 0,
3250 .bp_in_en_shift = 17,
3251 .bp_in_mask = 0x1ffff,
3252 .hfb_filter_cnt = 48,
3253 .hfb_filter_size = 128,
3254 .qtag_mask = 0x3F,
3255 .tbuf_offset = 0x0600,
3256 .hfb_offset = 0x8000,
3257 .hfb_reg_offset = 0xfc00,
3258 .rdma_offset = 0x2000,
3259 .tdma_offset = 0x4000,
3260 .words_per_bd = 3,
3261 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3262 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3263 },
3264 };
3265
3266 /* Infer hardware parameters from the detected GENET version */
bcmgenet_set_hw_params(struct bcmgenet_priv * priv)3267 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3268 {
3269 struct bcmgenet_hw_params *params;
3270 u32 reg;
3271 u8 major;
3272 u16 gphy_rev;
3273
3274 if (GENET_IS_V4(priv)) {
3275 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3276 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3277 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3278 priv->version = GENET_V4;
3279 } else if (GENET_IS_V3(priv)) {
3280 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3281 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3282 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3283 priv->version = GENET_V3;
3284 } else if (GENET_IS_V2(priv)) {
3285 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3286 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3287 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3288 priv->version = GENET_V2;
3289 } else if (GENET_IS_V1(priv)) {
3290 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3291 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3292 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3293 priv->version = GENET_V1;
3294 }
3295
3296 /* enum genet_version starts at 1 */
3297 priv->hw_params = &bcmgenet_hw_params[priv->version];
3298 params = priv->hw_params;
3299
3300 /* Read GENET HW version */
3301 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3302 major = (reg >> 24 & 0x0f);
3303 if (major == 5)
3304 major = 4;
3305 else if (major == 0)
3306 major = 1;
3307 if (major != priv->version) {
3308 dev_err(&priv->pdev->dev,
3309 "GENET version mismatch, got: %d, configured for: %d\n",
3310 major, priv->version);
3311 }
3312
3313 /* Print the GENET core version */
3314 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3315 major, (reg >> 16) & 0x0f, reg & 0xffff);
3316
3317 /* Store the integrated PHY revision for the MDIO probing function
3318 * to pass this information to the PHY driver. The PHY driver expects
3319 * to find the PHY major revision in bits 15:8 while the GENET register
3320 * stores that information in bits 7:0, account for that.
3321 *
3322 * On newer chips, starting with PHY revision G0, a new scheme is
3323 * deployed similar to the Starfighter 2 switch with GPHY major
3324 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3325 * is reserved as well as special value 0x01ff, we have a small
3326 * heuristic to check for the new GPHY revision and re-arrange things
3327 * so the GPHY driver is happy.
3328 */
3329 gphy_rev = reg & 0xffff;
3330
3331 /* This is reserved so should require special treatment */
3332 if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3333 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3334 return;
3335 }
3336
3337 /* This is the good old scheme, just GPHY major, no minor nor patch */
3338 if ((gphy_rev & 0xf0) != 0)
3339 priv->gphy_rev = gphy_rev << 8;
3340
3341 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3342 else if ((gphy_rev & 0xff00) != 0)
3343 priv->gphy_rev = gphy_rev;
3344
3345 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3346 if (!(params->flags & GENET_HAS_40BITS))
3347 pr_warn("GENET does not support 40-bits PA\n");
3348 #endif
3349
3350 pr_debug("Configuration for version: %d\n"
3351 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3352 "BP << en: %2d, BP msk: 0x%05x\n"
3353 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3354 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3355 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3356 "Words/BD: %d\n",
3357 priv->version,
3358 params->tx_queues, params->tx_bds_per_q,
3359 params->rx_queues, params->rx_bds_per_q,
3360 params->bp_in_en_shift, params->bp_in_mask,
3361 params->hfb_filter_cnt, params->qtag_mask,
3362 params->tbuf_offset, params->hfb_offset,
3363 params->hfb_reg_offset,
3364 params->rdma_offset, params->tdma_offset,
3365 params->words_per_bd);
3366 }
3367
3368 static const struct of_device_id bcmgenet_match[] = {
3369 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3370 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3371 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3372 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3373 { },
3374 };
3375 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3376
bcmgenet_probe(struct platform_device * pdev)3377 static int bcmgenet_probe(struct platform_device *pdev)
3378 {
3379 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3380 struct device_node *dn = pdev->dev.of_node;
3381 const struct of_device_id *of_id = NULL;
3382 struct bcmgenet_priv *priv;
3383 struct net_device *dev;
3384 const void *macaddr;
3385 struct resource *r;
3386 int err = -EIO;
3387 const char *phy_mode_str;
3388
3389 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3390 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3391 GENET_MAX_MQ_CNT + 1);
3392 if (!dev) {
3393 dev_err(&pdev->dev, "can't allocate net device\n");
3394 return -ENOMEM;
3395 }
3396
3397 if (dn) {
3398 of_id = of_match_node(bcmgenet_match, dn);
3399 if (!of_id)
3400 return -EINVAL;
3401 }
3402
3403 priv = netdev_priv(dev);
3404 priv->irq0 = platform_get_irq(pdev, 0);
3405 priv->irq1 = platform_get_irq(pdev, 1);
3406 priv->wol_irq = platform_get_irq(pdev, 2);
3407 if (!priv->irq0 || !priv->irq1) {
3408 dev_err(&pdev->dev, "can't find IRQs\n");
3409 err = -EINVAL;
3410 goto err;
3411 }
3412
3413 if (dn) {
3414 macaddr = of_get_mac_address(dn);
3415 if (!macaddr) {
3416 dev_err(&pdev->dev, "can't find MAC address\n");
3417 err = -EINVAL;
3418 goto err;
3419 }
3420 } else {
3421 macaddr = pd->mac_address;
3422 }
3423
3424 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3425 priv->base = devm_ioremap_resource(&pdev->dev, r);
3426 if (IS_ERR(priv->base)) {
3427 err = PTR_ERR(priv->base);
3428 goto err;
3429 }
3430
3431 SET_NETDEV_DEV(dev, &pdev->dev);
3432 dev_set_drvdata(&pdev->dev, dev);
3433 ether_addr_copy(dev->dev_addr, macaddr);
3434 dev->watchdog_timeo = 2 * HZ;
3435 dev->ethtool_ops = &bcmgenet_ethtool_ops;
3436 dev->netdev_ops = &bcmgenet_netdev_ops;
3437
3438 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3439
3440 /* Set hardware features */
3441 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3442 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3443
3444 /* Request the WOL interrupt and advertise suspend if available */
3445 priv->wol_irq_disabled = true;
3446 if (priv->wol_irq > 0) {
3447 err = devm_request_irq(&pdev->dev, priv->wol_irq,
3448 bcmgenet_wol_isr, 0, dev->name, priv);
3449 if (!err)
3450 device_set_wakeup_capable(&pdev->dev, 1);
3451 }
3452
3453 /* Set the needed headroom to account for any possible
3454 * features enabling/disabling at runtime
3455 */
3456 dev->needed_headroom += 64;
3457
3458 netdev_boot_setup_check(dev);
3459
3460 priv->dev = dev;
3461 priv->pdev = pdev;
3462 if (of_id)
3463 priv->version = (enum bcmgenet_version)of_id->data;
3464 else
3465 priv->version = pd->genet_version;
3466
3467 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3468 if (IS_ERR(priv->clk)) {
3469 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3470 priv->clk = NULL;
3471 }
3472
3473 clk_prepare_enable(priv->clk);
3474
3475 bcmgenet_set_hw_params(priv);
3476
3477 /* Mii wait queue */
3478 init_waitqueue_head(&priv->wq);
3479 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3480 priv->rx_buf_len = RX_BUF_LENGTH;
3481 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3482
3483 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3484 if (IS_ERR(priv->clk_wol)) {
3485 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3486 priv->clk_wol = NULL;
3487 }
3488
3489 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3490 if (IS_ERR(priv->clk_eee)) {
3491 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3492 priv->clk_eee = NULL;
3493 }
3494
3495 /* If this is an internal GPHY, power it on now, before UniMAC is
3496 * brought out of reset as absolutely no UniMAC activity is allowed
3497 */
3498 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3499 !strcasecmp(phy_mode_str, "internal"))
3500 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3501
3502 err = reset_umac(priv);
3503 if (err)
3504 goto err_clk_disable;
3505
3506 err = bcmgenet_mii_init(dev);
3507 if (err)
3508 goto err_clk_disable;
3509
3510 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3511 * just the ring 16 descriptor based TX
3512 */
3513 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3514 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3515
3516 /* libphy will determine the link state */
3517 netif_carrier_off(dev);
3518
3519 /* Turn off the main clock, WOL clock is handled separately */
3520 clk_disable_unprepare(priv->clk);
3521
3522 err = register_netdev(dev);
3523 if (err) {
3524 bcmgenet_mii_exit(dev);
3525 goto err;
3526 }
3527
3528 return err;
3529
3530 err_clk_disable:
3531 clk_disable_unprepare(priv->clk);
3532 err:
3533 free_netdev(dev);
3534 return err;
3535 }
3536
bcmgenet_remove(struct platform_device * pdev)3537 static int bcmgenet_remove(struct platform_device *pdev)
3538 {
3539 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3540
3541 dev_set_drvdata(&pdev->dev, NULL);
3542 unregister_netdev(priv->dev);
3543 bcmgenet_mii_exit(priv->dev);
3544 free_netdev(priv->dev);
3545
3546 return 0;
3547 }
3548
3549 #ifdef CONFIG_PM_SLEEP
bcmgenet_suspend(struct device * d)3550 static int bcmgenet_suspend(struct device *d)
3551 {
3552 struct net_device *dev = dev_get_drvdata(d);
3553 struct bcmgenet_priv *priv = netdev_priv(dev);
3554 int ret;
3555
3556 if (!netif_running(dev))
3557 return 0;
3558
3559 bcmgenet_netif_stop(dev);
3560
3561 if (!device_may_wakeup(d))
3562 phy_suspend(priv->phydev);
3563
3564 netif_device_detach(dev);
3565
3566 /* Disable MAC receive */
3567 umac_enable_set(priv, CMD_RX_EN, false);
3568
3569 ret = bcmgenet_dma_teardown(priv);
3570 if (ret)
3571 return ret;
3572
3573 /* Disable MAC transmit. TX DMA disabled have to done before this */
3574 umac_enable_set(priv, CMD_TX_EN, false);
3575
3576 /* tx reclaim */
3577 bcmgenet_tx_reclaim_all(dev);
3578 bcmgenet_fini_dma(priv);
3579
3580 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3581 if (device_may_wakeup(d) && priv->wolopts) {
3582 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3583 clk_prepare_enable(priv->clk_wol);
3584 } else if (priv->internal_phy) {
3585 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3586 }
3587
3588 /* Turn off the clocks */
3589 clk_disable_unprepare(priv->clk);
3590
3591 return ret;
3592 }
3593
bcmgenet_resume(struct device * d)3594 static int bcmgenet_resume(struct device *d)
3595 {
3596 struct net_device *dev = dev_get_drvdata(d);
3597 struct bcmgenet_priv *priv = netdev_priv(dev);
3598 unsigned long dma_ctrl;
3599 int ret;
3600
3601 if (!netif_running(dev))
3602 return 0;
3603
3604 /* Turn on the clock */
3605 ret = clk_prepare_enable(priv->clk);
3606 if (ret)
3607 return ret;
3608
3609 /* If this is an internal GPHY, power it back on now, before UniMAC is
3610 * brought out of reset as absolutely no UniMAC activity is allowed
3611 */
3612 if (priv->internal_phy)
3613 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3614
3615 bcmgenet_umac_reset(priv);
3616
3617 ret = init_umac(priv);
3618 if (ret)
3619 goto out_clk_disable;
3620
3621 /* From WOL-enabled suspend, switch to regular clock */
3622 if (priv->wolopts)
3623 clk_disable_unprepare(priv->clk_wol);
3624
3625 phy_init_hw(priv->phydev);
3626 /* Speed settings must be restored */
3627 bcmgenet_mii_config(priv->dev);
3628
3629 /* disable ethernet MAC while updating its registers */
3630 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3631
3632 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3633
3634 if (priv->wolopts)
3635 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3636
3637 /* Disable RX/TX DMA and flush TX queues */
3638 dma_ctrl = bcmgenet_dma_disable(priv);
3639
3640 /* Reinitialize TDMA and RDMA and SW housekeeping */
3641 ret = bcmgenet_init_dma(priv);
3642 if (ret) {
3643 netdev_err(dev, "failed to initialize DMA\n");
3644 goto out_clk_disable;
3645 }
3646
3647 /* Always enable ring 16 - descriptor ring */
3648 bcmgenet_enable_dma(priv, dma_ctrl);
3649
3650 netif_device_attach(dev);
3651
3652 if (!device_may_wakeup(d))
3653 phy_resume(priv->phydev);
3654
3655 if (priv->eee.eee_enabled)
3656 bcmgenet_eee_enable_set(dev, true);
3657
3658 bcmgenet_netif_start(dev);
3659
3660 return 0;
3661
3662 out_clk_disable:
3663 if (priv->internal_phy)
3664 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3665 clk_disable_unprepare(priv->clk);
3666 return ret;
3667 }
3668 #endif /* CONFIG_PM_SLEEP */
3669
3670 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3671
3672 static struct platform_driver bcmgenet_driver = {
3673 .probe = bcmgenet_probe,
3674 .remove = bcmgenet_remove,
3675 .driver = {
3676 .name = "bcmgenet",
3677 .of_match_table = bcmgenet_match,
3678 .pm = &bcmgenet_pm_ops,
3679 },
3680 };
3681 module_platform_driver(bcmgenet_driver);
3682
3683 MODULE_AUTHOR("Broadcom Corporation");
3684 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3685 MODULE_ALIAS("platform:bcmgenet");
3686 MODULE_LICENSE("GPL");
3687