1 /*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/phy.h>
16 #include <linux/of.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
19
20 #include "nic_reg.h"
21 #include "nic.h"
22 #include "thunder_bgx.h"
23
24 #define DRV_NAME "thunder-BGX"
25 #define DRV_VERSION "1.0"
26
27 struct lmac {
28 struct bgx *bgx;
29 int dmac;
30 u8 mac[ETH_ALEN];
31 bool link_up;
32 int lmacid; /* ID within BGX */
33 int lmacid_bd; /* ID on board */
34 struct net_device netdev;
35 struct phy_device *phydev;
36 unsigned int last_duplex;
37 unsigned int last_link;
38 unsigned int last_speed;
39 bool is_sgmii;
40 struct delayed_work dwork;
41 struct workqueue_struct *check_link;
42 };
43
44 struct bgx {
45 u8 bgx_id;
46 u8 qlm_mode;
47 struct lmac lmac[MAX_LMAC_PER_BGX];
48 int lmac_count;
49 int lmac_type;
50 int lane_to_sds;
51 int use_training;
52 void __iomem *reg_base;
53 struct pci_dev *pdev;
54 };
55
56 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
57 static int lmac_count; /* Total no of LMACs in system */
58
59 static int bgx_xaui_check_link(struct lmac *lmac);
60
61 /* Supported devices */
62 static const struct pci_device_id bgx_id_table[] = {
63 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
64 { 0, } /* end of table */
65 };
66
67 MODULE_AUTHOR("Cavium Inc");
68 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
69 MODULE_LICENSE("GPL v2");
70 MODULE_VERSION(DRV_VERSION);
71 MODULE_DEVICE_TABLE(pci, bgx_id_table);
72
73 /* The Cavium ThunderX network controller can *only* be found in SoCs
74 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
75 * registers on this platform are implicitly strongly ordered with respect
76 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
77 * with no memory barriers in this driver. The readq()/writeq() functions add
78 * explicit ordering operation which in this case are redundant, and only
79 * add overhead.
80 */
81
82 /* Register read/write APIs */
bgx_reg_read(struct bgx * bgx,u8 lmac,u64 offset)83 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
84 {
85 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
86
87 return readq_relaxed(addr);
88 }
89
bgx_reg_write(struct bgx * bgx,u8 lmac,u64 offset,u64 val)90 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
91 {
92 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
93
94 writeq_relaxed(val, addr);
95 }
96
bgx_reg_modify(struct bgx * bgx,u8 lmac,u64 offset,u64 val)97 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
98 {
99 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
100
101 writeq_relaxed(val | readq_relaxed(addr), addr);
102 }
103
bgx_poll_reg(struct bgx * bgx,u8 lmac,u64 reg,u64 mask,bool zero)104 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
105 {
106 int timeout = 100;
107 u64 reg_val;
108
109 while (timeout) {
110 reg_val = bgx_reg_read(bgx, lmac, reg);
111 if (zero && !(reg_val & mask))
112 return 0;
113 if (!zero && (reg_val & mask))
114 return 0;
115 usleep_range(1000, 2000);
116 timeout--;
117 }
118 return 1;
119 }
120
121 /* Return number of BGX present in HW */
bgx_get_map(int node)122 unsigned bgx_get_map(int node)
123 {
124 int i;
125 unsigned map = 0;
126
127 for (i = 0; i < MAX_BGX_PER_CN88XX; i++) {
128 if (bgx_vnic[(node * MAX_BGX_PER_CN88XX) + i])
129 map |= (1 << i);
130 }
131
132 return map;
133 }
134 EXPORT_SYMBOL(bgx_get_map);
135
136 /* Return number of LMAC configured for this BGX */
bgx_get_lmac_count(int node,int bgx_idx)137 int bgx_get_lmac_count(int node, int bgx_idx)
138 {
139 struct bgx *bgx;
140
141 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
142 if (bgx)
143 return bgx->lmac_count;
144
145 return 0;
146 }
147 EXPORT_SYMBOL(bgx_get_lmac_count);
148
149 /* Returns the current link status of LMAC */
bgx_get_lmac_link_state(int node,int bgx_idx,int lmacid,void * status)150 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
151 {
152 struct bgx_link_status *link = (struct bgx_link_status *)status;
153 struct bgx *bgx;
154 struct lmac *lmac;
155
156 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
157 if (!bgx)
158 return;
159
160 lmac = &bgx->lmac[lmacid];
161 link->link_up = lmac->link_up;
162 link->duplex = lmac->last_duplex;
163 link->speed = lmac->last_speed;
164 }
165 EXPORT_SYMBOL(bgx_get_lmac_link_state);
166
bgx_get_lmac_mac(int node,int bgx_idx,int lmacid)167 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
168 {
169 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
170
171 if (bgx)
172 return bgx->lmac[lmacid].mac;
173
174 return NULL;
175 }
176 EXPORT_SYMBOL(bgx_get_lmac_mac);
177
bgx_set_lmac_mac(int node,int bgx_idx,int lmacid,const u8 * mac)178 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
179 {
180 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
181
182 if (!bgx)
183 return;
184
185 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
186 }
187 EXPORT_SYMBOL(bgx_set_lmac_mac);
188
bgx_lmac_rx_tx_enable(int node,int bgx_idx,int lmacid,bool enable)189 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
190 {
191 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
192 u64 cfg;
193
194 if (!bgx)
195 return;
196
197 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
198 if (enable)
199 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
200 else
201 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
202 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
203 }
204 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
205
bgx_sgmii_change_link_state(struct lmac * lmac)206 static void bgx_sgmii_change_link_state(struct lmac *lmac)
207 {
208 struct bgx *bgx = lmac->bgx;
209 u64 cmr_cfg;
210 u64 port_cfg = 0;
211 u64 misc_ctl = 0;
212
213 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
214 cmr_cfg &= ~CMR_EN;
215 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
216
217 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
218 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
219
220 if (lmac->link_up) {
221 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
222 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
223 port_cfg |= (lmac->last_duplex << 2);
224 } else {
225 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
226 }
227
228 switch (lmac->last_speed) {
229 case 10:
230 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
231 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
232 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
233 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
234 misc_ctl |= 50; /* samp_pt */
235 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
236 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
237 break;
238 case 100:
239 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
240 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
241 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
242 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
243 misc_ctl |= 5; /* samp_pt */
244 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
245 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
246 break;
247 case 1000:
248 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
249 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
250 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
251 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
252 misc_ctl |= 1; /* samp_pt */
253 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
254 if (lmac->last_duplex)
255 bgx_reg_write(bgx, lmac->lmacid,
256 BGX_GMP_GMI_TXX_BURST, 0);
257 else
258 bgx_reg_write(bgx, lmac->lmacid,
259 BGX_GMP_GMI_TXX_BURST, 8192);
260 break;
261 default:
262 break;
263 }
264 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
265 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
266
267 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
268
269 /* renable lmac */
270 cmr_cfg |= CMR_EN;
271 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
272 }
273
bgx_lmac_handler(struct net_device * netdev)274 static void bgx_lmac_handler(struct net_device *netdev)
275 {
276 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
277 struct phy_device *phydev = lmac->phydev;
278 int link_changed = 0;
279
280 if (!lmac)
281 return;
282
283 if (!phydev->link && lmac->last_link)
284 link_changed = -1;
285
286 if (phydev->link &&
287 (lmac->last_duplex != phydev->duplex ||
288 lmac->last_link != phydev->link ||
289 lmac->last_speed != phydev->speed)) {
290 link_changed = 1;
291 }
292
293 lmac->last_link = phydev->link;
294 lmac->last_speed = phydev->speed;
295 lmac->last_duplex = phydev->duplex;
296
297 if (!link_changed)
298 return;
299
300 if (link_changed > 0)
301 lmac->link_up = true;
302 else
303 lmac->link_up = false;
304
305 if (lmac->is_sgmii)
306 bgx_sgmii_change_link_state(lmac);
307 else
308 bgx_xaui_check_link(lmac);
309 }
310
bgx_get_rx_stats(int node,int bgx_idx,int lmac,int idx)311 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
312 {
313 struct bgx *bgx;
314
315 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
316 if (!bgx)
317 return 0;
318
319 if (idx > 8)
320 lmac = 0;
321 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
322 }
323 EXPORT_SYMBOL(bgx_get_rx_stats);
324
bgx_get_tx_stats(int node,int bgx_idx,int lmac,int idx)325 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
326 {
327 struct bgx *bgx;
328
329 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
330 if (!bgx)
331 return 0;
332
333 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
334 }
335 EXPORT_SYMBOL(bgx_get_tx_stats);
336
bgx_flush_dmac_addrs(struct bgx * bgx,int lmac)337 static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
338 {
339 u64 offset;
340
341 while (bgx->lmac[lmac].dmac > 0) {
342 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
343 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
344 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
345 bgx->lmac[lmac].dmac--;
346 }
347 }
348
349 /* Configure BGX LMAC in internal loopback mode */
bgx_lmac_internal_loopback(int node,int bgx_idx,int lmac_idx,bool enable)350 void bgx_lmac_internal_loopback(int node, int bgx_idx,
351 int lmac_idx, bool enable)
352 {
353 struct bgx *bgx;
354 struct lmac *lmac;
355 u64 cfg;
356
357 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
358 if (!bgx)
359 return;
360
361 lmac = &bgx->lmac[lmac_idx];
362 if (lmac->is_sgmii) {
363 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
364 if (enable)
365 cfg |= PCS_MRX_CTL_LOOPBACK1;
366 else
367 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
368 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
369 } else {
370 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
371 if (enable)
372 cfg |= SPU_CTL_LOOPBACK;
373 else
374 cfg &= ~SPU_CTL_LOOPBACK;
375 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
376 }
377 }
378 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
379
bgx_lmac_sgmii_init(struct bgx * bgx,int lmacid)380 static int bgx_lmac_sgmii_init(struct bgx *bgx, int lmacid)
381 {
382 u64 cfg;
383
384 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
385 /* max packet size */
386 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
387
388 /* Disable frame alignment if using preamble */
389 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
390 if (cfg & 1)
391 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
392
393 /* Enable lmac */
394 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
395
396 /* PCS reset */
397 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
398 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
399 PCS_MRX_CTL_RESET, true)) {
400 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
401 return -1;
402 }
403
404 /* power down, reset autoneg, autoneg enable */
405 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
406 cfg &= ~PCS_MRX_CTL_PWR_DN;
407 cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN);
408 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
409
410 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
411 PCS_MRX_STATUS_AN_CPT, false)) {
412 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
413 return -1;
414 }
415
416 return 0;
417 }
418
bgx_lmac_xaui_init(struct bgx * bgx,int lmacid,int lmac_type)419 static int bgx_lmac_xaui_init(struct bgx *bgx, int lmacid, int lmac_type)
420 {
421 u64 cfg;
422
423 /* Reset SPU */
424 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
425 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
426 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
427 return -1;
428 }
429
430 /* Disable LMAC */
431 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
432 cfg &= ~CMR_EN;
433 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
434
435 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
436 /* Set interleaved running disparity for RXAUI */
437 if (bgx->lmac_type != BGX_MODE_RXAUI)
438 bgx_reg_modify(bgx, lmacid,
439 BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
440 else
441 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
442 SPU_MISC_CTL_RX_DIS | SPU_MISC_CTL_INTLV_RDISP);
443
444 /* clear all interrupts */
445 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
446 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
447 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
448 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
449 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
450 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
451
452 if (bgx->use_training) {
453 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
454 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
455 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
456 /* training enable */
457 bgx_reg_modify(bgx, lmacid,
458 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
459 }
460
461 /* Append FCS to each packet */
462 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
463
464 /* Disable forward error correction */
465 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
466 cfg &= ~SPU_FEC_CTL_FEC_EN;
467 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
468
469 /* Disable autoneg */
470 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
471 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
472 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
473
474 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
475 if (bgx->lmac_type == BGX_MODE_10G_KR)
476 cfg |= (1 << 23);
477 else if (bgx->lmac_type == BGX_MODE_40G_KR)
478 cfg |= (1 << 24);
479 else
480 cfg &= ~((1 << 23) | (1 << 24));
481 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
482 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
483
484 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
485 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
486 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
487
488 /* Enable lmac */
489 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
490
491 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
492 cfg &= ~SPU_CTL_LOW_POWER;
493 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
494
495 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
496 cfg &= ~SMU_TX_CTL_UNI_EN;
497 cfg |= SMU_TX_CTL_DIC_EN;
498 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
499
500 /* take lmac_count into account */
501 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
502 /* max packet size */
503 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
504
505 return 0;
506 }
507
bgx_xaui_check_link(struct lmac * lmac)508 static int bgx_xaui_check_link(struct lmac *lmac)
509 {
510 struct bgx *bgx = lmac->bgx;
511 int lmacid = lmac->lmacid;
512 int lmac_type = bgx->lmac_type;
513 u64 cfg;
514
515 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
516 if (bgx->use_training) {
517 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
518 if (!(cfg & (1ull << 13))) {
519 cfg = (1ull << 13) | (1ull << 14);
520 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
521 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
522 cfg |= (1ull << 0);
523 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
524 return -1;
525 }
526 }
527
528 /* wait for PCS to come out of reset */
529 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
530 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
531 return -1;
532 }
533
534 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
535 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
536 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
537 SPU_BR_STATUS_BLK_LOCK, false)) {
538 dev_err(&bgx->pdev->dev,
539 "SPU_BR_STATUS_BLK_LOCK not completed\n");
540 return -1;
541 }
542 } else {
543 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
544 SPU_BX_STATUS_RX_ALIGN, false)) {
545 dev_err(&bgx->pdev->dev,
546 "SPU_BX_STATUS_RX_ALIGN not completed\n");
547 return -1;
548 }
549 }
550
551 /* Clear rcvflt bit (latching high) and read it back */
552 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
553 bgx_reg_modify(bgx, lmacid,
554 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
555 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
556 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
557 if (bgx->use_training) {
558 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
559 if (!(cfg & (1ull << 13))) {
560 cfg = (1ull << 13) | (1ull << 14);
561 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
562 cfg = bgx_reg_read(bgx, lmacid,
563 BGX_SPUX_BR_PMD_CRTL);
564 cfg |= (1ull << 0);
565 bgx_reg_write(bgx, lmacid,
566 BGX_SPUX_BR_PMD_CRTL, cfg);
567 return -1;
568 }
569 }
570 return -1;
571 }
572
573 /* Wait for BGX RX to be idle */
574 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
575 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
576 return -1;
577 }
578
579 /* Wait for BGX TX to be idle */
580 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
581 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
582 return -1;
583 }
584
585 /* Clear receive packet disable */
586 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
587 cfg &= ~SPU_MISC_CTL_RX_DIS;
588 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
589
590 /* Check for MAC RX faults */
591 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
592 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
593 cfg &= SMU_RX_CTL_STATUS;
594 if (!cfg)
595 return 0;
596
597 /* Rx local/remote fault seen.
598 * Do lmac reinit to see if condition recovers
599 */
600 bgx_lmac_xaui_init(bgx, lmacid, bgx->lmac_type);
601
602 return -1;
603 }
604
bgx_poll_for_link(struct work_struct * work)605 static void bgx_poll_for_link(struct work_struct *work)
606 {
607 struct lmac *lmac;
608 u64 spu_link, smu_link;
609
610 lmac = container_of(work, struct lmac, dwork.work);
611
612 /* Receive link is latching low. Force it high and verify it */
613 bgx_reg_modify(lmac->bgx, lmac->lmacid,
614 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
615 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
616 SPU_STATUS1_RCV_LNK, false);
617
618 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
619 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
620
621 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
622 !(smu_link & SMU_RX_CTL_STATUS)) {
623 lmac->link_up = 1;
624 if (lmac->bgx->lmac_type == BGX_MODE_XLAUI)
625 lmac->last_speed = 40000;
626 else
627 lmac->last_speed = 10000;
628 lmac->last_duplex = 1;
629 } else {
630 lmac->link_up = 0;
631 lmac->last_speed = SPEED_UNKNOWN;
632 lmac->last_duplex = DUPLEX_UNKNOWN;
633 }
634
635 if (lmac->last_link != lmac->link_up) {
636 if (lmac->link_up) {
637 if (bgx_xaui_check_link(lmac)) {
638 /* Errors, clear link_up state */
639 lmac->link_up = 0;
640 lmac->last_speed = SPEED_UNKNOWN;
641 lmac->last_duplex = DUPLEX_UNKNOWN;
642 }
643 }
644 lmac->last_link = lmac->link_up;
645 }
646
647 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
648 }
649
bgx_lmac_enable(struct bgx * bgx,u8 lmacid)650 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
651 {
652 struct lmac *lmac;
653 u64 cfg;
654
655 lmac = &bgx->lmac[lmacid];
656 lmac->bgx = bgx;
657
658 if (bgx->lmac_type == BGX_MODE_SGMII) {
659 lmac->is_sgmii = 1;
660 if (bgx_lmac_sgmii_init(bgx, lmacid))
661 return -1;
662 } else {
663 lmac->is_sgmii = 0;
664 if (bgx_lmac_xaui_init(bgx, lmacid, bgx->lmac_type))
665 return -1;
666 }
667
668 if (lmac->is_sgmii) {
669 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
670 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
671 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
672 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
673 } else {
674 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
675 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
676 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
677 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
678 }
679
680 /* Enable lmac */
681 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
682
683 /* Restore default cfg, incase low level firmware changed it */
684 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
685
686 if ((bgx->lmac_type != BGX_MODE_XFI) &&
687 (bgx->lmac_type != BGX_MODE_XLAUI) &&
688 (bgx->lmac_type != BGX_MODE_40G_KR) &&
689 (bgx->lmac_type != BGX_MODE_10G_KR)) {
690 if (!lmac->phydev)
691 return -ENODEV;
692
693 lmac->phydev->dev_flags = 0;
694
695 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
696 bgx_lmac_handler,
697 PHY_INTERFACE_MODE_SGMII))
698 return -ENODEV;
699
700 phy_start_aneg(lmac->phydev);
701 } else {
702 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
703 WQ_MEM_RECLAIM, 1);
704 if (!lmac->check_link)
705 return -ENOMEM;
706 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
707 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
708 }
709
710 return 0;
711 }
712
bgx_lmac_disable(struct bgx * bgx,u8 lmacid)713 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
714 {
715 struct lmac *lmac;
716 u64 cfg;
717
718 lmac = &bgx->lmac[lmacid];
719 if (lmac->check_link) {
720 /* Destroy work queue */
721 cancel_delayed_work_sync(&lmac->dwork);
722 destroy_workqueue(lmac->check_link);
723 }
724
725 /* Disable packet reception */
726 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
727 cfg &= ~CMR_PKT_RX_EN;
728 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
729
730 /* Give chance for Rx/Tx FIFO to get drained */
731 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
732 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
733
734 /* Disable packet transmission */
735 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
736 cfg &= ~CMR_PKT_TX_EN;
737 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
738
739 /* Disable serdes lanes */
740 if (!lmac->is_sgmii)
741 bgx_reg_modify(bgx, lmacid,
742 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
743 else
744 bgx_reg_modify(bgx, lmacid,
745 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
746
747 /* Disable LMAC */
748 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
749 cfg &= ~CMR_EN;
750 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
751
752 bgx_flush_dmac_addrs(bgx, lmacid);
753
754 if ((bgx->lmac_type != BGX_MODE_XFI) &&
755 (bgx->lmac_type != BGX_MODE_XLAUI) &&
756 (bgx->lmac_type != BGX_MODE_40G_KR) &&
757 (bgx->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
758 phy_disconnect(lmac->phydev);
759
760 lmac->phydev = NULL;
761 }
762
bgx_set_num_ports(struct bgx * bgx)763 static void bgx_set_num_ports(struct bgx *bgx)
764 {
765 u64 lmac_count;
766
767 switch (bgx->qlm_mode) {
768 case QLM_MODE_SGMII:
769 bgx->lmac_count = 4;
770 bgx->lmac_type = BGX_MODE_SGMII;
771 bgx->lane_to_sds = 0;
772 break;
773 case QLM_MODE_XAUI_1X4:
774 bgx->lmac_count = 1;
775 bgx->lmac_type = BGX_MODE_XAUI;
776 bgx->lane_to_sds = 0xE4;
777 break;
778 case QLM_MODE_RXAUI_2X2:
779 bgx->lmac_count = 2;
780 bgx->lmac_type = BGX_MODE_RXAUI;
781 bgx->lane_to_sds = 0xE4;
782 break;
783 case QLM_MODE_XFI_4X1:
784 bgx->lmac_count = 4;
785 bgx->lmac_type = BGX_MODE_XFI;
786 bgx->lane_to_sds = 0;
787 break;
788 case QLM_MODE_XLAUI_1X4:
789 bgx->lmac_count = 1;
790 bgx->lmac_type = BGX_MODE_XLAUI;
791 bgx->lane_to_sds = 0xE4;
792 break;
793 case QLM_MODE_10G_KR_4X1:
794 bgx->lmac_count = 4;
795 bgx->lmac_type = BGX_MODE_10G_KR;
796 bgx->lane_to_sds = 0;
797 bgx->use_training = 1;
798 break;
799 case QLM_MODE_40G_KR4_1X4:
800 bgx->lmac_count = 1;
801 bgx->lmac_type = BGX_MODE_40G_KR;
802 bgx->lane_to_sds = 0xE4;
803 bgx->use_training = 1;
804 break;
805 default:
806 bgx->lmac_count = 0;
807 break;
808 }
809
810 /* Check if low level firmware has programmed LMAC count
811 * based on board type, if yes consider that otherwise
812 * the default static values
813 */
814 lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
815 if (lmac_count != 4)
816 bgx->lmac_count = lmac_count;
817 }
818
bgx_init_hw(struct bgx * bgx)819 static void bgx_init_hw(struct bgx *bgx)
820 {
821 int i;
822
823 bgx_set_num_ports(bgx);
824
825 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
826 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
827 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
828
829 /* Set lmac type and lane2serdes mapping */
830 for (i = 0; i < bgx->lmac_count; i++) {
831 if (bgx->lmac_type == BGX_MODE_RXAUI) {
832 if (i)
833 bgx->lane_to_sds = 0x0e;
834 else
835 bgx->lane_to_sds = 0x04;
836 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
837 (bgx->lmac_type << 8) | bgx->lane_to_sds);
838 continue;
839 }
840 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
841 (bgx->lmac_type << 8) | (bgx->lane_to_sds + i));
842 bgx->lmac[i].lmacid_bd = lmac_count;
843 lmac_count++;
844 }
845
846 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
847 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
848
849 /* Set the backpressure AND mask */
850 for (i = 0; i < bgx->lmac_count; i++)
851 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
852 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
853 (i * MAX_BGX_CHANS_PER_LMAC));
854
855 /* Disable all MAC filtering */
856 for (i = 0; i < RX_DMAC_COUNT; i++)
857 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
858
859 /* Disable MAC steering (NCSI traffic) */
860 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
861 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
862 }
863
bgx_get_qlm_mode(struct bgx * bgx)864 static void bgx_get_qlm_mode(struct bgx *bgx)
865 {
866 struct device *dev = &bgx->pdev->dev;
867 int lmac_type;
868 int train_en;
869
870 /* Read LMAC0 type to figure out QLM mode
871 * This is configured by low level firmware
872 */
873 lmac_type = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
874 lmac_type = (lmac_type >> 8) & 0x07;
875
876 train_en = bgx_reg_read(bgx, 0, BGX_SPUX_BR_PMD_CRTL) &
877 SPU_PMD_CRTL_TRAIN_EN;
878
879 switch (lmac_type) {
880 case BGX_MODE_SGMII:
881 bgx->qlm_mode = QLM_MODE_SGMII;
882 dev_info(dev, "BGX%d QLM mode: SGMII\n", bgx->bgx_id);
883 break;
884 case BGX_MODE_XAUI:
885 bgx->qlm_mode = QLM_MODE_XAUI_1X4;
886 dev_info(dev, "BGX%d QLM mode: XAUI\n", bgx->bgx_id);
887 break;
888 case BGX_MODE_RXAUI:
889 bgx->qlm_mode = QLM_MODE_RXAUI_2X2;
890 dev_info(dev, "BGX%d QLM mode: RXAUI\n", bgx->bgx_id);
891 break;
892 case BGX_MODE_XFI:
893 if (!train_en) {
894 bgx->qlm_mode = QLM_MODE_XFI_4X1;
895 dev_info(dev, "BGX%d QLM mode: XFI\n", bgx->bgx_id);
896 } else {
897 bgx->qlm_mode = QLM_MODE_10G_KR_4X1;
898 dev_info(dev, "BGX%d QLM mode: 10G_KR\n", bgx->bgx_id);
899 }
900 break;
901 case BGX_MODE_XLAUI:
902 if (!train_en) {
903 bgx->qlm_mode = QLM_MODE_XLAUI_1X4;
904 dev_info(dev, "BGX%d QLM mode: XLAUI\n", bgx->bgx_id);
905 } else {
906 bgx->qlm_mode = QLM_MODE_40G_KR4_1X4;
907 dev_info(dev, "BGX%d QLM mode: 40G_KR4\n", bgx->bgx_id);
908 }
909 break;
910 default:
911 bgx->qlm_mode = QLM_MODE_SGMII;
912 dev_info(dev, "BGX%d QLM default mode: SGMII\n", bgx->bgx_id);
913 }
914 }
915
916 #ifdef CONFIG_ACPI
917
acpi_get_mac_address(struct acpi_device * adev,u8 * dst)918 static int acpi_get_mac_address(struct acpi_device *adev, u8 *dst)
919 {
920 u8 mac[ETH_ALEN];
921 int ret;
922
923 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
924 "mac-address", mac, ETH_ALEN);
925 if (ret)
926 goto out;
927
928 if (!is_valid_ether_addr(mac)) {
929 ret = -EINVAL;
930 goto out;
931 }
932
933 memcpy(dst, mac, ETH_ALEN);
934 out:
935 return ret;
936 }
937
938 /* Currently only sets the MAC address. */
bgx_acpi_register_phy(acpi_handle handle,u32 lvl,void * context,void ** rv)939 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
940 u32 lvl, void *context, void **rv)
941 {
942 struct bgx *bgx = context;
943 struct acpi_device *adev;
944
945 if (acpi_bus_get_device(handle, &adev))
946 goto out;
947
948 acpi_get_mac_address(adev, bgx->lmac[bgx->lmac_count].mac);
949
950 SET_NETDEV_DEV(&bgx->lmac[bgx->lmac_count].netdev, &bgx->pdev->dev);
951
952 bgx->lmac[bgx->lmac_count].lmacid = bgx->lmac_count;
953 out:
954 bgx->lmac_count++;
955 return AE_OK;
956 }
957
bgx_acpi_match_id(acpi_handle handle,u32 lvl,void * context,void ** ret_val)958 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
959 void *context, void **ret_val)
960 {
961 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
962 struct bgx *bgx = context;
963 char bgx_sel[5];
964
965 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
966 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
967 pr_warn("Invalid link device\n");
968 return AE_OK;
969 }
970
971 if (strncmp(string.pointer, bgx_sel, 4))
972 return AE_OK;
973
974 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
975 bgx_acpi_register_phy, NULL, bgx, NULL);
976
977 kfree(string.pointer);
978 return AE_CTRL_TERMINATE;
979 }
980
bgx_init_acpi_phy(struct bgx * bgx)981 static int bgx_init_acpi_phy(struct bgx *bgx)
982 {
983 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
984 return 0;
985 }
986
987 #else
988
bgx_init_acpi_phy(struct bgx * bgx)989 static int bgx_init_acpi_phy(struct bgx *bgx)
990 {
991 return -ENODEV;
992 }
993
994 #endif /* CONFIG_ACPI */
995
996 #if IS_ENABLED(CONFIG_OF_MDIO)
997
bgx_init_of_phy(struct bgx * bgx)998 static int bgx_init_of_phy(struct bgx *bgx)
999 {
1000 struct device_node *np;
1001 struct device_node *np_child;
1002 u8 lmac = 0;
1003 char bgx_sel[5];
1004 const char *mac;
1005
1006 /* Get BGX node from DT */
1007 snprintf(bgx_sel, 5, "bgx%d", bgx->bgx_id);
1008 np = of_find_node_by_name(NULL, bgx_sel);
1009 if (!np)
1010 return -ENODEV;
1011
1012 for_each_child_of_node(np, np_child) {
1013 struct device_node *phy_np = of_parse_phandle(np_child,
1014 "phy-handle", 0);
1015 if (!phy_np)
1016 continue;
1017 bgx->lmac[lmac].phydev = of_phy_find_device(phy_np);
1018
1019 mac = of_get_mac_address(np_child);
1020 if (mac)
1021 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1022
1023 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1024 bgx->lmac[lmac].lmacid = lmac;
1025 lmac++;
1026 if (lmac == MAX_LMAC_PER_BGX) {
1027 of_node_put(np_child);
1028 break;
1029 }
1030 }
1031 return 0;
1032 }
1033
1034 #else
1035
bgx_init_of_phy(struct bgx * bgx)1036 static int bgx_init_of_phy(struct bgx *bgx)
1037 {
1038 return -ENODEV;
1039 }
1040
1041 #endif /* CONFIG_OF_MDIO */
1042
bgx_init_phy(struct bgx * bgx)1043 static int bgx_init_phy(struct bgx *bgx)
1044 {
1045 if (!acpi_disabled)
1046 return bgx_init_acpi_phy(bgx);
1047
1048 return bgx_init_of_phy(bgx);
1049 }
1050
bgx_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1051 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1052 {
1053 int err;
1054 struct device *dev = &pdev->dev;
1055 struct bgx *bgx = NULL;
1056 u8 lmac;
1057
1058 /* Load octeon mdio driver */
1059 octeon_mdiobus_force_mod_depencency();
1060
1061 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1062 if (!bgx)
1063 return -ENOMEM;
1064 bgx->pdev = pdev;
1065
1066 pci_set_drvdata(pdev, bgx);
1067
1068 err = pci_enable_device(pdev);
1069 if (err) {
1070 dev_err(dev, "Failed to enable PCI device\n");
1071 pci_set_drvdata(pdev, NULL);
1072 return err;
1073 }
1074
1075 err = pci_request_regions(pdev, DRV_NAME);
1076 if (err) {
1077 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1078 goto err_disable_device;
1079 }
1080
1081 /* MAP configuration registers */
1082 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1083 if (!bgx->reg_base) {
1084 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1085 err = -ENOMEM;
1086 goto err_release_regions;
1087 }
1088 bgx->bgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) & 1;
1089 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_CN88XX;
1090
1091 bgx_vnic[bgx->bgx_id] = bgx;
1092 bgx_get_qlm_mode(bgx);
1093
1094 err = bgx_init_phy(bgx);
1095 if (err)
1096 goto err_enable;
1097
1098 bgx_init_hw(bgx);
1099
1100 /* Enable all LMACs */
1101 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1102 err = bgx_lmac_enable(bgx, lmac);
1103 if (err) {
1104 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1105 bgx->bgx_id, lmac);
1106 goto err_enable;
1107 }
1108 }
1109
1110 return 0;
1111
1112 err_enable:
1113 bgx_vnic[bgx->bgx_id] = NULL;
1114 err_release_regions:
1115 pci_release_regions(pdev);
1116 err_disable_device:
1117 pci_disable_device(pdev);
1118 pci_set_drvdata(pdev, NULL);
1119 return err;
1120 }
1121
bgx_remove(struct pci_dev * pdev)1122 static void bgx_remove(struct pci_dev *pdev)
1123 {
1124 struct bgx *bgx = pci_get_drvdata(pdev);
1125 u8 lmac;
1126
1127 /* Disable all LMACs */
1128 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1129 bgx_lmac_disable(bgx, lmac);
1130
1131 bgx_vnic[bgx->bgx_id] = NULL;
1132 pci_release_regions(pdev);
1133 pci_disable_device(pdev);
1134 pci_set_drvdata(pdev, NULL);
1135 }
1136
1137 static struct pci_driver bgx_driver = {
1138 .name = DRV_NAME,
1139 .id_table = bgx_id_table,
1140 .probe = bgx_probe,
1141 .remove = bgx_remove,
1142 };
1143
bgx_init_module(void)1144 static int __init bgx_init_module(void)
1145 {
1146 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1147
1148 return pci_register_driver(&bgx_driver);
1149 }
1150
bgx_cleanup_module(void)1151 static void __exit bgx_cleanup_module(void)
1152 {
1153 pci_unregister_driver(&bgx_driver);
1154 }
1155
1156 module_init(bgx_init_module);
1157 module_exit(bgx_cleanup_module);
1158