1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Up to 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the IRQF_SHARED flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added IRQF_DISABLED temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
437 present.
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
444 */
445
446 #include <linux/module.h>
447 #include <linux/kernel.h>
448 #include <linux/string.h>
449 #include <linux/interrupt.h>
450 #include <linux/ptrace.h>
451 #include <linux/errno.h>
452 #include <linux/ioport.h>
453 #include <linux/pci.h>
454 #include <linux/eisa.h>
455 #include <linux/delay.h>
456 #include <linux/init.h>
457 #include <linux/spinlock.h>
458 #include <linux/crc32.h>
459 #include <linux/netdevice.h>
460 #include <linux/etherdevice.h>
461 #include <linux/skbuff.h>
462 #include <linux/time.h>
463 #include <linux/types.h>
464 #include <linux/unistd.h>
465 #include <linux/ctype.h>
466 #include <linux/dma-mapping.h>
467 #include <linux/moduleparam.h>
468 #include <linux/bitops.h>
469 #include <linux/gfp.h>
470
471 #include <asm/io.h>
472 #include <asm/dma.h>
473 #include <asm/byteorder.h>
474 #include <asm/unaligned.h>
475 #include <asm/uaccess.h>
476 #ifdef CONFIG_PPC_PMAC
477 #include <asm/machdep.h>
478 #endif /* CONFIG_PPC_PMAC */
479
480 #include "de4x5.h"
481
482 static const char version[] =
483 KERN_INFO "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
484
485 #define c_char const char
486
487 /*
488 ** MII Information
489 */
490 struct phy_table {
491 int reset; /* Hard reset required? */
492 int id; /* IEEE OUI */
493 int ta; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
495 int reg;
496 int mask;
497 int value;
498 } spd;
499 };
500
501 struct mii_phy {
502 int reset; /* Hard reset required? */
503 int id; /* IEEE OUI */
504 int ta; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
506 int reg;
507 int mask;
508 int value;
509 } spd;
510 int addr; /* MII address for the PHY */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
513 u_int mc; /* Media Capabilities */
514 u_int ana; /* NWay Advertisement */
515 u_int fdx; /* Full DupleX capabilities for each media */
516 u_int ttm; /* Transmit Threshold Mode for each media */
517 u_int mci; /* 21142 MII Connector Interrupt info */
518 };
519
520 #define DE4X5_MAX_PHY 8 /* Allow up to 8 attached PHY devices per board */
521
522 struct sia_phy {
523 u_char mc; /* Media Code */
524 u_char ext; /* csr13-15 valid when set */
525 int csr13; /* SIA Connectivity Register */
526 int csr14; /* SIA TX/RX Register */
527 int csr15; /* SIA General Register */
528 int gepc; /* SIA GEP Control Information */
529 int gep; /* SIA GEP Data */
530 };
531
532 /*
533 ** Define the know universe of PHY devices that can be
534 ** recognised by this driver.
535 */
536 static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
542 };
543
544 /*
545 ** These GENERIC values assumes that the PHY devices follow 802.3u and
546 ** allow parallel detection to set the link partner ability register.
547 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
548 */
549 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
552
553 /*
554 ** Define special SROM detection cases
555 */
556 static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559 };
560
561 #define SMC 1
562 #define ACCTON 2
563
564 /*
565 ** SROM Repair definitions. If a broken SROM is detected a card may
566 ** use this information to help figure out what to do. This is a
567 ** "stab in the dark" and so far for SMC9332's only.
568 */
569 static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573 0x00,0x18,}
574 };
575
576
577 #ifdef DE4X5_DEBUG
578 static int de4x5_debug = DE4X5_DEBUG;
579 #else
580 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582 #endif
583
584 /*
585 ** Allow per adapter set up. For modules this is simply a command line
586 ** parameter, e.g.:
587 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
588 **
589 ** For a compiled in driver, place e.g.
590 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
591 ** here
592 */
593 #ifdef DE4X5_PARM
594 static char *args = DE4X5_PARM;
595 #else
596 static char *args;
597 #endif
598
599 struct parameters {
600 bool fdx;
601 int autosense;
602 };
603
604 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
605
606 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
607
608 /*
609 ** Ethernet PROM defines
610 */
611 #define PROBE_LENGTH 32
612 #define ETH_PROM_SIG 0xAA5500FFUL
613
614 /*
615 ** Ethernet Info
616 */
617 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618 #define IEEE802_3_SZ 1518 /* Packet + CRC */
619 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622 #define PKT_HDR_LEN 14 /* Addresses and data length info */
623 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
625
626
627 /*
628 ** EISA bus defines
629 */
630 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
632
633 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
634
635 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636 #define DE4X5_NAME_LENGTH 8
637
638 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
639
640 /*
641 ** Ethernet PROM defines for DC21040
642 */
643 #define PROBE_LENGTH 32
644 #define ETH_PROM_SIG 0xAA5500FFUL
645
646 /*
647 ** PCI Bus defines
648 */
649 #define PCI_MAX_BUS_NUM 8
650 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
652
653 /*
654 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
655 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
657 ** and hence the RX descriptor ring's first entry.
658 */
659 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
665
666 #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
667 #define DE4X5_CACHE_ALIGN CAL_16LONG
668 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
669 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
670 #define DESC_ALIGN
671
672 #ifndef DEC_ONLY /* See README.de4x5 for using this */
673 static int dec_only;
674 #else
675 static int dec_only = 1;
676 #endif
677
678 /*
679 ** DE4X5 IRQ ENABLE/DISABLE
680 */
681 #define ENABLE_IRQs { \
682 imr |= lp->irq_en;\
683 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
684 }
685
686 #define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
688 imr &= ~lp->irq_en;\
689 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
690 }
691
692 #define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
695 }
696
697 #define MASK_IRQs {\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
701 }
702
703 /*
704 ** DE4X5 START/STOP
705 */
706 #define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
710 }
711
712 #define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
716 }
717
718 /*
719 ** DE4X5 SIA RESET
720 */
721 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
722
723 /*
724 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
725 */
726 #define DE4X5_AUTOSENSE_MS 250
727
728 /*
729 ** SROM Structure
730 */
731 struct de4x5_srom {
732 char sub_vendor_id[2];
733 char sub_system_id[2];
734 char reserved[12];
735 char id_block_crc;
736 char reserved2;
737 char version;
738 char num_controllers;
739 char ieee_addr[6];
740 char info[100];
741 short chksum;
742 };
743 #define SUB_VENDOR_ID 0x500a
744
745 /*
746 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747 ** and have sizes of both a power of 2 and a multiple of 4.
748 ** A size of 256 bytes for each buffer could be chosen because over 90% of
749 ** all packets in our network are <256 bytes long and 64 longword alignment
750 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751 ** descriptors are needed for machines with an ALPHA CPU.
752 */
753 #define NUM_RX_DESC 8 /* Number of RX descriptors */
754 #define NUM_TX_DESC 32 /* Number of TX descriptors */
755 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
756 /* Multiple of 4 for DC21040 */
757 /* Allows 512 byte alignment */
758 struct de4x5_desc {
759 volatile __le32 status;
760 __le32 des1;
761 __le32 buf;
762 __le32 next;
763 DESC_ALIGN
764 };
765
766 /*
767 ** The DE4X5 private structure
768 */
769 #define DE4X5_PKT_STAT_SZ 16
770 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
771 increase DE4X5_PKT_STAT_SZ */
772
773 struct pkt_stats {
774 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
775 u_int unicast;
776 u_int multicast;
777 u_int broadcast;
778 u_int excessive_collisions;
779 u_int tx_underruns;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
782 u_int rx_collision;
783 u_int rx_dribble;
784 u_int rx_overflow;
785 };
786
787 struct de4x5_private {
788 char adapter_name[80]; /* Adapter name */
789 u_long interrupt; /* Aligned ISR flag */
790 struct de4x5_desc *rx_ring; /* RX descriptor ring */
791 struct de4x5_desc *tx_ring; /* TX descriptor ring */
792 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
793 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
794 int rx_new, rx_old; /* RX descriptor ring pointers */
795 int tx_new, tx_old; /* TX descriptor ring pointers */
796 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
797 char frame[64]; /* Min sized packet for loopback*/
798 spinlock_t lock; /* Adapter specific spinlock */
799 struct net_device_stats stats; /* Public stats */
800 struct pkt_stats pktStats; /* Private stats counters */
801 char rxRingSize;
802 char txRingSize;
803 int bus; /* EISA or PCI */
804 int bus_num; /* PCI Bus number */
805 int device; /* Device number on PCI bus */
806 int state; /* Adapter OPENED or CLOSED */
807 int chipset; /* DC21040, DC21041 or DC21140 */
808 s32 irq_mask; /* Interrupt Mask (Enable) bits */
809 s32 irq_en; /* Summary interrupt bits */
810 int media; /* Media (eg TP), mode (eg 100B)*/
811 int c_media; /* Remember the last media conn */
812 bool fdx; /* media full duplex flag */
813 int linkOK; /* Link is OK */
814 int autosense; /* Allow/disallow autosensing */
815 bool tx_enable; /* Enable descriptor polling */
816 int setup_f; /* Setup frame filtering type */
817 int local_state; /* State within a 'media' state */
818 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
819 struct sia_phy sia; /* SIA PHY Information */
820 int active; /* Index to active PHY device */
821 int mii_cnt; /* Number of attached PHY's */
822 int timeout; /* Scheduling counter */
823 struct timer_list timer; /* Timer info for kernel */
824 int tmp; /* Temporary global per card */
825 struct {
826 u_long lock; /* Lock the cache accesses */
827 s32 csr0; /* Saved Bus Mode Register */
828 s32 csr6; /* Saved Operating Mode Reg. */
829 s32 csr7; /* Saved IRQ Mask Register */
830 s32 gep; /* Saved General Purpose Reg. */
831 s32 gepc; /* Control info for GEP */
832 s32 csr13; /* Saved SIA Connectivity Reg. */
833 s32 csr14; /* Saved SIA TX/RX Register */
834 s32 csr15; /* Saved SIA General Register */
835 int save_cnt; /* Flag if state already saved */
836 struct sk_buff_head queue; /* Save the (re-ordered) skb's */
837 } cache;
838 struct de4x5_srom srom; /* A copy of the SROM */
839 int cfrv; /* Card CFRV copy */
840 int rx_ovf; /* Check for 'RX overflow' tag */
841 bool useSROM; /* For non-DEC card use SROM */
842 bool useMII; /* Infoblock using the MII */
843 int asBitValid; /* Autosense bits in GEP? */
844 int asPolarity; /* 0 => asserted high */
845 int asBit; /* Autosense bit number in GEP */
846 int defMedium; /* SROM default medium */
847 int tcount; /* Last infoblock number */
848 int infoblock_init; /* Initialised this infoblock? */
849 int infoleaf_offset; /* SROM infoleaf for controller */
850 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
851 int infoblock_media; /* infoblock media */
852 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
853 u_char *rst; /* Pointer to Type 5 reset info */
854 u_char ibn; /* Infoblock number */
855 struct parameters params; /* Command line/ #defined params */
856 struct device *gendev; /* Generic device */
857 dma_addr_t dma_rings; /* DMA handle for rings */
858 int dma_size; /* Size of the DMA area */
859 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
860 };
861
862 /*
863 ** To get around certain poxy cards that don't provide an SROM
864 ** for the second and more DECchip, I have to key off the first
865 ** chip's address. I'll assume there's not a bad SROM iff:
866 **
867 ** o the chipset is the same
868 ** o the bus number is the same and > 0
869 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
870 **
871 ** Also have to save the irq for those cards whose hardware designers
872 ** can't follow the PCI to PCI Bridge Architecture spec.
873 */
874 static struct {
875 int chipset;
876 int bus;
877 int irq;
878 u_char addr[ETH_ALEN];
879 } last = {0,};
880
881 /*
882 ** The transmit ring full condition is described by the tx_old and tx_new
883 ** pointers by:
884 ** tx_old = tx_new Empty ring
885 ** tx_old = tx_new+1 Full ring
886 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
887 */
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
891
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893
894 /*
895 ** Public Functions
896 */
897 static int de4x5_open(struct net_device *dev);
898 static netdev_tx_t de4x5_queue_pkt(struct sk_buff *skb,
899 struct net_device *dev);
900 static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
901 static int de4x5_close(struct net_device *dev);
902 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
903 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
904 static void set_multicast_list(struct net_device *dev);
905 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
906
907 /*
908 ** Private functions
909 */
910 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
911 static int de4x5_init(struct net_device *dev);
912 static int de4x5_sw_reset(struct net_device *dev);
913 static int de4x5_rx(struct net_device *dev);
914 static int de4x5_tx(struct net_device *dev);
915 static void de4x5_ast(struct net_device *dev);
916 static int de4x5_txur(struct net_device *dev);
917 static int de4x5_rx_ovfc(struct net_device *dev);
918
919 static int autoconf_media(struct net_device *dev);
920 static void create_packet(struct net_device *dev, char *frame, int len);
921 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
922 static int dc21040_autoconf(struct net_device *dev);
923 static int dc21041_autoconf(struct net_device *dev);
924 static int dc21140m_autoconf(struct net_device *dev);
925 static int dc2114x_autoconf(struct net_device *dev);
926 static int srom_autoconf(struct net_device *dev);
927 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
928 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
929 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
930 static int test_for_100Mb(struct net_device *dev, int msec);
931 static int wait_for_link(struct net_device *dev);
932 static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec);
933 static int is_spd_100(struct net_device *dev);
934 static int is_100_up(struct net_device *dev);
935 static int is_10_up(struct net_device *dev);
936 static int is_anc_capable(struct net_device *dev);
937 static int ping_media(struct net_device *dev, int msec);
938 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
939 static void de4x5_free_rx_buffs(struct net_device *dev);
940 static void de4x5_free_tx_buffs(struct net_device *dev);
941 static void de4x5_save_skbs(struct net_device *dev);
942 static void de4x5_rst_desc_ring(struct net_device *dev);
943 static void de4x5_cache_state(struct net_device *dev, int flag);
944 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
945 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
946 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
947 static void de4x5_setup_intr(struct net_device *dev);
948 static void de4x5_init_connection(struct net_device *dev);
949 static int de4x5_reset_phy(struct net_device *dev);
950 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
951 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
952 static int test_tp(struct net_device *dev, s32 msec);
953 static int EISA_signature(char *name, struct device *device);
954 static int PCI_signature(char *name, struct de4x5_private *lp);
955 static void DevicePresent(struct net_device *dev, u_long iobase);
956 static void enet_addr_rst(u_long aprom_addr);
957 static int de4x5_bad_srom(struct de4x5_private *lp);
958 static short srom_rd(u_long address, u_char offset);
959 static void srom_latch(u_int command, u_long address);
960 static void srom_command(u_int command, u_long address);
961 static void srom_address(u_int command, u_long address, u_char offset);
962 static short srom_data(u_int command, u_long address);
963 /*static void srom_busy(u_int command, u_long address);*/
964 static void sendto_srom(u_int command, u_long addr);
965 static int getfrom_srom(u_long addr);
966 static int srom_map_media(struct net_device *dev);
967 static int srom_infoleaf_info(struct net_device *dev);
968 static void srom_init(struct net_device *dev);
969 static void srom_exec(struct net_device *dev, u_char *p);
970 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972 static int mii_rdata(u_long ioaddr);
973 static void mii_wdata(int data, int len, u_long ioaddr);
974 static void mii_ta(u_long rw, u_long ioaddr);
975 static int mii_swap(int data, int len);
976 static void mii_address(u_char addr, u_long ioaddr);
977 static void sendto_mii(u32 command, int data, u_long ioaddr);
978 static int getfrom_mii(u32 command, u_long ioaddr);
979 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
980 static int mii_get_phy(struct net_device *dev);
981 static void SetMulticastFilter(struct net_device *dev);
982 static int get_hw_addr(struct net_device *dev);
983 static void srom_repair(struct net_device *dev, int card);
984 static int test_bad_enet(struct net_device *dev, int status);
985 static int an_exception(struct de4x5_private *lp);
986 static char *build_setup_frame(struct net_device *dev, int mode);
987 static void disable_ast(struct net_device *dev);
988 static long de4x5_switch_mac_port(struct net_device *dev);
989 static int gep_rd(struct net_device *dev);
990 static void gep_wr(s32 data, struct net_device *dev);
991 static void yawn(struct net_device *dev, int state);
992 static void de4x5_parse_params(struct net_device *dev);
993 static void de4x5_dbg_open(struct net_device *dev);
994 static void de4x5_dbg_mii(struct net_device *dev, int k);
995 static void de4x5_dbg_media(struct net_device *dev);
996 static void de4x5_dbg_srom(struct de4x5_srom *p);
997 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
998 static int dc21041_infoleaf(struct net_device *dev);
999 static int dc21140_infoleaf(struct net_device *dev);
1000 static int dc21142_infoleaf(struct net_device *dev);
1001 static int dc21143_infoleaf(struct net_device *dev);
1002 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1003 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1004 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1005 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1006 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1007 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1008 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1009
1010 /*
1011 ** Note now that module autoprobing is allowed under EISA and PCI. The
1012 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1013 ** to "do the right thing".
1014 */
1015
1016 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1017
1018 module_param(io, int, 0);
1019 module_param(de4x5_debug, int, 0);
1020 module_param(dec_only, int, 0);
1021 module_param(args, charp, 0);
1022
1023 MODULE_PARM_DESC(io, "de4x5 I/O base address");
1024 MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1025 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1026 MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1027 MODULE_LICENSE("GPL");
1028
1029 /*
1030 ** List the SROM infoleaf functions and chipsets
1031 */
1032 struct InfoLeaf {
1033 int chipset;
1034 int (*fn)(struct net_device *);
1035 };
1036 static struct InfoLeaf infoleaf_array[] = {
1037 {DC21041, dc21041_infoleaf},
1038 {DC21140, dc21140_infoleaf},
1039 {DC21142, dc21142_infoleaf},
1040 {DC21143, dc21143_infoleaf}
1041 };
1042 #define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array)
1043
1044 /*
1045 ** List the SROM info block functions
1046 */
1047 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1048 type0_infoblock,
1049 type1_infoblock,
1050 type2_infoblock,
1051 type3_infoblock,
1052 type4_infoblock,
1053 type5_infoblock,
1054 compact_infoblock
1055 };
1056
1057 #define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1058
1059 /*
1060 ** Miscellaneous defines...
1061 */
1062 #define RESET_DE4X5 {\
1063 int i;\
1064 i=inl(DE4X5_BMR);\
1065 mdelay(1);\
1066 outl(i | BMR_SWR, DE4X5_BMR);\
1067 mdelay(1);\
1068 outl(i, DE4X5_BMR);\
1069 mdelay(1);\
1070 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1071 mdelay(1);\
1072 }
1073
1074 #define PHY_HARD_RESET {\
1075 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1076 mdelay(1); /* Assert for 1ms */\
1077 outl(0x00, DE4X5_GEP);\
1078 mdelay(2); /* Wait for 2ms */\
1079 }
1080
1081 static const struct net_device_ops de4x5_netdev_ops = {
1082 .ndo_open = de4x5_open,
1083 .ndo_stop = de4x5_close,
1084 .ndo_start_xmit = de4x5_queue_pkt,
1085 .ndo_get_stats = de4x5_get_stats,
1086 .ndo_set_rx_mode = set_multicast_list,
1087 .ndo_do_ioctl = de4x5_ioctl,
1088 .ndo_change_mtu = eth_change_mtu,
1089 .ndo_set_mac_address= eth_mac_addr,
1090 .ndo_validate_addr = eth_validate_addr,
1091 };
1092
1093
1094 static int
de4x5_hw_init(struct net_device * dev,u_long iobase,struct device * gendev)1095 de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1096 {
1097 char name[DE4X5_NAME_LENGTH + 1];
1098 struct de4x5_private *lp = netdev_priv(dev);
1099 struct pci_dev *pdev = NULL;
1100 int i, status=0;
1101
1102 dev_set_drvdata(gendev, dev);
1103
1104 /* Ensure we're not sleeping */
1105 if (lp->bus == EISA) {
1106 outb(WAKEUP, PCI_CFPM);
1107 } else {
1108 pdev = to_pci_dev (gendev);
1109 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1110 }
1111 mdelay(10);
1112
1113 RESET_DE4X5;
1114
1115 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1116 return -ENXIO; /* Hardware could not reset */
1117 }
1118
1119 /*
1120 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1121 */
1122 lp->useSROM = false;
1123 if (lp->bus == PCI) {
1124 PCI_signature(name, lp);
1125 } else {
1126 EISA_signature(name, gendev);
1127 }
1128
1129 if (*name == '\0') { /* Not found a board signature */
1130 return -ENXIO;
1131 }
1132
1133 dev->base_addr = iobase;
1134 printk ("%s: %s at 0x%04lx", dev_name(gendev), name, iobase);
1135
1136 status = get_hw_addr(dev);
1137 printk(", h/w address %pM\n", dev->dev_addr);
1138
1139 if (status != 0) {
1140 printk(" which has an Ethernet PROM CRC error.\n");
1141 return -ENXIO;
1142 } else {
1143 skb_queue_head_init(&lp->cache.queue);
1144 lp->cache.gepc = GEP_INIT;
1145 lp->asBit = GEP_SLNK;
1146 lp->asPolarity = GEP_SLNK;
1147 lp->asBitValid = ~0;
1148 lp->timeout = -1;
1149 lp->gendev = gendev;
1150 spin_lock_init(&lp->lock);
1151 init_timer(&lp->timer);
1152 lp->timer.function = (void (*)(unsigned long))de4x5_ast;
1153 lp->timer.data = (unsigned long)dev;
1154 de4x5_parse_params(dev);
1155
1156 /*
1157 ** Choose correct autosensing in case someone messed up
1158 */
1159 lp->autosense = lp->params.autosense;
1160 if (lp->chipset != DC21140) {
1161 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1162 lp->params.autosense = TP;
1163 }
1164 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1165 lp->params.autosense = BNC;
1166 }
1167 }
1168 lp->fdx = lp->params.fdx;
1169 sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev));
1170
1171 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1172 #if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
1173 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1174 #endif
1175 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1176 &lp->dma_rings, GFP_ATOMIC);
1177 if (lp->rx_ring == NULL) {
1178 return -ENOMEM;
1179 }
1180
1181 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1182
1183 /*
1184 ** Set up the RX descriptor ring (Intels)
1185 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1186 */
1187 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1188 for (i=0; i<NUM_RX_DESC; i++) {
1189 lp->rx_ring[i].status = 0;
1190 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1191 lp->rx_ring[i].buf = 0;
1192 lp->rx_ring[i].next = 0;
1193 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1194 }
1195
1196 #else
1197 {
1198 dma_addr_t dma_rx_bufs;
1199
1200 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1201 * sizeof(struct de4x5_desc);
1202 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1203 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1204 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1205 for (i=0; i<NUM_RX_DESC; i++) {
1206 lp->rx_ring[i].status = 0;
1207 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1208 lp->rx_ring[i].buf =
1209 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1210 lp->rx_ring[i].next = 0;
1211 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1212 }
1213
1214 }
1215 #endif
1216
1217 barrier();
1218
1219 lp->rxRingSize = NUM_RX_DESC;
1220 lp->txRingSize = NUM_TX_DESC;
1221
1222 /* Write the end of list marker to the descriptor lists */
1223 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1224 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1225
1226 /* Tell the adapter where the TX/RX rings are located. */
1227 outl(lp->dma_rings, DE4X5_RRBA);
1228 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1229 DE4X5_TRBA);
1230
1231 /* Initialise the IRQ mask and Enable/Disable */
1232 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1233 lp->irq_en = IMR_NIM | IMR_AIM;
1234
1235 /* Create a loopback packet frame for later media probing */
1236 create_packet(dev, lp->frame, sizeof(lp->frame));
1237
1238 /* Check if the RX overflow bug needs testing for */
1239 i = lp->cfrv & 0x000000fe;
1240 if ((lp->chipset == DC21140) && (i == 0x20)) {
1241 lp->rx_ovf = 1;
1242 }
1243
1244 /* Initialise the SROM pointers if possible */
1245 if (lp->useSROM) {
1246 lp->state = INITIALISED;
1247 if (srom_infoleaf_info(dev)) {
1248 dma_free_coherent (gendev, lp->dma_size,
1249 lp->rx_ring, lp->dma_rings);
1250 return -ENXIO;
1251 }
1252 srom_init(dev);
1253 }
1254
1255 lp->state = CLOSED;
1256
1257 /*
1258 ** Check for an MII interface
1259 */
1260 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1261 mii_get_phy(dev);
1262 }
1263
1264 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1265 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1266 }
1267
1268 if (de4x5_debug & DEBUG_VERSION) {
1269 printk(version);
1270 }
1271
1272 /* The DE4X5-specific entries in the device structure. */
1273 SET_NETDEV_DEV(dev, gendev);
1274 dev->netdev_ops = &de4x5_netdev_ops;
1275 dev->mem_start = 0;
1276
1277 /* Fill in the generic fields of the device structure. */
1278 if ((status = register_netdev (dev))) {
1279 dma_free_coherent (gendev, lp->dma_size,
1280 lp->rx_ring, lp->dma_rings);
1281 return status;
1282 }
1283
1284 /* Let the adapter sleep to save power */
1285 yawn(dev, SLEEP);
1286
1287 return status;
1288 }
1289
1290
1291 static int
de4x5_open(struct net_device * dev)1292 de4x5_open(struct net_device *dev)
1293 {
1294 struct de4x5_private *lp = netdev_priv(dev);
1295 u_long iobase = dev->base_addr;
1296 int i, status = 0;
1297 s32 omr;
1298
1299 /* Allocate the RX buffers */
1300 for (i=0; i<lp->rxRingSize; i++) {
1301 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1302 de4x5_free_rx_buffs(dev);
1303 return -EAGAIN;
1304 }
1305 }
1306
1307 /*
1308 ** Wake up the adapter
1309 */
1310 yawn(dev, WAKEUP);
1311
1312 /*
1313 ** Re-initialize the DE4X5...
1314 */
1315 status = de4x5_init(dev);
1316 spin_lock_init(&lp->lock);
1317 lp->state = OPEN;
1318 de4x5_dbg_open(dev);
1319
1320 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1321 lp->adapter_name, dev)) {
1322 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1323 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1324 lp->adapter_name, dev)) {
1325 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1326 disable_ast(dev);
1327 de4x5_free_rx_buffs(dev);
1328 de4x5_free_tx_buffs(dev);
1329 yawn(dev, SLEEP);
1330 lp->state = CLOSED;
1331 return -EAGAIN;
1332 } else {
1333 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1334 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1335 }
1336 }
1337
1338 lp->interrupt = UNMASK_INTERRUPTS;
1339 dev->trans_start = jiffies; /* prevent tx timeout */
1340
1341 START_DE4X5;
1342
1343 de4x5_setup_intr(dev);
1344
1345 if (de4x5_debug & DEBUG_OPEN) {
1346 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1347 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1348 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1349 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1350 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1351 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1352 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1353 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1354 }
1355
1356 return status;
1357 }
1358
1359 /*
1360 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1361 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1362 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1363 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1364 ** to be data corruption problems if it is larger (UDP errors seen from a
1365 ** ttcp source).
1366 */
1367 static int
de4x5_init(struct net_device * dev)1368 de4x5_init(struct net_device *dev)
1369 {
1370 /* Lock out other processes whilst setting up the hardware */
1371 netif_stop_queue(dev);
1372
1373 de4x5_sw_reset(dev);
1374
1375 /* Autoconfigure the connected port */
1376 autoconf_media(dev);
1377
1378 return 0;
1379 }
1380
1381 static int
de4x5_sw_reset(struct net_device * dev)1382 de4x5_sw_reset(struct net_device *dev)
1383 {
1384 struct de4x5_private *lp = netdev_priv(dev);
1385 u_long iobase = dev->base_addr;
1386 int i, j, status = 0;
1387 s32 bmr, omr;
1388
1389 /* Select the MII or SRL port now and RESET the MAC */
1390 if (!lp->useSROM) {
1391 if (lp->phy[lp->active].id != 0) {
1392 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1393 } else {
1394 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1395 }
1396 de4x5_switch_mac_port(dev);
1397 }
1398
1399 /*
1400 ** Set the programmable burst length to 8 longwords for all the DC21140
1401 ** Fasternet chips and 4 longwords for all others: DMA errors result
1402 ** without these values. Cache align 16 long.
1403 */
1404 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1405 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1406 outl(bmr, DE4X5_BMR);
1407
1408 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1409 if (lp->chipset == DC21140) {
1410 omr |= (OMR_SDP | OMR_SB);
1411 }
1412 lp->setup_f = PERFECT;
1413 outl(lp->dma_rings, DE4X5_RRBA);
1414 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1415 DE4X5_TRBA);
1416
1417 lp->rx_new = lp->rx_old = 0;
1418 lp->tx_new = lp->tx_old = 0;
1419
1420 for (i = 0; i < lp->rxRingSize; i++) {
1421 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1422 }
1423
1424 for (i = 0; i < lp->txRingSize; i++) {
1425 lp->tx_ring[i].status = cpu_to_le32(0);
1426 }
1427
1428 barrier();
1429
1430 /* Build the setup frame depending on filtering mode */
1431 SetMulticastFilter(dev);
1432
1433 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1434 outl(omr|OMR_ST, DE4X5_OMR);
1435
1436 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1437
1438 for (j=0, i=0;(i<500) && (j==0);i++) { /* Up to 500ms delay */
1439 mdelay(1);
1440 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1441 }
1442 outl(omr, DE4X5_OMR); /* Stop everything! */
1443
1444 if (j == 0) {
1445 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1446 inl(DE4X5_STS));
1447 status = -EIO;
1448 }
1449
1450 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1451 lp->tx_old = lp->tx_new;
1452
1453 return status;
1454 }
1455
1456 /*
1457 ** Writes a socket buffer address to the next available transmit descriptor.
1458 */
1459 static netdev_tx_t
de4x5_queue_pkt(struct sk_buff * skb,struct net_device * dev)1460 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1461 {
1462 struct de4x5_private *lp = netdev_priv(dev);
1463 u_long iobase = dev->base_addr;
1464 u_long flags = 0;
1465
1466 netif_stop_queue(dev);
1467 if (!lp->tx_enable) /* Cannot send for now */
1468 return NETDEV_TX_LOCKED;
1469
1470 /*
1471 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1472 ** interrupts are lost by delayed descriptor status updates relative to
1473 ** the irq assertion, especially with a busy PCI bus.
1474 */
1475 spin_lock_irqsave(&lp->lock, flags);
1476 de4x5_tx(dev);
1477 spin_unlock_irqrestore(&lp->lock, flags);
1478
1479 /* Test if cache is already locked - requeue skb if so */
1480 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1481 return NETDEV_TX_LOCKED;
1482
1483 /* Transmit descriptor ring full or stale skb */
1484 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1485 if (lp->interrupt) {
1486 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1487 } else {
1488 de4x5_put_cache(dev, skb);
1489 }
1490 if (de4x5_debug & DEBUG_TX) {
1491 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1492 }
1493 } else if (skb->len > 0) {
1494 /* If we already have stuff queued locally, use that first */
1495 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1496 de4x5_put_cache(dev, skb);
1497 skb = de4x5_get_cache(dev);
1498 }
1499
1500 while (skb && !netif_queue_stopped(dev) &&
1501 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1502 spin_lock_irqsave(&lp->lock, flags);
1503 netif_stop_queue(dev);
1504 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1505 lp->stats.tx_bytes += skb->len;
1506 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1507
1508 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1509
1510 if (TX_BUFFS_AVAIL) {
1511 netif_start_queue(dev); /* Another pkt may be queued */
1512 }
1513 skb = de4x5_get_cache(dev);
1514 spin_unlock_irqrestore(&lp->lock, flags);
1515 }
1516 if (skb) de4x5_putb_cache(dev, skb);
1517 }
1518
1519 lp->cache.lock = 0;
1520
1521 return NETDEV_TX_OK;
1522 }
1523
1524 /*
1525 ** The DE4X5 interrupt handler.
1526 **
1527 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1528 ** so that the asserted interrupt always has some real data to work with -
1529 ** if these I/O accesses are ever changed to memory accesses, ensure the
1530 ** STS write is read immediately to complete the transaction if the adapter
1531 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1532 ** is high and descriptor status bits cannot be set before the associated
1533 ** interrupt is asserted and this routine entered.
1534 */
1535 static irqreturn_t
de4x5_interrupt(int irq,void * dev_id)1536 de4x5_interrupt(int irq, void *dev_id)
1537 {
1538 struct net_device *dev = dev_id;
1539 struct de4x5_private *lp;
1540 s32 imr, omr, sts, limit;
1541 u_long iobase;
1542 unsigned int handled = 0;
1543
1544 lp = netdev_priv(dev);
1545 spin_lock(&lp->lock);
1546 iobase = dev->base_addr;
1547
1548 DISABLE_IRQs; /* Ensure non re-entrancy */
1549
1550 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1551 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1552
1553 synchronize_irq(dev->irq);
1554
1555 for (limit=0; limit<8; limit++) {
1556 sts = inl(DE4X5_STS); /* Read IRQ status */
1557 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1558
1559 if (!(sts & lp->irq_mask)) break;/* All done */
1560 handled = 1;
1561
1562 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1563 de4x5_rx(dev);
1564
1565 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1566 de4x5_tx(dev);
1567
1568 if (sts & STS_LNF) { /* TP Link has failed */
1569 lp->irq_mask &= ~IMR_LFM;
1570 }
1571
1572 if (sts & STS_UNF) { /* Transmit underrun */
1573 de4x5_txur(dev);
1574 }
1575
1576 if (sts & STS_SE) { /* Bus Error */
1577 STOP_DE4X5;
1578 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1579 dev->name, sts);
1580 spin_unlock(&lp->lock);
1581 return IRQ_HANDLED;
1582 }
1583 }
1584
1585 /* Load the TX ring with any locally stored packets */
1586 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1587 while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) {
1588 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1589 }
1590 lp->cache.lock = 0;
1591 }
1592
1593 lp->interrupt = UNMASK_INTERRUPTS;
1594 ENABLE_IRQs;
1595 spin_unlock(&lp->lock);
1596
1597 return IRQ_RETVAL(handled);
1598 }
1599
1600 static int
de4x5_rx(struct net_device * dev)1601 de4x5_rx(struct net_device *dev)
1602 {
1603 struct de4x5_private *lp = netdev_priv(dev);
1604 u_long iobase = dev->base_addr;
1605 int entry;
1606 s32 status;
1607
1608 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1609 entry=lp->rx_new) {
1610 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1611
1612 if (lp->rx_ovf) {
1613 if (inl(DE4X5_MFC) & MFC_FOCM) {
1614 de4x5_rx_ovfc(dev);
1615 break;
1616 }
1617 }
1618
1619 if (status & RD_FS) { /* Remember the start of frame */
1620 lp->rx_old = entry;
1621 }
1622
1623 if (status & RD_LS) { /* Valid frame status */
1624 if (lp->tx_enable) lp->linkOK++;
1625 if (status & RD_ES) { /* There was an error. */
1626 lp->stats.rx_errors++; /* Update the error stats. */
1627 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1628 if (status & RD_CE) lp->stats.rx_crc_errors++;
1629 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1630 if (status & RD_TL) lp->stats.rx_length_errors++;
1631 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1632 if (status & RD_CS) lp->pktStats.rx_collision++;
1633 if (status & RD_DB) lp->pktStats.rx_dribble++;
1634 if (status & RD_OF) lp->pktStats.rx_overflow++;
1635 } else { /* A valid frame received */
1636 struct sk_buff *skb;
1637 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1638 >> 16) - 4;
1639
1640 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1641 printk("%s: Insufficient memory; nuking packet.\n",
1642 dev->name);
1643 lp->stats.rx_dropped++;
1644 } else {
1645 de4x5_dbg_rx(skb, pkt_len);
1646
1647 /* Push up the protocol stack */
1648 skb->protocol=eth_type_trans(skb,dev);
1649 de4x5_local_stats(dev, skb->data, pkt_len);
1650 netif_rx(skb);
1651
1652 /* Update stats */
1653 lp->stats.rx_packets++;
1654 lp->stats.rx_bytes += pkt_len;
1655 }
1656 }
1657
1658 /* Change buffer ownership for this frame, back to the adapter */
1659 for (;lp->rx_old!=entry;lp->rx_old=(lp->rx_old + 1)%lp->rxRingSize) {
1660 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1661 barrier();
1662 }
1663 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1664 barrier();
1665 }
1666
1667 /*
1668 ** Update entry information
1669 */
1670 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1671 }
1672
1673 return 0;
1674 }
1675
1676 static inline void
de4x5_free_tx_buff(struct de4x5_private * lp,int entry)1677 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1678 {
1679 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1680 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1681 DMA_TO_DEVICE);
1682 if ((u_long) lp->tx_skb[entry] > 1)
1683 dev_kfree_skb_irq(lp->tx_skb[entry]);
1684 lp->tx_skb[entry] = NULL;
1685 }
1686
1687 /*
1688 ** Buffer sent - check for TX buffer errors.
1689 */
1690 static int
de4x5_tx(struct net_device * dev)1691 de4x5_tx(struct net_device *dev)
1692 {
1693 struct de4x5_private *lp = netdev_priv(dev);
1694 u_long iobase = dev->base_addr;
1695 int entry;
1696 s32 status;
1697
1698 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1699 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1700 if (status < 0) { /* Buffer not sent yet */
1701 break;
1702 } else if (status != 0x7fffffff) { /* Not setup frame */
1703 if (status & TD_ES) { /* An error happened */
1704 lp->stats.tx_errors++;
1705 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1706 if (status & TD_LC) lp->stats.tx_window_errors++;
1707 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1708 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1709 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1710
1711 if (TX_PKT_PENDING) {
1712 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1713 }
1714 } else { /* Packet sent */
1715 lp->stats.tx_packets++;
1716 if (lp->tx_enable) lp->linkOK++;
1717 }
1718 /* Update the collision counter */
1719 lp->stats.collisions += ((status & TD_EC) ? 16 :
1720 ((status & TD_CC) >> 3));
1721
1722 /* Free the buffer. */
1723 if (lp->tx_skb[entry] != NULL)
1724 de4x5_free_tx_buff(lp, entry);
1725 }
1726
1727 /* Update all the pointers */
1728 lp->tx_old = (lp->tx_old + 1) % lp->txRingSize;
1729 }
1730
1731 /* Any resources available? */
1732 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1733 if (lp->interrupt)
1734 netif_wake_queue(dev);
1735 else
1736 netif_start_queue(dev);
1737 }
1738
1739 return 0;
1740 }
1741
1742 static void
de4x5_ast(struct net_device * dev)1743 de4x5_ast(struct net_device *dev)
1744 {
1745 struct de4x5_private *lp = netdev_priv(dev);
1746 int next_tick = DE4X5_AUTOSENSE_MS;
1747 int dt;
1748
1749 if (lp->useSROM)
1750 next_tick = srom_autoconf(dev);
1751 else if (lp->chipset == DC21140)
1752 next_tick = dc21140m_autoconf(dev);
1753 else if (lp->chipset == DC21041)
1754 next_tick = dc21041_autoconf(dev);
1755 else if (lp->chipset == DC21040)
1756 next_tick = dc21040_autoconf(dev);
1757 lp->linkOK = 0;
1758
1759 dt = (next_tick * HZ) / 1000;
1760
1761 if (!dt)
1762 dt = 1;
1763
1764 mod_timer(&lp->timer, jiffies + dt);
1765 }
1766
1767 static int
de4x5_txur(struct net_device * dev)1768 de4x5_txur(struct net_device *dev)
1769 {
1770 struct de4x5_private *lp = netdev_priv(dev);
1771 u_long iobase = dev->base_addr;
1772 int omr;
1773
1774 omr = inl(DE4X5_OMR);
1775 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1776 omr &= ~(OMR_ST|OMR_SR);
1777 outl(omr, DE4X5_OMR);
1778 while (inl(DE4X5_STS) & STS_TS);
1779 if ((omr & OMR_TR) < OMR_TR) {
1780 omr += 0x4000;
1781 } else {
1782 omr |= OMR_SF;
1783 }
1784 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1785 }
1786
1787 return 0;
1788 }
1789
1790 static int
de4x5_rx_ovfc(struct net_device * dev)1791 de4x5_rx_ovfc(struct net_device *dev)
1792 {
1793 struct de4x5_private *lp = netdev_priv(dev);
1794 u_long iobase = dev->base_addr;
1795 int omr;
1796
1797 omr = inl(DE4X5_OMR);
1798 outl(omr & ~OMR_SR, DE4X5_OMR);
1799 while (inl(DE4X5_STS) & STS_RS);
1800
1801 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1802 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1803 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1804 }
1805
1806 outl(omr, DE4X5_OMR);
1807
1808 return 0;
1809 }
1810
1811 static int
de4x5_close(struct net_device * dev)1812 de4x5_close(struct net_device *dev)
1813 {
1814 struct de4x5_private *lp = netdev_priv(dev);
1815 u_long iobase = dev->base_addr;
1816 s32 imr, omr;
1817
1818 disable_ast(dev);
1819
1820 netif_stop_queue(dev);
1821
1822 if (de4x5_debug & DEBUG_CLOSE) {
1823 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1824 dev->name, inl(DE4X5_STS));
1825 }
1826
1827 /*
1828 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1829 */
1830 DISABLE_IRQs;
1831 STOP_DE4X5;
1832
1833 /* Free the associated irq */
1834 free_irq(dev->irq, dev);
1835 lp->state = CLOSED;
1836
1837 /* Free any socket buffers */
1838 de4x5_free_rx_buffs(dev);
1839 de4x5_free_tx_buffs(dev);
1840
1841 /* Put the adapter to sleep to save power */
1842 yawn(dev, SLEEP);
1843
1844 return 0;
1845 }
1846
1847 static struct net_device_stats *
de4x5_get_stats(struct net_device * dev)1848 de4x5_get_stats(struct net_device *dev)
1849 {
1850 struct de4x5_private *lp = netdev_priv(dev);
1851 u_long iobase = dev->base_addr;
1852
1853 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1854
1855 return &lp->stats;
1856 }
1857
1858 static void
de4x5_local_stats(struct net_device * dev,char * buf,int pkt_len)1859 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1860 {
1861 struct de4x5_private *lp = netdev_priv(dev);
1862 int i;
1863
1864 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1865 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1866 lp->pktStats.bins[i]++;
1867 i = DE4X5_PKT_STAT_SZ;
1868 }
1869 }
1870 if (is_multicast_ether_addr(buf)) {
1871 if (is_broadcast_ether_addr(buf)) {
1872 lp->pktStats.broadcast++;
1873 } else {
1874 lp->pktStats.multicast++;
1875 }
1876 } else if (ether_addr_equal(buf, dev->dev_addr)) {
1877 lp->pktStats.unicast++;
1878 }
1879
1880 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1881 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1882 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1883 }
1884 }
1885
1886 /*
1887 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1888 ** If the flag is changed on a descriptor that is being read by the hardware,
1889 ** I assume PCI transaction ordering will mean you are either successful or
1890 ** just miss asserting the change to the hardware. Anyway you're messing with
1891 ** a descriptor you don't own, but this shouldn't kill the chip provided
1892 ** the descriptor register is read only to the hardware.
1893 */
1894 static void
load_packet(struct net_device * dev,char * buf,u32 flags,struct sk_buff * skb)1895 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1896 {
1897 struct de4x5_private *lp = netdev_priv(dev);
1898 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1899 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1900
1901 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1902 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1903 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1904 lp->tx_skb[lp->tx_new] = skb;
1905 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1906 barrier();
1907
1908 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1909 barrier();
1910 }
1911
1912 /*
1913 ** Set or clear the multicast filter for this adaptor.
1914 */
1915 static void
set_multicast_list(struct net_device * dev)1916 set_multicast_list(struct net_device *dev)
1917 {
1918 struct de4x5_private *lp = netdev_priv(dev);
1919 u_long iobase = dev->base_addr;
1920
1921 /* First, double check that the adapter is open */
1922 if (lp->state == OPEN) {
1923 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1924 u32 omr;
1925 omr = inl(DE4X5_OMR);
1926 omr |= OMR_PR;
1927 outl(omr, DE4X5_OMR);
1928 } else {
1929 SetMulticastFilter(dev);
1930 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1931 SETUP_FRAME_LEN, (struct sk_buff *)1);
1932
1933 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1934 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1935 dev->trans_start = jiffies; /* prevent tx timeout */
1936 }
1937 }
1938 }
1939
1940 /*
1941 ** Calculate the hash code and update the logical address filter
1942 ** from a list of ethernet multicast addresses.
1943 ** Little endian crc one liner from Matt Thomas, DEC.
1944 */
1945 static void
SetMulticastFilter(struct net_device * dev)1946 SetMulticastFilter(struct net_device *dev)
1947 {
1948 struct de4x5_private *lp = netdev_priv(dev);
1949 struct netdev_hw_addr *ha;
1950 u_long iobase = dev->base_addr;
1951 int i, bit, byte;
1952 u16 hashcode;
1953 u32 omr, crc;
1954 char *pa;
1955 unsigned char *addrs;
1956
1957 omr = inl(DE4X5_OMR);
1958 omr &= ~(OMR_PR | OMR_PM);
1959 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1960
1961 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 14)) {
1962 omr |= OMR_PM; /* Pass all multicasts */
1963 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1964 netdev_for_each_mc_addr(ha, dev) {
1965 crc = ether_crc_le(ETH_ALEN, ha->addr);
1966 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1967
1968 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1969 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1970
1971 byte <<= 1; /* calc offset into setup frame */
1972 if (byte & 0x02) {
1973 byte -= 1;
1974 }
1975 lp->setup_frame[byte] |= bit;
1976 }
1977 } else { /* Perfect filtering */
1978 netdev_for_each_mc_addr(ha, dev) {
1979 addrs = ha->addr;
1980 for (i=0; i<ETH_ALEN; i++) {
1981 *(pa + (i&1)) = *addrs++;
1982 if (i & 0x01) pa += 4;
1983 }
1984 }
1985 }
1986 outl(omr, DE4X5_OMR);
1987 }
1988
1989 #ifdef CONFIG_EISA
1990
1991 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1992
de4x5_eisa_probe(struct device * gendev)1993 static int de4x5_eisa_probe(struct device *gendev)
1994 {
1995 struct eisa_device *edev;
1996 u_long iobase;
1997 u_char irq, regval;
1998 u_short vendor;
1999 u32 cfid;
2000 int status, device;
2001 struct net_device *dev;
2002 struct de4x5_private *lp;
2003
2004 edev = to_eisa_device (gendev);
2005 iobase = edev->base_addr;
2006
2007 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2008 return -EBUSY;
2009
2010 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2011 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2012 status = -EBUSY;
2013 goto release_reg_1;
2014 }
2015
2016 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2017 status = -ENOMEM;
2018 goto release_reg_2;
2019 }
2020 lp = netdev_priv(dev);
2021
2022 cfid = (u32) inl(PCI_CFID);
2023 lp->cfrv = (u_short) inl(PCI_CFRV);
2024 device = (cfid >> 8) & 0x00ffff00;
2025 vendor = (u_short) cfid;
2026
2027 /* Read the EISA Configuration Registers */
2028 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2029 #ifdef CONFIG_ALPHA
2030 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2031 * care about the EISA configuration, and thus doesn't
2032 * configure the PLX bridge properly. Oh well... Simply mimic
2033 * the EISA config file to sort it out. */
2034
2035 /* EISA REG1: Assert DecChip 21040 HW Reset */
2036 outb (ER1_IAM | 1, EISA_REG1);
2037 mdelay (1);
2038
2039 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2040 outb (ER1_IAM, EISA_REG1);
2041 mdelay (1);
2042
2043 /* EISA REG3: R/W Burst Transfer Enable */
2044 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2045
2046 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2047 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2048 #endif
2049 irq = de4x5_irq[(regval >> 1) & 0x03];
2050
2051 if (is_DC2114x) {
2052 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2053 }
2054 lp->chipset = device;
2055 lp->bus = EISA;
2056
2057 /* Write the PCI Configuration Registers */
2058 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2059 outl(0x00006000, PCI_CFLT);
2060 outl(iobase, PCI_CBIO);
2061
2062 DevicePresent(dev, EISA_APROM);
2063
2064 dev->irq = irq;
2065
2066 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2067 return 0;
2068 }
2069
2070 free_netdev (dev);
2071 release_reg_2:
2072 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2073 release_reg_1:
2074 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2075
2076 return status;
2077 }
2078
de4x5_eisa_remove(struct device * device)2079 static int de4x5_eisa_remove(struct device *device)
2080 {
2081 struct net_device *dev;
2082 u_long iobase;
2083
2084 dev = dev_get_drvdata(device);
2085 iobase = dev->base_addr;
2086
2087 unregister_netdev (dev);
2088 free_netdev (dev);
2089 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2090 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2091
2092 return 0;
2093 }
2094
2095 static struct eisa_device_id de4x5_eisa_ids[] = {
2096 { "DEC4250", 0 }, /* 0 is the board name index... */
2097 { "" }
2098 };
2099 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2100
2101 static struct eisa_driver de4x5_eisa_driver = {
2102 .id_table = de4x5_eisa_ids,
2103 .driver = {
2104 .name = "de4x5",
2105 .probe = de4x5_eisa_probe,
2106 .remove = de4x5_eisa_remove,
2107 }
2108 };
2109 #endif
2110
2111 #ifdef CONFIG_PCI
2112
2113 /*
2114 ** This function searches the current bus (which is >0) for a DECchip with an
2115 ** SROM, so that in multiport cards that have one SROM shared between multiple
2116 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2117 ** For single port cards this is a time waster...
2118 */
2119 static void
srom_search(struct net_device * dev,struct pci_dev * pdev)2120 srom_search(struct net_device *dev, struct pci_dev *pdev)
2121 {
2122 u_char pb;
2123 u_short vendor, status;
2124 u_int irq = 0, device;
2125 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2126 int i, j;
2127 struct de4x5_private *lp = netdev_priv(dev);
2128 struct pci_dev *this_dev;
2129
2130 list_for_each_entry(this_dev, &pdev->bus->devices, bus_list) {
2131 vendor = this_dev->vendor;
2132 device = this_dev->device << 8;
2133 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2134
2135 /* Get the chip configuration revision register */
2136 pb = this_dev->bus->number;
2137
2138 /* Set the device number information */
2139 lp->device = PCI_SLOT(this_dev->devfn);
2140 lp->bus_num = pb;
2141
2142 /* Set the chipset information */
2143 if (is_DC2114x) {
2144 device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
2145 ? DC21142 : DC21143);
2146 }
2147 lp->chipset = device;
2148
2149 /* Get the board I/O address (64 bits on sparc64) */
2150 iobase = pci_resource_start(this_dev, 0);
2151
2152 /* Fetch the IRQ to be used */
2153 irq = this_dev->irq;
2154 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2155
2156 /* Check if I/O accesses are enabled */
2157 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2158 if (!(status & PCI_COMMAND_IO)) continue;
2159
2160 /* Search for a valid SROM attached to this DECchip */
2161 DevicePresent(dev, DE4X5_APROM);
2162 for (j=0, i=0; i<ETH_ALEN; i++) {
2163 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2164 }
2165 if (j != 0 && j != 6 * 0xff) {
2166 last.chipset = device;
2167 last.bus = pb;
2168 last.irq = irq;
2169 for (i=0; i<ETH_ALEN; i++) {
2170 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2171 }
2172 return;
2173 }
2174 }
2175 }
2176
2177 /*
2178 ** PCI bus I/O device probe
2179 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2180 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2181 ** enabled by the user first in the set up utility. Hence we just check for
2182 ** enabled features and silently ignore the card if they're not.
2183 **
2184 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2185 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2186 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2187 ** PC doesn't conform to the PCI standard)!
2188 **
2189 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2190 ** kernels use the V0.535[n] drivers.
2191 */
2192
de4x5_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2193 static int de4x5_pci_probe(struct pci_dev *pdev,
2194 const struct pci_device_id *ent)
2195 {
2196 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2197 u_short vendor, status;
2198 u_int irq = 0, device;
2199 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2200 int error;
2201 struct net_device *dev;
2202 struct de4x5_private *lp;
2203
2204 dev_num = PCI_SLOT(pdev->devfn);
2205 pb = pdev->bus->number;
2206
2207 if (io) { /* probe a single PCI device */
2208 pbus = (u_short)(io >> 8);
2209 dnum = (u_short)(io & 0xff);
2210 if ((pbus != pb) || (dnum != dev_num))
2211 return -ENODEV;
2212 }
2213
2214 vendor = pdev->vendor;
2215 device = pdev->device << 8;
2216 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2217 return -ENODEV;
2218
2219 /* Ok, the device seems to be for us. */
2220 if ((error = pci_enable_device (pdev)))
2221 return error;
2222
2223 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2224 error = -ENOMEM;
2225 goto disable_dev;
2226 }
2227
2228 lp = netdev_priv(dev);
2229 lp->bus = PCI;
2230 lp->bus_num = 0;
2231
2232 /* Search for an SROM on this bus */
2233 if (lp->bus_num != pb) {
2234 lp->bus_num = pb;
2235 srom_search(dev, pdev);
2236 }
2237
2238 /* Get the chip configuration revision register */
2239 lp->cfrv = pdev->revision;
2240
2241 /* Set the device number information */
2242 lp->device = dev_num;
2243 lp->bus_num = pb;
2244
2245 /* Set the chipset information */
2246 if (is_DC2114x) {
2247 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2248 }
2249 lp->chipset = device;
2250
2251 /* Get the board I/O address (64 bits on sparc64) */
2252 iobase = pci_resource_start(pdev, 0);
2253
2254 /* Fetch the IRQ to be used */
2255 irq = pdev->irq;
2256 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2257 error = -ENODEV;
2258 goto free_dev;
2259 }
2260
2261 /* Check if I/O accesses and Bus Mastering are enabled */
2262 pci_read_config_word(pdev, PCI_COMMAND, &status);
2263 #ifdef __powerpc__
2264 if (!(status & PCI_COMMAND_IO)) {
2265 status |= PCI_COMMAND_IO;
2266 pci_write_config_word(pdev, PCI_COMMAND, status);
2267 pci_read_config_word(pdev, PCI_COMMAND, &status);
2268 }
2269 #endif /* __powerpc__ */
2270 if (!(status & PCI_COMMAND_IO)) {
2271 error = -ENODEV;
2272 goto free_dev;
2273 }
2274
2275 if (!(status & PCI_COMMAND_MASTER)) {
2276 status |= PCI_COMMAND_MASTER;
2277 pci_write_config_word(pdev, PCI_COMMAND, status);
2278 pci_read_config_word(pdev, PCI_COMMAND, &status);
2279 }
2280 if (!(status & PCI_COMMAND_MASTER)) {
2281 error = -ENODEV;
2282 goto free_dev;
2283 }
2284
2285 /* Check the latency timer for values >= 0x60 */
2286 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2287 if (timer < 0x60) {
2288 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2289 }
2290
2291 DevicePresent(dev, DE4X5_APROM);
2292
2293 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2294 error = -EBUSY;
2295 goto free_dev;
2296 }
2297
2298 dev->irq = irq;
2299
2300 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2301 goto release;
2302 }
2303
2304 return 0;
2305
2306 release:
2307 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2308 free_dev:
2309 free_netdev (dev);
2310 disable_dev:
2311 pci_disable_device (pdev);
2312 return error;
2313 }
2314
de4x5_pci_remove(struct pci_dev * pdev)2315 static void de4x5_pci_remove(struct pci_dev *pdev)
2316 {
2317 struct net_device *dev;
2318 u_long iobase;
2319
2320 dev = pci_get_drvdata(pdev);
2321 iobase = dev->base_addr;
2322
2323 unregister_netdev (dev);
2324 free_netdev (dev);
2325 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2326 pci_disable_device (pdev);
2327 }
2328
2329 static const struct pci_device_id de4x5_pci_tbl[] = {
2330 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2331 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2332 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2334 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2336 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2337 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2338 { },
2339 };
2340
2341 static struct pci_driver de4x5_pci_driver = {
2342 .name = "de4x5",
2343 .id_table = de4x5_pci_tbl,
2344 .probe = de4x5_pci_probe,
2345 .remove = de4x5_pci_remove,
2346 };
2347
2348 #endif
2349
2350 /*
2351 ** Auto configure the media here rather than setting the port at compile
2352 ** time. This routine is called by de4x5_init() and when a loss of media is
2353 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2354 ** [TP] or no recent receive activity) to check whether the user has been
2355 ** sneaky and changed the port on us.
2356 */
2357 static int
autoconf_media(struct net_device * dev)2358 autoconf_media(struct net_device *dev)
2359 {
2360 struct de4x5_private *lp = netdev_priv(dev);
2361 u_long iobase = dev->base_addr;
2362
2363 disable_ast(dev);
2364
2365 lp->c_media = AUTO; /* Bogus last media */
2366 inl(DE4X5_MFC); /* Zero the lost frames counter */
2367 lp->media = INIT;
2368 lp->tcount = 0;
2369
2370 de4x5_ast(dev);
2371
2372 return lp->media;
2373 }
2374
2375 /*
2376 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2377 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2378 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2379 ** The only way to test for that is to place a loopback packet onto the
2380 ** network and watch for errors. Since we're messing with the interrupt mask
2381 ** register, disable the board interrupts and do not allow any more packets to
2382 ** be queued to the hardware. Re-enable everything only when the media is
2383 ** found.
2384 ** I may have to "age out" locally queued packets so that the higher layer
2385 ** timeouts don't effectively duplicate packets on the network.
2386 */
2387 static int
dc21040_autoconf(struct net_device * dev)2388 dc21040_autoconf(struct net_device *dev)
2389 {
2390 struct de4x5_private *lp = netdev_priv(dev);
2391 u_long iobase = dev->base_addr;
2392 int next_tick = DE4X5_AUTOSENSE_MS;
2393 s32 imr;
2394
2395 switch (lp->media) {
2396 case INIT:
2397 DISABLE_IRQs;
2398 lp->tx_enable = false;
2399 lp->timeout = -1;
2400 de4x5_save_skbs(dev);
2401 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2402 lp->media = TP;
2403 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2404 lp->media = BNC_AUI;
2405 } else if (lp->autosense == EXT_SIA) {
2406 lp->media = EXT_SIA;
2407 } else {
2408 lp->media = NC;
2409 }
2410 lp->local_state = 0;
2411 next_tick = dc21040_autoconf(dev);
2412 break;
2413
2414 case TP:
2415 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2416 TP_SUSPECT, test_tp);
2417 break;
2418
2419 case TP_SUSPECT:
2420 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2421 break;
2422
2423 case BNC:
2424 case AUI:
2425 case BNC_AUI:
2426 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2427 BNC_AUI_SUSPECT, ping_media);
2428 break;
2429
2430 case BNC_AUI_SUSPECT:
2431 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2432 break;
2433
2434 case EXT_SIA:
2435 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2436 NC, EXT_SIA_SUSPECT, ping_media);
2437 break;
2438
2439 case EXT_SIA_SUSPECT:
2440 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2441 break;
2442
2443 case NC:
2444 /* default to TP for all */
2445 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2446 if (lp->media != lp->c_media) {
2447 de4x5_dbg_media(dev);
2448 lp->c_media = lp->media;
2449 }
2450 lp->media = INIT;
2451 lp->tx_enable = false;
2452 break;
2453 }
2454
2455 return next_tick;
2456 }
2457
2458 static int
dc21040_state(struct net_device * dev,int csr13,int csr14,int csr15,int timeout,int next_state,int suspect_state,int (* fn)(struct net_device *,int))2459 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2460 int next_state, int suspect_state,
2461 int (*fn)(struct net_device *, int))
2462 {
2463 struct de4x5_private *lp = netdev_priv(dev);
2464 int next_tick = DE4X5_AUTOSENSE_MS;
2465 int linkBad;
2466
2467 switch (lp->local_state) {
2468 case 0:
2469 reset_init_sia(dev, csr13, csr14, csr15);
2470 lp->local_state++;
2471 next_tick = 500;
2472 break;
2473
2474 case 1:
2475 if (!lp->tx_enable) {
2476 linkBad = fn(dev, timeout);
2477 if (linkBad < 0) {
2478 next_tick = linkBad & ~TIMER_CB;
2479 } else {
2480 if (linkBad && (lp->autosense == AUTO)) {
2481 lp->local_state = 0;
2482 lp->media = next_state;
2483 } else {
2484 de4x5_init_connection(dev);
2485 }
2486 }
2487 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2488 lp->media = suspect_state;
2489 next_tick = 3000;
2490 }
2491 break;
2492 }
2493
2494 return next_tick;
2495 }
2496
2497 static int
de4x5_suspect_state(struct net_device * dev,int timeout,int prev_state,int (* fn)(struct net_device *,int),int (* asfn)(struct net_device *))2498 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2499 int (*fn)(struct net_device *, int),
2500 int (*asfn)(struct net_device *))
2501 {
2502 struct de4x5_private *lp = netdev_priv(dev);
2503 int next_tick = DE4X5_AUTOSENSE_MS;
2504 int linkBad;
2505
2506 switch (lp->local_state) {
2507 case 1:
2508 if (lp->linkOK) {
2509 lp->media = prev_state;
2510 } else {
2511 lp->local_state++;
2512 next_tick = asfn(dev);
2513 }
2514 break;
2515
2516 case 2:
2517 linkBad = fn(dev, timeout);
2518 if (linkBad < 0) {
2519 next_tick = linkBad & ~TIMER_CB;
2520 } else if (!linkBad) {
2521 lp->local_state--;
2522 lp->media = prev_state;
2523 } else {
2524 lp->media = INIT;
2525 lp->tcount++;
2526 }
2527 }
2528
2529 return next_tick;
2530 }
2531
2532 /*
2533 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2534 ** before BNC, because the BNC port will indicate activity if it's not
2535 ** terminated correctly. The only way to test for that is to place a loopback
2536 ** packet onto the network and watch for errors. Since we're messing with
2537 ** the interrupt mask register, disable the board interrupts and do not allow
2538 ** any more packets to be queued to the hardware. Re-enable everything only
2539 ** when the media is found.
2540 */
2541 static int
dc21041_autoconf(struct net_device * dev)2542 dc21041_autoconf(struct net_device *dev)
2543 {
2544 struct de4x5_private *lp = netdev_priv(dev);
2545 u_long iobase = dev->base_addr;
2546 s32 sts, irqs, irq_mask, imr, omr;
2547 int next_tick = DE4X5_AUTOSENSE_MS;
2548
2549 switch (lp->media) {
2550 case INIT:
2551 DISABLE_IRQs;
2552 lp->tx_enable = false;
2553 lp->timeout = -1;
2554 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2555 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2556 lp->media = TP; /* On chip auto negotiation is broken */
2557 } else if (lp->autosense == TP) {
2558 lp->media = TP;
2559 } else if (lp->autosense == BNC) {
2560 lp->media = BNC;
2561 } else if (lp->autosense == AUI) {
2562 lp->media = AUI;
2563 } else {
2564 lp->media = NC;
2565 }
2566 lp->local_state = 0;
2567 next_tick = dc21041_autoconf(dev);
2568 break;
2569
2570 case TP_NW:
2571 if (lp->timeout < 0) {
2572 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2573 outl(omr | OMR_FDX, DE4X5_OMR);
2574 }
2575 irqs = STS_LNF | STS_LNP;
2576 irq_mask = IMR_LFM | IMR_LPM;
2577 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2578 if (sts < 0) {
2579 next_tick = sts & ~TIMER_CB;
2580 } else {
2581 if (sts & STS_LNP) {
2582 lp->media = ANS;
2583 } else {
2584 lp->media = AUI;
2585 }
2586 next_tick = dc21041_autoconf(dev);
2587 }
2588 break;
2589
2590 case ANS:
2591 if (!lp->tx_enable) {
2592 irqs = STS_LNP;
2593 irq_mask = IMR_LPM;
2594 sts = test_ans(dev, irqs, irq_mask, 3000);
2595 if (sts < 0) {
2596 next_tick = sts & ~TIMER_CB;
2597 } else {
2598 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2599 lp->media = TP;
2600 next_tick = dc21041_autoconf(dev);
2601 } else {
2602 lp->local_state = 1;
2603 de4x5_init_connection(dev);
2604 }
2605 }
2606 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2607 lp->media = ANS_SUSPECT;
2608 next_tick = 3000;
2609 }
2610 break;
2611
2612 case ANS_SUSPECT:
2613 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2614 break;
2615
2616 case TP:
2617 if (!lp->tx_enable) {
2618 if (lp->timeout < 0) {
2619 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2620 outl(omr & ~OMR_FDX, DE4X5_OMR);
2621 }
2622 irqs = STS_LNF | STS_LNP;
2623 irq_mask = IMR_LFM | IMR_LPM;
2624 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2625 if (sts < 0) {
2626 next_tick = sts & ~TIMER_CB;
2627 } else {
2628 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2629 if (inl(DE4X5_SISR) & SISR_NRA) {
2630 lp->media = AUI; /* Non selected port activity */
2631 } else {
2632 lp->media = BNC;
2633 }
2634 next_tick = dc21041_autoconf(dev);
2635 } else {
2636 lp->local_state = 1;
2637 de4x5_init_connection(dev);
2638 }
2639 }
2640 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2641 lp->media = TP_SUSPECT;
2642 next_tick = 3000;
2643 }
2644 break;
2645
2646 case TP_SUSPECT:
2647 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2648 break;
2649
2650 case AUI:
2651 if (!lp->tx_enable) {
2652 if (lp->timeout < 0) {
2653 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2654 outl(omr & ~OMR_FDX, DE4X5_OMR);
2655 }
2656 irqs = 0;
2657 irq_mask = 0;
2658 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2659 if (sts < 0) {
2660 next_tick = sts & ~TIMER_CB;
2661 } else {
2662 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2663 lp->media = BNC;
2664 next_tick = dc21041_autoconf(dev);
2665 } else {
2666 lp->local_state = 1;
2667 de4x5_init_connection(dev);
2668 }
2669 }
2670 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2671 lp->media = AUI_SUSPECT;
2672 next_tick = 3000;
2673 }
2674 break;
2675
2676 case AUI_SUSPECT:
2677 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2678 break;
2679
2680 case BNC:
2681 switch (lp->local_state) {
2682 case 0:
2683 if (lp->timeout < 0) {
2684 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2685 outl(omr & ~OMR_FDX, DE4X5_OMR);
2686 }
2687 irqs = 0;
2688 irq_mask = 0;
2689 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2690 if (sts < 0) {
2691 next_tick = sts & ~TIMER_CB;
2692 } else {
2693 lp->local_state++; /* Ensure media connected */
2694 next_tick = dc21041_autoconf(dev);
2695 }
2696 break;
2697
2698 case 1:
2699 if (!lp->tx_enable) {
2700 if ((sts = ping_media(dev, 3000)) < 0) {
2701 next_tick = sts & ~TIMER_CB;
2702 } else {
2703 if (sts) {
2704 lp->local_state = 0;
2705 lp->media = NC;
2706 } else {
2707 de4x5_init_connection(dev);
2708 }
2709 }
2710 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2711 lp->media = BNC_SUSPECT;
2712 next_tick = 3000;
2713 }
2714 break;
2715 }
2716 break;
2717
2718 case BNC_SUSPECT:
2719 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2720 break;
2721
2722 case NC:
2723 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2724 outl(omr | OMR_FDX, DE4X5_OMR);
2725 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2726 if (lp->media != lp->c_media) {
2727 de4x5_dbg_media(dev);
2728 lp->c_media = lp->media;
2729 }
2730 lp->media = INIT;
2731 lp->tx_enable = false;
2732 break;
2733 }
2734
2735 return next_tick;
2736 }
2737
2738 /*
2739 ** Some autonegotiation chips are broken in that they do not return the
2740 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2741 ** register, except at the first power up negotiation.
2742 */
2743 static int
dc21140m_autoconf(struct net_device * dev)2744 dc21140m_autoconf(struct net_device *dev)
2745 {
2746 struct de4x5_private *lp = netdev_priv(dev);
2747 int ana, anlpa, cap, cr, slnk, sr;
2748 int next_tick = DE4X5_AUTOSENSE_MS;
2749 u_long imr, omr, iobase = dev->base_addr;
2750
2751 switch(lp->media) {
2752 case INIT:
2753 if (lp->timeout < 0) {
2754 DISABLE_IRQs;
2755 lp->tx_enable = false;
2756 lp->linkOK = 0;
2757 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2758 }
2759 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2760 next_tick &= ~TIMER_CB;
2761 } else {
2762 if (lp->useSROM) {
2763 if (srom_map_media(dev) < 0) {
2764 lp->tcount++;
2765 return next_tick;
2766 }
2767 srom_exec(dev, lp->phy[lp->active].gep);
2768 if (lp->infoblock_media == ANS) {
2769 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2770 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2771 }
2772 } else {
2773 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2774 SET_10Mb;
2775 if (lp->autosense == _100Mb) {
2776 lp->media = _100Mb;
2777 } else if (lp->autosense == _10Mb) {
2778 lp->media = _10Mb;
2779 } else if ((lp->autosense == AUTO) &&
2780 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2781 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2782 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2783 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2784 lp->media = ANS;
2785 } else if (lp->autosense == AUTO) {
2786 lp->media = SPD_DET;
2787 } else if (is_spd_100(dev) && is_100_up(dev)) {
2788 lp->media = _100Mb;
2789 } else {
2790 lp->media = NC;
2791 }
2792 }
2793 lp->local_state = 0;
2794 next_tick = dc21140m_autoconf(dev);
2795 }
2796 break;
2797
2798 case ANS:
2799 switch (lp->local_state) {
2800 case 0:
2801 if (lp->timeout < 0) {
2802 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2803 }
2804 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2805 if (cr < 0) {
2806 next_tick = cr & ~TIMER_CB;
2807 } else {
2808 if (cr) {
2809 lp->local_state = 0;
2810 lp->media = SPD_DET;
2811 } else {
2812 lp->local_state++;
2813 }
2814 next_tick = dc21140m_autoconf(dev);
2815 }
2816 break;
2817
2818 case 1:
2819 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) {
2820 next_tick = sr & ~TIMER_CB;
2821 } else {
2822 lp->media = SPD_DET;
2823 lp->local_state = 0;
2824 if (sr) { /* Success! */
2825 lp->tmp = MII_SR_ASSC;
2826 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2827 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2828 if (!(anlpa & MII_ANLPA_RF) &&
2829 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2830 if (cap & MII_ANA_100M) {
2831 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2832 lp->media = _100Mb;
2833 } else if (cap & MII_ANA_10M) {
2834 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2835
2836 lp->media = _10Mb;
2837 }
2838 }
2839 } /* Auto Negotiation failed to finish */
2840 next_tick = dc21140m_autoconf(dev);
2841 } /* Auto Negotiation failed to start */
2842 break;
2843 }
2844 break;
2845
2846 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2847 if (lp->timeout < 0) {
2848 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2849 (~gep_rd(dev) & GEP_LNP));
2850 SET_100Mb_PDET;
2851 }
2852 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2853 next_tick = slnk & ~TIMER_CB;
2854 } else {
2855 if (is_spd_100(dev) && is_100_up(dev)) {
2856 lp->media = _100Mb;
2857 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2858 lp->media = _10Mb;
2859 } else {
2860 lp->media = NC;
2861 }
2862 next_tick = dc21140m_autoconf(dev);
2863 }
2864 break;
2865
2866 case _100Mb: /* Set 100Mb/s */
2867 next_tick = 3000;
2868 if (!lp->tx_enable) {
2869 SET_100Mb;
2870 de4x5_init_connection(dev);
2871 } else {
2872 if (!lp->linkOK && (lp->autosense == AUTO)) {
2873 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2874 lp->media = INIT;
2875 lp->tcount++;
2876 next_tick = DE4X5_AUTOSENSE_MS;
2877 }
2878 }
2879 }
2880 break;
2881
2882 case BNC:
2883 case AUI:
2884 case _10Mb: /* Set 10Mb/s */
2885 next_tick = 3000;
2886 if (!lp->tx_enable) {
2887 SET_10Mb;
2888 de4x5_init_connection(dev);
2889 } else {
2890 if (!lp->linkOK && (lp->autosense == AUTO)) {
2891 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2892 lp->media = INIT;
2893 lp->tcount++;
2894 next_tick = DE4X5_AUTOSENSE_MS;
2895 }
2896 }
2897 }
2898 break;
2899
2900 case NC:
2901 if (lp->media != lp->c_media) {
2902 de4x5_dbg_media(dev);
2903 lp->c_media = lp->media;
2904 }
2905 lp->media = INIT;
2906 lp->tx_enable = false;
2907 break;
2908 }
2909
2910 return next_tick;
2911 }
2912
2913 /*
2914 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2915 ** changing how I figure out the media - but trying to keep it backwards
2916 ** compatible with the de500-xa and de500-aa.
2917 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2918 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2919 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2920 ** active.
2921 ** When autonegotiation is working, the ANS part searches the SROM for
2922 ** the highest common speed (TP) link that both can run and if that can
2923 ** be full duplex. That infoblock is executed and then the link speed set.
2924 **
2925 ** Only _10Mb and _100Mb are tested here.
2926 */
2927 static int
dc2114x_autoconf(struct net_device * dev)2928 dc2114x_autoconf(struct net_device *dev)
2929 {
2930 struct de4x5_private *lp = netdev_priv(dev);
2931 u_long iobase = dev->base_addr;
2932 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2933 int next_tick = DE4X5_AUTOSENSE_MS;
2934
2935 switch (lp->media) {
2936 case INIT:
2937 if (lp->timeout < 0) {
2938 DISABLE_IRQs;
2939 lp->tx_enable = false;
2940 lp->linkOK = 0;
2941 lp->timeout = -1;
2942 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2943 if (lp->params.autosense & ~AUTO) {
2944 srom_map_media(dev); /* Fixed media requested */
2945 if (lp->media != lp->params.autosense) {
2946 lp->tcount++;
2947 lp->media = INIT;
2948 return next_tick;
2949 }
2950 lp->media = INIT;
2951 }
2952 }
2953 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2954 next_tick &= ~TIMER_CB;
2955 } else {
2956 if (lp->autosense == _100Mb) {
2957 lp->media = _100Mb;
2958 } else if (lp->autosense == _10Mb) {
2959 lp->media = _10Mb;
2960 } else if (lp->autosense == TP) {
2961 lp->media = TP;
2962 } else if (lp->autosense == BNC) {
2963 lp->media = BNC;
2964 } else if (lp->autosense == AUI) {
2965 lp->media = AUI;
2966 } else {
2967 lp->media = SPD_DET;
2968 if ((lp->infoblock_media == ANS) &&
2969 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2970 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2971 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2972 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2973 lp->media = ANS;
2974 }
2975 }
2976 lp->local_state = 0;
2977 next_tick = dc2114x_autoconf(dev);
2978 }
2979 break;
2980
2981 case ANS:
2982 switch (lp->local_state) {
2983 case 0:
2984 if (lp->timeout < 0) {
2985 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2986 }
2987 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2988 if (cr < 0) {
2989 next_tick = cr & ~TIMER_CB;
2990 } else {
2991 if (cr) {
2992 lp->local_state = 0;
2993 lp->media = SPD_DET;
2994 } else {
2995 lp->local_state++;
2996 }
2997 next_tick = dc2114x_autoconf(dev);
2998 }
2999 break;
3000
3001 case 1:
3002 sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000);
3003 if (sr < 0) {
3004 next_tick = sr & ~TIMER_CB;
3005 } else {
3006 lp->media = SPD_DET;
3007 lp->local_state = 0;
3008 if (sr) { /* Success! */
3009 lp->tmp = MII_SR_ASSC;
3010 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3011 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3012 if (!(anlpa & MII_ANLPA_RF) &&
3013 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3014 if (cap & MII_ANA_100M) {
3015 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3016 lp->media = _100Mb;
3017 } else if (cap & MII_ANA_10M) {
3018 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3019 lp->media = _10Mb;
3020 }
3021 }
3022 } /* Auto Negotiation failed to finish */
3023 next_tick = dc2114x_autoconf(dev);
3024 } /* Auto Negotiation failed to start */
3025 break;
3026 }
3027 break;
3028
3029 case AUI:
3030 if (!lp->tx_enable) {
3031 if (lp->timeout < 0) {
3032 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3033 outl(omr & ~OMR_FDX, DE4X5_OMR);
3034 }
3035 irqs = 0;
3036 irq_mask = 0;
3037 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3038 if (sts < 0) {
3039 next_tick = sts & ~TIMER_CB;
3040 } else {
3041 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3042 lp->media = BNC;
3043 next_tick = dc2114x_autoconf(dev);
3044 } else {
3045 lp->local_state = 1;
3046 de4x5_init_connection(dev);
3047 }
3048 }
3049 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3050 lp->media = AUI_SUSPECT;
3051 next_tick = 3000;
3052 }
3053 break;
3054
3055 case AUI_SUSPECT:
3056 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3057 break;
3058
3059 case BNC:
3060 switch (lp->local_state) {
3061 case 0:
3062 if (lp->timeout < 0) {
3063 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3064 outl(omr & ~OMR_FDX, DE4X5_OMR);
3065 }
3066 irqs = 0;
3067 irq_mask = 0;
3068 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3069 if (sts < 0) {
3070 next_tick = sts & ~TIMER_CB;
3071 } else {
3072 lp->local_state++; /* Ensure media connected */
3073 next_tick = dc2114x_autoconf(dev);
3074 }
3075 break;
3076
3077 case 1:
3078 if (!lp->tx_enable) {
3079 if ((sts = ping_media(dev, 3000)) < 0) {
3080 next_tick = sts & ~TIMER_CB;
3081 } else {
3082 if (sts) {
3083 lp->local_state = 0;
3084 lp->tcount++;
3085 lp->media = INIT;
3086 } else {
3087 de4x5_init_connection(dev);
3088 }
3089 }
3090 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3091 lp->media = BNC_SUSPECT;
3092 next_tick = 3000;
3093 }
3094 break;
3095 }
3096 break;
3097
3098 case BNC_SUSPECT:
3099 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3100 break;
3101
3102 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3103 if (srom_map_media(dev) < 0) {
3104 lp->tcount++;
3105 lp->media = INIT;
3106 return next_tick;
3107 }
3108 if (lp->media == _100Mb) {
3109 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3110 lp->media = SPD_DET;
3111 return slnk & ~TIMER_CB;
3112 }
3113 } else {
3114 if (wait_for_link(dev) < 0) {
3115 lp->media = SPD_DET;
3116 return PDET_LINK_WAIT;
3117 }
3118 }
3119 if (lp->media == ANS) { /* Do MII parallel detection */
3120 if (is_spd_100(dev)) {
3121 lp->media = _100Mb;
3122 } else {
3123 lp->media = _10Mb;
3124 }
3125 next_tick = dc2114x_autoconf(dev);
3126 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3127 (((lp->media == _10Mb) || (lp->media == TP) ||
3128 (lp->media == BNC) || (lp->media == AUI)) &&
3129 is_10_up(dev))) {
3130 next_tick = dc2114x_autoconf(dev);
3131 } else {
3132 lp->tcount++;
3133 lp->media = INIT;
3134 }
3135 break;
3136
3137 case _10Mb:
3138 next_tick = 3000;
3139 if (!lp->tx_enable) {
3140 SET_10Mb;
3141 de4x5_init_connection(dev);
3142 } else {
3143 if (!lp->linkOK && (lp->autosense == AUTO)) {
3144 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3145 lp->media = INIT;
3146 lp->tcount++;
3147 next_tick = DE4X5_AUTOSENSE_MS;
3148 }
3149 }
3150 }
3151 break;
3152
3153 case _100Mb:
3154 next_tick = 3000;
3155 if (!lp->tx_enable) {
3156 SET_100Mb;
3157 de4x5_init_connection(dev);
3158 } else {
3159 if (!lp->linkOK && (lp->autosense == AUTO)) {
3160 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3161 lp->media = INIT;
3162 lp->tcount++;
3163 next_tick = DE4X5_AUTOSENSE_MS;
3164 }
3165 }
3166 }
3167 break;
3168
3169 default:
3170 lp->tcount++;
3171 printk("Huh?: media:%02x\n", lp->media);
3172 lp->media = INIT;
3173 break;
3174 }
3175
3176 return next_tick;
3177 }
3178
3179 static int
srom_autoconf(struct net_device * dev)3180 srom_autoconf(struct net_device *dev)
3181 {
3182 struct de4x5_private *lp = netdev_priv(dev);
3183
3184 return lp->infoleaf_fn(dev);
3185 }
3186
3187 /*
3188 ** This mapping keeps the original media codes and FDX flag unchanged.
3189 ** While it isn't strictly necessary, it helps me for the moment...
3190 ** The early return avoids a media state / SROM media space clash.
3191 */
3192 static int
srom_map_media(struct net_device * dev)3193 srom_map_media(struct net_device *dev)
3194 {
3195 struct de4x5_private *lp = netdev_priv(dev);
3196
3197 lp->fdx = false;
3198 if (lp->infoblock_media == lp->media)
3199 return 0;
3200
3201 switch(lp->infoblock_media) {
3202 case SROM_10BASETF:
3203 if (!lp->params.fdx) return -1;
3204 lp->fdx = true;
3205 case SROM_10BASET:
3206 if (lp->params.fdx && !lp->fdx) return -1;
3207 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3208 lp->media = _10Mb;
3209 } else {
3210 lp->media = TP;
3211 }
3212 break;
3213
3214 case SROM_10BASE2:
3215 lp->media = BNC;
3216 break;
3217
3218 case SROM_10BASE5:
3219 lp->media = AUI;
3220 break;
3221
3222 case SROM_100BASETF:
3223 if (!lp->params.fdx) return -1;
3224 lp->fdx = true;
3225 case SROM_100BASET:
3226 if (lp->params.fdx && !lp->fdx) return -1;
3227 lp->media = _100Mb;
3228 break;
3229
3230 case SROM_100BASET4:
3231 lp->media = _100Mb;
3232 break;
3233
3234 case SROM_100BASEFF:
3235 if (!lp->params.fdx) return -1;
3236 lp->fdx = true;
3237 case SROM_100BASEF:
3238 if (lp->params.fdx && !lp->fdx) return -1;
3239 lp->media = _100Mb;
3240 break;
3241
3242 case ANS:
3243 lp->media = ANS;
3244 lp->fdx = lp->params.fdx;
3245 break;
3246
3247 default:
3248 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3249 lp->infoblock_media);
3250 return -1;
3251 }
3252
3253 return 0;
3254 }
3255
3256 static void
de4x5_init_connection(struct net_device * dev)3257 de4x5_init_connection(struct net_device *dev)
3258 {
3259 struct de4x5_private *lp = netdev_priv(dev);
3260 u_long iobase = dev->base_addr;
3261 u_long flags = 0;
3262
3263 if (lp->media != lp->c_media) {
3264 de4x5_dbg_media(dev);
3265 lp->c_media = lp->media; /* Stop scrolling media messages */
3266 }
3267
3268 spin_lock_irqsave(&lp->lock, flags);
3269 de4x5_rst_desc_ring(dev);
3270 de4x5_setup_intr(dev);
3271 lp->tx_enable = true;
3272 spin_unlock_irqrestore(&lp->lock, flags);
3273 outl(POLL_DEMAND, DE4X5_TPD);
3274
3275 netif_wake_queue(dev);
3276 }
3277
3278 /*
3279 ** General PHY reset function. Some MII devices don't reset correctly
3280 ** since their MII address pins can float at voltages that are dependent
3281 ** on the signal pin use. Do a double reset to ensure a reset.
3282 */
3283 static int
de4x5_reset_phy(struct net_device * dev)3284 de4x5_reset_phy(struct net_device *dev)
3285 {
3286 struct de4x5_private *lp = netdev_priv(dev);
3287 u_long iobase = dev->base_addr;
3288 int next_tick = 0;
3289
3290 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3291 if (lp->timeout < 0) {
3292 if (lp->useSROM) {
3293 if (lp->phy[lp->active].rst) {
3294 srom_exec(dev, lp->phy[lp->active].rst);
3295 srom_exec(dev, lp->phy[lp->active].rst);
3296 } else if (lp->rst) { /* Type 5 infoblock reset */
3297 srom_exec(dev, lp->rst);
3298 srom_exec(dev, lp->rst);
3299 }
3300 } else {
3301 PHY_HARD_RESET;
3302 }
3303 if (lp->useMII) {
3304 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3305 }
3306 }
3307 if (lp->useMII) {
3308 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500);
3309 }
3310 } else if (lp->chipset == DC21140) {
3311 PHY_HARD_RESET;
3312 }
3313
3314 return next_tick;
3315 }
3316
3317 static int
test_media(struct net_device * dev,s32 irqs,s32 irq_mask,s32 csr13,s32 csr14,s32 csr15,s32 msec)3318 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3319 {
3320 struct de4x5_private *lp = netdev_priv(dev);
3321 u_long iobase = dev->base_addr;
3322 s32 sts, csr12;
3323
3324 if (lp->timeout < 0) {
3325 lp->timeout = msec/100;
3326 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3327 reset_init_sia(dev, csr13, csr14, csr15);
3328 }
3329
3330 /* set up the interrupt mask */
3331 outl(irq_mask, DE4X5_IMR);
3332
3333 /* clear all pending interrupts */
3334 sts = inl(DE4X5_STS);
3335 outl(sts, DE4X5_STS);
3336
3337 /* clear csr12 NRA and SRA bits */
3338 if ((lp->chipset == DC21041) || lp->useSROM) {
3339 csr12 = inl(DE4X5_SISR);
3340 outl(csr12, DE4X5_SISR);
3341 }
3342 }
3343
3344 sts = inl(DE4X5_STS) & ~TIMER_CB;
3345
3346 if (!(sts & irqs) && --lp->timeout) {
3347 sts = 100 | TIMER_CB;
3348 } else {
3349 lp->timeout = -1;
3350 }
3351
3352 return sts;
3353 }
3354
3355 static int
test_tp(struct net_device * dev,s32 msec)3356 test_tp(struct net_device *dev, s32 msec)
3357 {
3358 struct de4x5_private *lp = netdev_priv(dev);
3359 u_long iobase = dev->base_addr;
3360 int sisr;
3361
3362 if (lp->timeout < 0) {
3363 lp->timeout = msec/100;
3364 }
3365
3366 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3367
3368 if (sisr && --lp->timeout) {
3369 sisr = 100 | TIMER_CB;
3370 } else {
3371 lp->timeout = -1;
3372 }
3373
3374 return sisr;
3375 }
3376
3377 /*
3378 ** Samples the 100Mb Link State Signal. The sample interval is important
3379 ** because too fast a rate can give erroneous results and confuse the
3380 ** speed sense algorithm.
3381 */
3382 #define SAMPLE_INTERVAL 500 /* ms */
3383 #define SAMPLE_DELAY 2000 /* ms */
3384 static int
test_for_100Mb(struct net_device * dev,int msec)3385 test_for_100Mb(struct net_device *dev, int msec)
3386 {
3387 struct de4x5_private *lp = netdev_priv(dev);
3388 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3389
3390 if (lp->timeout < 0) {
3391 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3392 if (msec > SAMPLE_DELAY) {
3393 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3394 gep = SAMPLE_DELAY | TIMER_CB;
3395 return gep;
3396 } else {
3397 lp->timeout = msec/SAMPLE_INTERVAL;
3398 }
3399 }
3400
3401 if (lp->phy[lp->active].id || lp->useSROM) {
3402 gep = is_100_up(dev) | is_spd_100(dev);
3403 } else {
3404 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3405 }
3406 if (!(gep & ret) && --lp->timeout) {
3407 gep = SAMPLE_INTERVAL | TIMER_CB;
3408 } else {
3409 lp->timeout = -1;
3410 }
3411
3412 return gep;
3413 }
3414
3415 static int
wait_for_link(struct net_device * dev)3416 wait_for_link(struct net_device *dev)
3417 {
3418 struct de4x5_private *lp = netdev_priv(dev);
3419
3420 if (lp->timeout < 0) {
3421 lp->timeout = 1;
3422 }
3423
3424 if (lp->timeout--) {
3425 return TIMER_CB;
3426 } else {
3427 lp->timeout = -1;
3428 }
3429
3430 return 0;
3431 }
3432
3433 /*
3434 **
3435 **
3436 */
3437 static int
test_mii_reg(struct net_device * dev,int reg,int mask,bool pol,long msec)3438 test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec)
3439 {
3440 struct de4x5_private *lp = netdev_priv(dev);
3441 int test;
3442 u_long iobase = dev->base_addr;
3443
3444 if (lp->timeout < 0) {
3445 lp->timeout = msec/100;
3446 }
3447
3448 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3449 test = (reg ^ (pol ? ~0 : 0)) & mask;
3450
3451 if (test && --lp->timeout) {
3452 reg = 100 | TIMER_CB;
3453 } else {
3454 lp->timeout = -1;
3455 }
3456
3457 return reg;
3458 }
3459
3460 static int
is_spd_100(struct net_device * dev)3461 is_spd_100(struct net_device *dev)
3462 {
3463 struct de4x5_private *lp = netdev_priv(dev);
3464 u_long iobase = dev->base_addr;
3465 int spd;
3466
3467 if (lp->useMII) {
3468 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3469 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3470 spd &= lp->phy[lp->active].spd.mask;
3471 } else if (!lp->useSROM) { /* de500-xa */
3472 spd = ((~gep_rd(dev)) & GEP_SLNK);
3473 } else {
3474 if ((lp->ibn == 2) || !lp->asBitValid)
3475 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3476
3477 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3478 (lp->linkOK & ~lp->asBitValid);
3479 }
3480
3481 return spd;
3482 }
3483
3484 static int
is_100_up(struct net_device * dev)3485 is_100_up(struct net_device *dev)
3486 {
3487 struct de4x5_private *lp = netdev_priv(dev);
3488 u_long iobase = dev->base_addr;
3489
3490 if (lp->useMII) {
3491 /* Double read for sticky bits & temporary drops */
3492 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3493 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3494 } else if (!lp->useSROM) { /* de500-xa */
3495 return (~gep_rd(dev)) & GEP_SLNK;
3496 } else {
3497 if ((lp->ibn == 2) || !lp->asBitValid)
3498 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3499
3500 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3501 (lp->linkOK & ~lp->asBitValid);
3502 }
3503 }
3504
3505 static int
is_10_up(struct net_device * dev)3506 is_10_up(struct net_device *dev)
3507 {
3508 struct de4x5_private *lp = netdev_priv(dev);
3509 u_long iobase = dev->base_addr;
3510
3511 if (lp->useMII) {
3512 /* Double read for sticky bits & temporary drops */
3513 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3514 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3515 } else if (!lp->useSROM) { /* de500-xa */
3516 return (~gep_rd(dev)) & GEP_LNP;
3517 } else {
3518 if ((lp->ibn == 2) || !lp->asBitValid)
3519 return ((lp->chipset & ~0x00ff) == DC2114x) ?
3520 (~inl(DE4X5_SISR)&SISR_LS10):
3521 0;
3522
3523 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3524 (lp->linkOK & ~lp->asBitValid);
3525 }
3526 }
3527
3528 static int
is_anc_capable(struct net_device * dev)3529 is_anc_capable(struct net_device *dev)
3530 {
3531 struct de4x5_private *lp = netdev_priv(dev);
3532 u_long iobase = dev->base_addr;
3533
3534 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3535 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3536 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3537 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3538 } else {
3539 return 0;
3540 }
3541 }
3542
3543 /*
3544 ** Send a packet onto the media and watch for send errors that indicate the
3545 ** media is bad or unconnected.
3546 */
3547 static int
ping_media(struct net_device * dev,int msec)3548 ping_media(struct net_device *dev, int msec)
3549 {
3550 struct de4x5_private *lp = netdev_priv(dev);
3551 u_long iobase = dev->base_addr;
3552 int sisr;
3553
3554 if (lp->timeout < 0) {
3555 lp->timeout = msec/100;
3556
3557 lp->tmp = lp->tx_new; /* Remember the ring position */
3558 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3559 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
3560 outl(POLL_DEMAND, DE4X5_TPD);
3561 }
3562
3563 sisr = inl(DE4X5_SISR);
3564
3565 if ((!(sisr & SISR_NCR)) &&
3566 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3567 (--lp->timeout)) {
3568 sisr = 100 | TIMER_CB;
3569 } else {
3570 if ((!(sisr & SISR_NCR)) &&
3571 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3572 lp->timeout) {
3573 sisr = 0;
3574 } else {
3575 sisr = 1;
3576 }
3577 lp->timeout = -1;
3578 }
3579
3580 return sisr;
3581 }
3582
3583 /*
3584 ** This function does 2 things: on Intels it kmalloc's another buffer to
3585 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3586 ** into which the packet is copied.
3587 */
3588 static struct sk_buff *
de4x5_alloc_rx_buff(struct net_device * dev,int index,int len)3589 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3590 {
3591 struct de4x5_private *lp = netdev_priv(dev);
3592 struct sk_buff *p;
3593
3594 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
3595 struct sk_buff *ret;
3596 u_long i=0, tmp;
3597
3598 p = netdev_alloc_skb(dev, IEEE802_3_SZ + DE4X5_ALIGN + 2);
3599 if (!p) return NULL;
3600
3601 tmp = virt_to_bus(p->data);
3602 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3603 skb_reserve(p, i);
3604 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3605
3606 ret = lp->rx_skb[index];
3607 lp->rx_skb[index] = p;
3608
3609 if ((u_long) ret > 1) {
3610 skb_put(ret, len);
3611 }
3612
3613 return ret;
3614
3615 #else
3616 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3617
3618 p = netdev_alloc_skb(dev, len + 2);
3619 if (!p) return NULL;
3620
3621 skb_reserve(p, 2); /* Align */
3622 if (index < lp->rx_old) { /* Wrapped buffer */
3623 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3624 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3625 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3626 } else { /* Linear buffer */
3627 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3628 }
3629
3630 return p;
3631 #endif
3632 }
3633
3634 static void
de4x5_free_rx_buffs(struct net_device * dev)3635 de4x5_free_rx_buffs(struct net_device *dev)
3636 {
3637 struct de4x5_private *lp = netdev_priv(dev);
3638 int i;
3639
3640 for (i=0; i<lp->rxRingSize; i++) {
3641 if ((u_long) lp->rx_skb[i] > 1) {
3642 dev_kfree_skb(lp->rx_skb[i]);
3643 }
3644 lp->rx_ring[i].status = 0;
3645 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3646 }
3647 }
3648
3649 static void
de4x5_free_tx_buffs(struct net_device * dev)3650 de4x5_free_tx_buffs(struct net_device *dev)
3651 {
3652 struct de4x5_private *lp = netdev_priv(dev);
3653 int i;
3654
3655 for (i=0; i<lp->txRingSize; i++) {
3656 if (lp->tx_skb[i])
3657 de4x5_free_tx_buff(lp, i);
3658 lp->tx_ring[i].status = 0;
3659 }
3660
3661 /* Unload the locally queued packets */
3662 __skb_queue_purge(&lp->cache.queue);
3663 }
3664
3665 /*
3666 ** When a user pulls a connection, the DECchip can end up in a
3667 ** 'running - waiting for end of transmission' state. This means that we
3668 ** have to perform a chip soft reset to ensure that we can synchronize
3669 ** the hardware and software and make any media probes using a loopback
3670 ** packet meaningful.
3671 */
3672 static void
de4x5_save_skbs(struct net_device * dev)3673 de4x5_save_skbs(struct net_device *dev)
3674 {
3675 struct de4x5_private *lp = netdev_priv(dev);
3676 u_long iobase = dev->base_addr;
3677 s32 omr;
3678
3679 if (!lp->cache.save_cnt) {
3680 STOP_DE4X5;
3681 de4x5_tx(dev); /* Flush any sent skb's */
3682 de4x5_free_tx_buffs(dev);
3683 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3684 de4x5_sw_reset(dev);
3685 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3686 lp->cache.save_cnt++;
3687 START_DE4X5;
3688 }
3689 }
3690
3691 static void
de4x5_rst_desc_ring(struct net_device * dev)3692 de4x5_rst_desc_ring(struct net_device *dev)
3693 {
3694 struct de4x5_private *lp = netdev_priv(dev);
3695 u_long iobase = dev->base_addr;
3696 int i;
3697 s32 omr;
3698
3699 if (lp->cache.save_cnt) {
3700 STOP_DE4X5;
3701 outl(lp->dma_rings, DE4X5_RRBA);
3702 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3703 DE4X5_TRBA);
3704
3705 lp->rx_new = lp->rx_old = 0;
3706 lp->tx_new = lp->tx_old = 0;
3707
3708 for (i = 0; i < lp->rxRingSize; i++) {
3709 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3710 }
3711
3712 for (i = 0; i < lp->txRingSize; i++) {
3713 lp->tx_ring[i].status = cpu_to_le32(0);
3714 }
3715
3716 barrier();
3717 lp->cache.save_cnt--;
3718 START_DE4X5;
3719 }
3720 }
3721
3722 static void
de4x5_cache_state(struct net_device * dev,int flag)3723 de4x5_cache_state(struct net_device *dev, int flag)
3724 {
3725 struct de4x5_private *lp = netdev_priv(dev);
3726 u_long iobase = dev->base_addr;
3727
3728 switch(flag) {
3729 case DE4X5_SAVE_STATE:
3730 lp->cache.csr0 = inl(DE4X5_BMR);
3731 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3732 lp->cache.csr7 = inl(DE4X5_IMR);
3733 break;
3734
3735 case DE4X5_RESTORE_STATE:
3736 outl(lp->cache.csr0, DE4X5_BMR);
3737 outl(lp->cache.csr6, DE4X5_OMR);
3738 outl(lp->cache.csr7, DE4X5_IMR);
3739 if (lp->chipset == DC21140) {
3740 gep_wr(lp->cache.gepc, dev);
3741 gep_wr(lp->cache.gep, dev);
3742 } else {
3743 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3744 lp->cache.csr15);
3745 }
3746 break;
3747 }
3748 }
3749
3750 static void
de4x5_put_cache(struct net_device * dev,struct sk_buff * skb)3751 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3752 {
3753 struct de4x5_private *lp = netdev_priv(dev);
3754
3755 __skb_queue_tail(&lp->cache.queue, skb);
3756 }
3757
3758 static void
de4x5_putb_cache(struct net_device * dev,struct sk_buff * skb)3759 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3760 {
3761 struct de4x5_private *lp = netdev_priv(dev);
3762
3763 __skb_queue_head(&lp->cache.queue, skb);
3764 }
3765
3766 static struct sk_buff *
de4x5_get_cache(struct net_device * dev)3767 de4x5_get_cache(struct net_device *dev)
3768 {
3769 struct de4x5_private *lp = netdev_priv(dev);
3770
3771 return __skb_dequeue(&lp->cache.queue);
3772 }
3773
3774 /*
3775 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3776 ** is received and the auto-negotiation status is NWAY OK.
3777 */
3778 static int
test_ans(struct net_device * dev,s32 irqs,s32 irq_mask,s32 msec)3779 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3780 {
3781 struct de4x5_private *lp = netdev_priv(dev);
3782 u_long iobase = dev->base_addr;
3783 s32 sts, ans;
3784
3785 if (lp->timeout < 0) {
3786 lp->timeout = msec/100;
3787 outl(irq_mask, DE4X5_IMR);
3788
3789 /* clear all pending interrupts */
3790 sts = inl(DE4X5_STS);
3791 outl(sts, DE4X5_STS);
3792 }
3793
3794 ans = inl(DE4X5_SISR) & SISR_ANS;
3795 sts = inl(DE4X5_STS) & ~TIMER_CB;
3796
3797 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3798 sts = 100 | TIMER_CB;
3799 } else {
3800 lp->timeout = -1;
3801 }
3802
3803 return sts;
3804 }
3805
3806 static void
de4x5_setup_intr(struct net_device * dev)3807 de4x5_setup_intr(struct net_device *dev)
3808 {
3809 struct de4x5_private *lp = netdev_priv(dev);
3810 u_long iobase = dev->base_addr;
3811 s32 imr, sts;
3812
3813 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3814 imr = 0;
3815 UNMASK_IRQs;
3816 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3817 outl(sts, DE4X5_STS);
3818 ENABLE_IRQs;
3819 }
3820 }
3821
3822 /*
3823 **
3824 */
3825 static void
reset_init_sia(struct net_device * dev,s32 csr13,s32 csr14,s32 csr15)3826 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3827 {
3828 struct de4x5_private *lp = netdev_priv(dev);
3829 u_long iobase = dev->base_addr;
3830
3831 RESET_SIA;
3832 if (lp->useSROM) {
3833 if (lp->ibn == 3) {
3834 srom_exec(dev, lp->phy[lp->active].rst);
3835 srom_exec(dev, lp->phy[lp->active].gep);
3836 outl(1, DE4X5_SICR);
3837 return;
3838 } else {
3839 csr15 = lp->cache.csr15;
3840 csr14 = lp->cache.csr14;
3841 csr13 = lp->cache.csr13;
3842 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3843 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3844 }
3845 } else {
3846 outl(csr15, DE4X5_SIGR);
3847 }
3848 outl(csr14, DE4X5_STRR);
3849 outl(csr13, DE4X5_SICR);
3850
3851 mdelay(10);
3852 }
3853
3854 /*
3855 ** Create a loopback ethernet packet
3856 */
3857 static void
create_packet(struct net_device * dev,char * frame,int len)3858 create_packet(struct net_device *dev, char *frame, int len)
3859 {
3860 int i;
3861 char *buf = frame;
3862
3863 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3864 *buf++ = dev->dev_addr[i];
3865 }
3866 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3867 *buf++ = dev->dev_addr[i];
3868 }
3869
3870 *buf++ = 0; /* Packet length (2 bytes) */
3871 *buf++ = 1;
3872 }
3873
3874 /*
3875 ** Look for a particular board name in the EISA configuration space
3876 */
3877 static int
EISA_signature(char * name,struct device * device)3878 EISA_signature(char *name, struct device *device)
3879 {
3880 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3881 struct eisa_device *edev;
3882
3883 *name = '\0';
3884 edev = to_eisa_device (device);
3885 i = edev->id.driver_data;
3886
3887 if (i >= 0 && i < siglen) {
3888 strcpy (name, de4x5_signatures[i]);
3889 status = 1;
3890 }
3891
3892 return status; /* return the device name string */
3893 }
3894
3895 /*
3896 ** Look for a particular board name in the PCI configuration space
3897 */
3898 static int
PCI_signature(char * name,struct de4x5_private * lp)3899 PCI_signature(char *name, struct de4x5_private *lp)
3900 {
3901 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3902
3903 if (lp->chipset == DC21040) {
3904 strcpy(name, "DE434/5");
3905 return status;
3906 } else { /* Search for a DEC name in the SROM */
3907 int tmp = *((char *)&lp->srom + 19) * 3;
3908 strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
3909 }
3910 name[8] = '\0';
3911 for (i=0; i<siglen; i++) {
3912 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3913 }
3914 if (i == siglen) {
3915 if (dec_only) {
3916 *name = '\0';
3917 } else { /* Use chip name to avoid confusion */
3918 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3919 ((lp->chipset == DC21041) ? "DC21041" :
3920 ((lp->chipset == DC21140) ? "DC21140" :
3921 ((lp->chipset == DC21142) ? "DC21142" :
3922 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3923 )))))));
3924 }
3925 if (lp->chipset != DC21041) {
3926 lp->useSROM = true; /* card is not recognisably DEC */
3927 }
3928 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3929 lp->useSROM = true;
3930 }
3931
3932 return status;
3933 }
3934
3935 /*
3936 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
3937 ** the DC21040, else read the SROM for the other chips.
3938 ** The SROM may not be present in a multi-MAC card, so first read the
3939 ** MAC address and check for a bad address. If there is a bad one then exit
3940 ** immediately with the prior srom contents intact (the h/w address will
3941 ** be fixed up later).
3942 */
3943 static void
DevicePresent(struct net_device * dev,u_long aprom_addr)3944 DevicePresent(struct net_device *dev, u_long aprom_addr)
3945 {
3946 int i, j=0;
3947 struct de4x5_private *lp = netdev_priv(dev);
3948
3949 if (lp->chipset == DC21040) {
3950 if (lp->bus == EISA) {
3951 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
3952 } else {
3953 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
3954 }
3955 } else { /* Read new srom */
3956 u_short tmp;
3957 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
3958 for (i=0; i<(ETH_ALEN>>1); i++) {
3959 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
3960 j += tmp; /* for check for 0:0:0:0:0:0 or ff:ff:ff:ff:ff:ff */
3961 *p = cpu_to_le16(tmp);
3962 }
3963 if (j == 0 || j == 3 * 0xffff) {
3964 /* could get 0 only from all-0 and 3 * 0xffff only from all-1 */
3965 return;
3966 }
3967
3968 p = (__le16 *)&lp->srom;
3969 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
3970 tmp = srom_rd(aprom_addr, i);
3971 *p++ = cpu_to_le16(tmp);
3972 }
3973 de4x5_dbg_srom(&lp->srom);
3974 }
3975 }
3976
3977 /*
3978 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
3979 ** pointer correctly (at least on my DE425 EISA card), this routine should do
3980 ** it...from depca.c.
3981 */
3982 static void
enet_addr_rst(u_long aprom_addr)3983 enet_addr_rst(u_long aprom_addr)
3984 {
3985 union {
3986 struct {
3987 u32 a;
3988 u32 b;
3989 } llsig;
3990 char Sig[sizeof(u32) << 1];
3991 } dev;
3992 short sigLength=0;
3993 s8 data;
3994 int i, j;
3995
3996 dev.llsig.a = ETH_PROM_SIG;
3997 dev.llsig.b = ETH_PROM_SIG;
3998 sigLength = sizeof(u32) << 1;
3999
4000 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4001 data = inb(aprom_addr);
4002 if (dev.Sig[j] == data) { /* track signature */
4003 j++;
4004 } else { /* lost signature; begin search again */
4005 if (data == dev.Sig[0]) { /* rare case.... */
4006 j=1;
4007 } else {
4008 j=0;
4009 }
4010 }
4011 }
4012 }
4013
4014 /*
4015 ** For the bad status case and no SROM, then add one to the previous
4016 ** address. However, need to add one backwards in case we have 0xff
4017 ** as one or more of the bytes. Only the last 3 bytes should be checked
4018 ** as the first three are invariant - assigned to an organisation.
4019 */
4020 static int
get_hw_addr(struct net_device * dev)4021 get_hw_addr(struct net_device *dev)
4022 {
4023 u_long iobase = dev->base_addr;
4024 int broken, i, k, tmp, status = 0;
4025 u_short j,chksum;
4026 struct de4x5_private *lp = netdev_priv(dev);
4027
4028 broken = de4x5_bad_srom(lp);
4029
4030 for (i=0,k=0,j=0;j<3;j++) {
4031 k <<= 1;
4032 if (k > 0xffff) k-=0xffff;
4033
4034 if (lp->bus == PCI) {
4035 if (lp->chipset == DC21040) {
4036 while ((tmp = inl(DE4X5_APROM)) < 0);
4037 k += (u_char) tmp;
4038 dev->dev_addr[i++] = (u_char) tmp;
4039 while ((tmp = inl(DE4X5_APROM)) < 0);
4040 k += (u_short) (tmp << 8);
4041 dev->dev_addr[i++] = (u_char) tmp;
4042 } else if (!broken) {
4043 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4044 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4045 } else if ((broken == SMC) || (broken == ACCTON)) {
4046 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4047 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4048 }
4049 } else {
4050 k += (u_char) (tmp = inb(EISA_APROM));
4051 dev->dev_addr[i++] = (u_char) tmp;
4052 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4053 dev->dev_addr[i++] = (u_char) tmp;
4054 }
4055
4056 if (k > 0xffff) k-=0xffff;
4057 }
4058 if (k == 0xffff) k=0;
4059
4060 if (lp->bus == PCI) {
4061 if (lp->chipset == DC21040) {
4062 while ((tmp = inl(DE4X5_APROM)) < 0);
4063 chksum = (u_char) tmp;
4064 while ((tmp = inl(DE4X5_APROM)) < 0);
4065 chksum |= (u_short) (tmp << 8);
4066 if ((k != chksum) && (dec_only)) status = -1;
4067 }
4068 } else {
4069 chksum = (u_char) inb(EISA_APROM);
4070 chksum |= (u_short) (inb(EISA_APROM) << 8);
4071 if ((k != chksum) && (dec_only)) status = -1;
4072 }
4073
4074 /* If possible, try to fix a broken card - SMC only so far */
4075 srom_repair(dev, broken);
4076
4077 #ifdef CONFIG_PPC_PMAC
4078 /*
4079 ** If the address starts with 00 a0, we have to bit-reverse
4080 ** each byte of the address.
4081 */
4082 if ( machine_is(powermac) &&
4083 (dev->dev_addr[0] == 0) &&
4084 (dev->dev_addr[1] == 0xa0) )
4085 {
4086 for (i = 0; i < ETH_ALEN; ++i)
4087 {
4088 int x = dev->dev_addr[i];
4089 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4090 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4091 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4092 }
4093 }
4094 #endif /* CONFIG_PPC_PMAC */
4095
4096 /* Test for a bad enet address */
4097 status = test_bad_enet(dev, status);
4098
4099 return status;
4100 }
4101
4102 /*
4103 ** Test for enet addresses in the first 32 bytes.
4104 */
4105 static int
de4x5_bad_srom(struct de4x5_private * lp)4106 de4x5_bad_srom(struct de4x5_private *lp)
4107 {
4108 int i, status = 0;
4109
4110 for (i = 0; i < ARRAY_SIZE(enet_det); i++) {
4111 if (!memcmp(&lp->srom, &enet_det[i], 3) &&
4112 !memcmp((char *)&lp->srom+0x10, &enet_det[i], 3)) {
4113 if (i == 0) {
4114 status = SMC;
4115 } else if (i == 1) {
4116 status = ACCTON;
4117 }
4118 break;
4119 }
4120 }
4121
4122 return status;
4123 }
4124
4125 static void
srom_repair(struct net_device * dev,int card)4126 srom_repair(struct net_device *dev, int card)
4127 {
4128 struct de4x5_private *lp = netdev_priv(dev);
4129
4130 switch(card) {
4131 case SMC:
4132 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4133 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4134 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4135 lp->useSROM = true;
4136 break;
4137 }
4138 }
4139
4140 /*
4141 ** Assume that the irq's do not follow the PCI spec - this is seems
4142 ** to be true so far (2 for 2).
4143 */
4144 static int
test_bad_enet(struct net_device * dev,int status)4145 test_bad_enet(struct net_device *dev, int status)
4146 {
4147 struct de4x5_private *lp = netdev_priv(dev);
4148 int i, tmp;
4149
4150 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4151 if ((tmp == 0) || (tmp == 0x5fa)) {
4152 if ((lp->chipset == last.chipset) &&
4153 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4154 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4155 for (i=ETH_ALEN-1; i>2; --i) {
4156 dev->dev_addr[i] += 1;
4157 if (dev->dev_addr[i] != 0) break;
4158 }
4159 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4160 if (!an_exception(lp)) {
4161 dev->irq = last.irq;
4162 }
4163
4164 status = 0;
4165 }
4166 } else if (!status) {
4167 last.chipset = lp->chipset;
4168 last.bus = lp->bus_num;
4169 last.irq = dev->irq;
4170 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4171 }
4172
4173 return status;
4174 }
4175
4176 /*
4177 ** List of board exceptions with correctly wired IRQs
4178 */
4179 static int
an_exception(struct de4x5_private * lp)4180 an_exception(struct de4x5_private *lp)
4181 {
4182 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4183 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4184 return -1;
4185 }
4186
4187 return 0;
4188 }
4189
4190 /*
4191 ** SROM Read
4192 */
4193 static short
srom_rd(u_long addr,u_char offset)4194 srom_rd(u_long addr, u_char offset)
4195 {
4196 sendto_srom(SROM_RD | SROM_SR, addr);
4197
4198 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4199 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4200 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4201
4202 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4203 }
4204
4205 static void
srom_latch(u_int command,u_long addr)4206 srom_latch(u_int command, u_long addr)
4207 {
4208 sendto_srom(command, addr);
4209 sendto_srom(command | DT_CLK, addr);
4210 sendto_srom(command, addr);
4211 }
4212
4213 static void
srom_command(u_int command,u_long addr)4214 srom_command(u_int command, u_long addr)
4215 {
4216 srom_latch(command, addr);
4217 srom_latch(command, addr);
4218 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4219 }
4220
4221 static void
srom_address(u_int command,u_long addr,u_char offset)4222 srom_address(u_int command, u_long addr, u_char offset)
4223 {
4224 int i, a;
4225
4226 a = offset << 2;
4227 for (i=0; i<6; i++, a <<= 1) {
4228 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4229 }
4230 udelay(1);
4231
4232 i = (getfrom_srom(addr) >> 3) & 0x01;
4233 }
4234
4235 static short
srom_data(u_int command,u_long addr)4236 srom_data(u_int command, u_long addr)
4237 {
4238 int i;
4239 short word = 0;
4240 s32 tmp;
4241
4242 for (i=0; i<16; i++) {
4243 sendto_srom(command | DT_CLK, addr);
4244 tmp = getfrom_srom(addr);
4245 sendto_srom(command, addr);
4246
4247 word = (word << 1) | ((tmp >> 3) & 0x01);
4248 }
4249
4250 sendto_srom(command & 0x0000ff00, addr);
4251
4252 return word;
4253 }
4254
4255 /*
4256 static void
4257 srom_busy(u_int command, u_long addr)
4258 {
4259 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4260
4261 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4262 mdelay(1);
4263 }
4264
4265 sendto_srom(command & 0x0000ff00, addr);
4266 }
4267 */
4268
4269 static void
sendto_srom(u_int command,u_long addr)4270 sendto_srom(u_int command, u_long addr)
4271 {
4272 outl(command, addr);
4273 udelay(1);
4274 }
4275
4276 static int
getfrom_srom(u_long addr)4277 getfrom_srom(u_long addr)
4278 {
4279 s32 tmp;
4280
4281 tmp = inl(addr);
4282 udelay(1);
4283
4284 return tmp;
4285 }
4286
4287 static int
srom_infoleaf_info(struct net_device * dev)4288 srom_infoleaf_info(struct net_device *dev)
4289 {
4290 struct de4x5_private *lp = netdev_priv(dev);
4291 int i, count;
4292 u_char *p;
4293
4294 /* Find the infoleaf decoder function that matches this chipset */
4295 for (i=0; i<INFOLEAF_SIZE; i++) {
4296 if (lp->chipset == infoleaf_array[i].chipset) break;
4297 }
4298 if (i == INFOLEAF_SIZE) {
4299 lp->useSROM = false;
4300 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4301 dev->name);
4302 return -ENXIO;
4303 }
4304
4305 lp->infoleaf_fn = infoleaf_array[i].fn;
4306
4307 /* Find the information offset that this function should use */
4308 count = *((u_char *)&lp->srom + 19);
4309 p = (u_char *)&lp->srom + 26;
4310
4311 if (count > 1) {
4312 for (i=count; i; --i, p+=3) {
4313 if (lp->device == *p) break;
4314 }
4315 if (i == 0) {
4316 lp->useSROM = false;
4317 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4318 dev->name, lp->device);
4319 return -ENXIO;
4320 }
4321 }
4322
4323 lp->infoleaf_offset = get_unaligned_le16(p + 1);
4324
4325 return 0;
4326 }
4327
4328 /*
4329 ** This routine loads any type 1 or 3 MII info into the mii device
4330 ** struct and executes any type 5 code to reset PHY devices for this
4331 ** controller.
4332 ** The info for the MII devices will be valid since the index used
4333 ** will follow the discovery process from MII address 1-31 then 0.
4334 */
4335 static void
srom_init(struct net_device * dev)4336 srom_init(struct net_device *dev)
4337 {
4338 struct de4x5_private *lp = netdev_priv(dev);
4339 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4340 u_char count;
4341
4342 p+=2;
4343 if (lp->chipset == DC21140) {
4344 lp->cache.gepc = (*p++ | GEP_CTRL);
4345 gep_wr(lp->cache.gepc, dev);
4346 }
4347
4348 /* Block count */
4349 count = *p++;
4350
4351 /* Jump the infoblocks to find types */
4352 for (;count; --count) {
4353 if (*p < 128) {
4354 p += COMPACT_LEN;
4355 } else if (*(p+1) == 5) {
4356 type5_infoblock(dev, 1, p);
4357 p += ((*p & BLOCK_LEN) + 1);
4358 } else if (*(p+1) == 4) {
4359 p += ((*p & BLOCK_LEN) + 1);
4360 } else if (*(p+1) == 3) {
4361 type3_infoblock(dev, 1, p);
4362 p += ((*p & BLOCK_LEN) + 1);
4363 } else if (*(p+1) == 2) {
4364 p += ((*p & BLOCK_LEN) + 1);
4365 } else if (*(p+1) == 1) {
4366 type1_infoblock(dev, 1, p);
4367 p += ((*p & BLOCK_LEN) + 1);
4368 } else {
4369 p += ((*p & BLOCK_LEN) + 1);
4370 }
4371 }
4372 }
4373
4374 /*
4375 ** A generic routine that writes GEP control, data and reset information
4376 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4377 */
4378 static void
srom_exec(struct net_device * dev,u_char * p)4379 srom_exec(struct net_device *dev, u_char *p)
4380 {
4381 struct de4x5_private *lp = netdev_priv(dev);
4382 u_long iobase = dev->base_addr;
4383 u_char count = (p ? *p++ : 0);
4384 u_short *w = (u_short *)p;
4385
4386 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4387
4388 if (lp->chipset != DC21140) RESET_SIA;
4389
4390 while (count--) {
4391 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4392 *p++ : get_unaligned_le16(w++)), dev);
4393 mdelay(2); /* 2ms per action */
4394 }
4395
4396 if (lp->chipset != DC21140) {
4397 outl(lp->cache.csr14, DE4X5_STRR);
4398 outl(lp->cache.csr13, DE4X5_SICR);
4399 }
4400 }
4401
4402 /*
4403 ** Basically this function is a NOP since it will never be called,
4404 ** unless I implement the DC21041 SROM functions. There's no need
4405 ** since the existing code will be satisfactory for all boards.
4406 */
4407 static int
dc21041_infoleaf(struct net_device * dev)4408 dc21041_infoleaf(struct net_device *dev)
4409 {
4410 return DE4X5_AUTOSENSE_MS;
4411 }
4412
4413 static int
dc21140_infoleaf(struct net_device * dev)4414 dc21140_infoleaf(struct net_device *dev)
4415 {
4416 struct de4x5_private *lp = netdev_priv(dev);
4417 u_char count = 0;
4418 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4419 int next_tick = DE4X5_AUTOSENSE_MS;
4420
4421 /* Read the connection type */
4422 p+=2;
4423
4424 /* GEP control */
4425 lp->cache.gepc = (*p++ | GEP_CTRL);
4426
4427 /* Block count */
4428 count = *p++;
4429
4430 /* Recursively figure out the info blocks */
4431 if (*p < 128) {
4432 next_tick = dc_infoblock[COMPACT](dev, count, p);
4433 } else {
4434 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4435 }
4436
4437 if (lp->tcount == count) {
4438 lp->media = NC;
4439 if (lp->media != lp->c_media) {
4440 de4x5_dbg_media(dev);
4441 lp->c_media = lp->media;
4442 }
4443 lp->media = INIT;
4444 lp->tcount = 0;
4445 lp->tx_enable = false;
4446 }
4447
4448 return next_tick & ~TIMER_CB;
4449 }
4450
4451 static int
dc21142_infoleaf(struct net_device * dev)4452 dc21142_infoleaf(struct net_device *dev)
4453 {
4454 struct de4x5_private *lp = netdev_priv(dev);
4455 u_char count = 0;
4456 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4457 int next_tick = DE4X5_AUTOSENSE_MS;
4458
4459 /* Read the connection type */
4460 p+=2;
4461
4462 /* Block count */
4463 count = *p++;
4464
4465 /* Recursively figure out the info blocks */
4466 if (*p < 128) {
4467 next_tick = dc_infoblock[COMPACT](dev, count, p);
4468 } else {
4469 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4470 }
4471
4472 if (lp->tcount == count) {
4473 lp->media = NC;
4474 if (lp->media != lp->c_media) {
4475 de4x5_dbg_media(dev);
4476 lp->c_media = lp->media;
4477 }
4478 lp->media = INIT;
4479 lp->tcount = 0;
4480 lp->tx_enable = false;
4481 }
4482
4483 return next_tick & ~TIMER_CB;
4484 }
4485
4486 static int
dc21143_infoleaf(struct net_device * dev)4487 dc21143_infoleaf(struct net_device *dev)
4488 {
4489 struct de4x5_private *lp = netdev_priv(dev);
4490 u_char count = 0;
4491 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4492 int next_tick = DE4X5_AUTOSENSE_MS;
4493
4494 /* Read the connection type */
4495 p+=2;
4496
4497 /* Block count */
4498 count = *p++;
4499
4500 /* Recursively figure out the info blocks */
4501 if (*p < 128) {
4502 next_tick = dc_infoblock[COMPACT](dev, count, p);
4503 } else {
4504 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4505 }
4506 if (lp->tcount == count) {
4507 lp->media = NC;
4508 if (lp->media != lp->c_media) {
4509 de4x5_dbg_media(dev);
4510 lp->c_media = lp->media;
4511 }
4512 lp->media = INIT;
4513 lp->tcount = 0;
4514 lp->tx_enable = false;
4515 }
4516
4517 return next_tick & ~TIMER_CB;
4518 }
4519
4520 /*
4521 ** The compact infoblock is only designed for DC21140[A] chips, so
4522 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4523 */
4524 static int
compact_infoblock(struct net_device * dev,u_char count,u_char * p)4525 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4526 {
4527 struct de4x5_private *lp = netdev_priv(dev);
4528 u_char flags, csr6;
4529
4530 /* Recursively figure out the info blocks */
4531 if (--count > lp->tcount) {
4532 if (*(p+COMPACT_LEN) < 128) {
4533 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4534 } else {
4535 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4536 }
4537 }
4538
4539 if ((lp->media == INIT) && (lp->timeout < 0)) {
4540 lp->ibn = COMPACT;
4541 lp->active = 0;
4542 gep_wr(lp->cache.gepc, dev);
4543 lp->infoblock_media = (*p++) & COMPACT_MC;
4544 lp->cache.gep = *p++;
4545 csr6 = *p++;
4546 flags = *p++;
4547
4548 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4549 lp->defMedium = (flags & 0x40) ? -1 : 0;
4550 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4551 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4552 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4553 lp->useMII = false;
4554
4555 de4x5_switch_mac_port(dev);
4556 }
4557
4558 return dc21140m_autoconf(dev);
4559 }
4560
4561 /*
4562 ** This block describes non MII media for the DC21140[A] only.
4563 */
4564 static int
type0_infoblock(struct net_device * dev,u_char count,u_char * p)4565 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4566 {
4567 struct de4x5_private *lp = netdev_priv(dev);
4568 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4569
4570 /* Recursively figure out the info blocks */
4571 if (--count > lp->tcount) {
4572 if (*(p+len) < 128) {
4573 return dc_infoblock[COMPACT](dev, count, p+len);
4574 } else {
4575 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4576 }
4577 }
4578
4579 if ((lp->media == INIT) && (lp->timeout < 0)) {
4580 lp->ibn = 0;
4581 lp->active = 0;
4582 gep_wr(lp->cache.gepc, dev);
4583 p+=2;
4584 lp->infoblock_media = (*p++) & BLOCK0_MC;
4585 lp->cache.gep = *p++;
4586 csr6 = *p++;
4587 flags = *p++;
4588
4589 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4590 lp->defMedium = (flags & 0x40) ? -1 : 0;
4591 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4592 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4593 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4594 lp->useMII = false;
4595
4596 de4x5_switch_mac_port(dev);
4597 }
4598
4599 return dc21140m_autoconf(dev);
4600 }
4601
4602 /* These functions are under construction! */
4603
4604 static int
type1_infoblock(struct net_device * dev,u_char count,u_char * p)4605 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4606 {
4607 struct de4x5_private *lp = netdev_priv(dev);
4608 u_char len = (*p & BLOCK_LEN)+1;
4609
4610 /* Recursively figure out the info blocks */
4611 if (--count > lp->tcount) {
4612 if (*(p+len) < 128) {
4613 return dc_infoblock[COMPACT](dev, count, p+len);
4614 } else {
4615 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4616 }
4617 }
4618
4619 p += 2;
4620 if (lp->state == INITIALISED) {
4621 lp->ibn = 1;
4622 lp->active = *p++;
4623 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4624 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4625 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4626 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4627 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4628 lp->phy[lp->active].ttm = get_unaligned_le16(p);
4629 return 0;
4630 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4631 lp->ibn = 1;
4632 lp->active = *p;
4633 lp->infoblock_csr6 = OMR_MII_100;
4634 lp->useMII = true;
4635 lp->infoblock_media = ANS;
4636
4637 de4x5_switch_mac_port(dev);
4638 }
4639
4640 return dc21140m_autoconf(dev);
4641 }
4642
4643 static int
type2_infoblock(struct net_device * dev,u_char count,u_char * p)4644 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4645 {
4646 struct de4x5_private *lp = netdev_priv(dev);
4647 u_char len = (*p & BLOCK_LEN)+1;
4648
4649 /* Recursively figure out the info blocks */
4650 if (--count > lp->tcount) {
4651 if (*(p+len) < 128) {
4652 return dc_infoblock[COMPACT](dev, count, p+len);
4653 } else {
4654 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4655 }
4656 }
4657
4658 if ((lp->media == INIT) && (lp->timeout < 0)) {
4659 lp->ibn = 2;
4660 lp->active = 0;
4661 p += 2;
4662 lp->infoblock_media = (*p) & MEDIA_CODE;
4663
4664 if ((*p++) & EXT_FIELD) {
4665 lp->cache.csr13 = get_unaligned_le16(p); p += 2;
4666 lp->cache.csr14 = get_unaligned_le16(p); p += 2;
4667 lp->cache.csr15 = get_unaligned_le16(p); p += 2;
4668 } else {
4669 lp->cache.csr13 = CSR13;
4670 lp->cache.csr14 = CSR14;
4671 lp->cache.csr15 = CSR15;
4672 }
4673 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4674 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16);
4675 lp->infoblock_csr6 = OMR_SIA;
4676 lp->useMII = false;
4677
4678 de4x5_switch_mac_port(dev);
4679 }
4680
4681 return dc2114x_autoconf(dev);
4682 }
4683
4684 static int
type3_infoblock(struct net_device * dev,u_char count,u_char * p)4685 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4686 {
4687 struct de4x5_private *lp = netdev_priv(dev);
4688 u_char len = (*p & BLOCK_LEN)+1;
4689
4690 /* Recursively figure out the info blocks */
4691 if (--count > lp->tcount) {
4692 if (*(p+len) < 128) {
4693 return dc_infoblock[COMPACT](dev, count, p+len);
4694 } else {
4695 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4696 }
4697 }
4698
4699 p += 2;
4700 if (lp->state == INITIALISED) {
4701 lp->ibn = 3;
4702 lp->active = *p++;
4703 if (MOTO_SROM_BUG) lp->active = 0;
4704 /* if (MOTO_SROM_BUG) statement indicates lp->active could
4705 * be 8 (i.e. the size of array lp->phy) */
4706 if (WARN_ON(lp->active >= ARRAY_SIZE(lp->phy)))
4707 return -EINVAL;
4708 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4709 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4710 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4711 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4712 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4713 lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2;
4714 lp->phy[lp->active].mci = *p;
4715 return 0;
4716 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4717 lp->ibn = 3;
4718 lp->active = *p;
4719 if (MOTO_SROM_BUG) lp->active = 0;
4720 lp->infoblock_csr6 = OMR_MII_100;
4721 lp->useMII = true;
4722 lp->infoblock_media = ANS;
4723
4724 de4x5_switch_mac_port(dev);
4725 }
4726
4727 return dc2114x_autoconf(dev);
4728 }
4729
4730 static int
type4_infoblock(struct net_device * dev,u_char count,u_char * p)4731 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4732 {
4733 struct de4x5_private *lp = netdev_priv(dev);
4734 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4735
4736 /* Recursively figure out the info blocks */
4737 if (--count > lp->tcount) {
4738 if (*(p+len) < 128) {
4739 return dc_infoblock[COMPACT](dev, count, p+len);
4740 } else {
4741 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4742 }
4743 }
4744
4745 if ((lp->media == INIT) && (lp->timeout < 0)) {
4746 lp->ibn = 4;
4747 lp->active = 0;
4748 p+=2;
4749 lp->infoblock_media = (*p++) & MEDIA_CODE;
4750 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4751 lp->cache.csr14 = CSR14;
4752 lp->cache.csr15 = CSR15;
4753 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4754 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4755 csr6 = *p++;
4756 flags = *p++;
4757
4758 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4759 lp->defMedium = (flags & 0x40) ? -1 : 0;
4760 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4761 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4762 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4763 lp->useMII = false;
4764
4765 de4x5_switch_mac_port(dev);
4766 }
4767
4768 return dc2114x_autoconf(dev);
4769 }
4770
4771 /*
4772 ** This block type provides information for resetting external devices
4773 ** (chips) through the General Purpose Register.
4774 */
4775 static int
type5_infoblock(struct net_device * dev,u_char count,u_char * p)4776 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4777 {
4778 struct de4x5_private *lp = netdev_priv(dev);
4779 u_char len = (*p & BLOCK_LEN)+1;
4780
4781 /* Recursively figure out the info blocks */
4782 if (--count > lp->tcount) {
4783 if (*(p+len) < 128) {
4784 return dc_infoblock[COMPACT](dev, count, p+len);
4785 } else {
4786 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4787 }
4788 }
4789
4790 /* Must be initializing to run this code */
4791 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4792 p+=2;
4793 lp->rst = p;
4794 srom_exec(dev, lp->rst);
4795 }
4796
4797 return DE4X5_AUTOSENSE_MS;
4798 }
4799
4800 /*
4801 ** MII Read/Write
4802 */
4803
4804 static int
mii_rd(u_char phyreg,u_char phyaddr,u_long ioaddr)4805 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4806 {
4807 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4808 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4809 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4810 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4811 mii_address(phyreg, ioaddr); /* PHY Register to read */
4812 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4813
4814 return mii_rdata(ioaddr); /* Read data */
4815 }
4816
4817 static void
mii_wr(int data,u_char phyreg,u_char phyaddr,u_long ioaddr)4818 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4819 {
4820 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4821 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4822 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4823 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4824 mii_address(phyreg, ioaddr); /* PHY Register to write */
4825 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4826 data = mii_swap(data, 16); /* Swap data bit ordering */
4827 mii_wdata(data, 16, ioaddr); /* Write data */
4828 }
4829
4830 static int
mii_rdata(u_long ioaddr)4831 mii_rdata(u_long ioaddr)
4832 {
4833 int i;
4834 s32 tmp = 0;
4835
4836 for (i=0; i<16; i++) {
4837 tmp <<= 1;
4838 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4839 }
4840
4841 return tmp;
4842 }
4843
4844 static void
mii_wdata(int data,int len,u_long ioaddr)4845 mii_wdata(int data, int len, u_long ioaddr)
4846 {
4847 int i;
4848
4849 for (i=0; i<len; i++) {
4850 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4851 data >>= 1;
4852 }
4853 }
4854
4855 static void
mii_address(u_char addr,u_long ioaddr)4856 mii_address(u_char addr, u_long ioaddr)
4857 {
4858 int i;
4859
4860 addr = mii_swap(addr, 5);
4861 for (i=0; i<5; i++) {
4862 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4863 addr >>= 1;
4864 }
4865 }
4866
4867 static void
mii_ta(u_long rw,u_long ioaddr)4868 mii_ta(u_long rw, u_long ioaddr)
4869 {
4870 if (rw == MII_STWR) {
4871 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4872 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4873 } else {
4874 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4875 }
4876 }
4877
4878 static int
mii_swap(int data,int len)4879 mii_swap(int data, int len)
4880 {
4881 int i, tmp = 0;
4882
4883 for (i=0; i<len; i++) {
4884 tmp <<= 1;
4885 tmp |= (data & 1);
4886 data >>= 1;
4887 }
4888
4889 return tmp;
4890 }
4891
4892 static void
sendto_mii(u32 command,int data,u_long ioaddr)4893 sendto_mii(u32 command, int data, u_long ioaddr)
4894 {
4895 u32 j;
4896
4897 j = (data & 1) << 17;
4898 outl(command | j, ioaddr);
4899 udelay(1);
4900 outl(command | MII_MDC | j, ioaddr);
4901 udelay(1);
4902 }
4903
4904 static int
getfrom_mii(u32 command,u_long ioaddr)4905 getfrom_mii(u32 command, u_long ioaddr)
4906 {
4907 outl(command, ioaddr);
4908 udelay(1);
4909 outl(command | MII_MDC, ioaddr);
4910 udelay(1);
4911
4912 return (inl(ioaddr) >> 19) & 1;
4913 }
4914
4915 /*
4916 ** Here's 3 ways to calculate the OUI from the ID registers.
4917 */
4918 static int
mii_get_oui(u_char phyaddr,u_long ioaddr)4919 mii_get_oui(u_char phyaddr, u_long ioaddr)
4920 {
4921 /*
4922 union {
4923 u_short reg;
4924 u_char breg[2];
4925 } a;
4926 int i, r2, r3, ret=0;*/
4927 int r2, r3;
4928
4929 /* Read r2 and r3 */
4930 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
4931 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
4932 /* SEEQ and Cypress way * /
4933 / * Shuffle r2 and r3 * /
4934 a.reg=0;
4935 r3 = ((r3>>10)|(r2<<6))&0x0ff;
4936 r2 = ((r2>>2)&0x3fff);
4937
4938 / * Bit reverse r3 * /
4939 for (i=0;i<8;i++) {
4940 ret<<=1;
4941 ret |= (r3&1);
4942 r3>>=1;
4943 }
4944
4945 / * Bit reverse r2 * /
4946 for (i=0;i<16;i++) {
4947 a.reg<<=1;
4948 a.reg |= (r2&1);
4949 r2>>=1;
4950 }
4951
4952 / * Swap r2 bytes * /
4953 i=a.breg[0];
4954 a.breg[0]=a.breg[1];
4955 a.breg[1]=i;
4956
4957 return (a.reg<<8)|ret; */ /* SEEQ and Cypress way */
4958 /* return (r2<<6)|(u_int)(r3>>10); */ /* NATIONAL and BROADCOM way */
4959 return r2; /* (I did it) My way */
4960 }
4961
4962 /*
4963 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
4964 */
4965 static int
mii_get_phy(struct net_device * dev)4966 mii_get_phy(struct net_device *dev)
4967 {
4968 struct de4x5_private *lp = netdev_priv(dev);
4969 u_long iobase = dev->base_addr;
4970 int i, j, k, n, limit=ARRAY_SIZE(phy_info);
4971 int id;
4972
4973 lp->active = 0;
4974 lp->useMII = true;
4975
4976 /* Search the MII address space for possible PHY devices */
4977 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
4978 lp->phy[lp->active].addr = i;
4979 if (i==0) n++; /* Count cycles */
4980 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
4981 id = mii_get_oui(i, DE4X5_MII);
4982 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
4983 for (j=0; j<limit; j++) { /* Search PHY table */
4984 if (id != phy_info[j].id) continue; /* ID match? */
4985 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
4986 if (k < DE4X5_MAX_PHY) {
4987 memcpy((char *)&lp->phy[k],
4988 (char *)&phy_info[j], sizeof(struct phy_table));
4989 lp->phy[k].addr = i;
4990 lp->mii_cnt++;
4991 lp->active++;
4992 } else {
4993 goto purgatory; /* Stop the search */
4994 }
4995 break;
4996 }
4997 if ((j == limit) && (i < DE4X5_MAX_MII)) {
4998 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
4999 if (k < DE4X5_MAX_PHY) {
5000 lp->phy[k].addr = i;
5001 lp->phy[k].id = id;
5002 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5003 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5004 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5005 lp->mii_cnt++;
5006 lp->active++;
5007 printk("%s: Using generic MII device control. If the board doesn't operate,\nplease mail the following dump to the author:\n", dev->name);
5008 j = de4x5_debug;
5009 de4x5_debug |= DEBUG_MII;
5010 de4x5_dbg_mii(dev, k);
5011 de4x5_debug = j;
5012 printk("\n");
5013 } else {
5014 goto purgatory;
5015 }
5016 }
5017 }
5018 purgatory:
5019 lp->active = 0;
5020 if (lp->phy[0].id) { /* Reset the PHY devices */
5021 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/
5022 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5023 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5024
5025 de4x5_dbg_mii(dev, k);
5026 }
5027 }
5028 if (!lp->mii_cnt) lp->useMII = false;
5029
5030 return lp->mii_cnt;
5031 }
5032
5033 static char *
build_setup_frame(struct net_device * dev,int mode)5034 build_setup_frame(struct net_device *dev, int mode)
5035 {
5036 struct de4x5_private *lp = netdev_priv(dev);
5037 int i;
5038 char *pa = lp->setup_frame;
5039
5040 /* Initialise the setup frame */
5041 if (mode == ALL) {
5042 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5043 }
5044
5045 if (lp->setup_f == HASH_PERF) {
5046 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5047 *(pa + i) = dev->dev_addr[i]; /* Host address */
5048 if (i & 0x01) pa += 2;
5049 }
5050 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5051 } else {
5052 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5053 *(pa + (i&1)) = dev->dev_addr[i];
5054 if (i & 0x01) pa += 4;
5055 }
5056 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5057 *(pa + (i&1)) = (char) 0xff;
5058 if (i & 0x01) pa += 4;
5059 }
5060 }
5061
5062 return pa; /* Points to the next entry */
5063 }
5064
5065 static void
disable_ast(struct net_device * dev)5066 disable_ast(struct net_device *dev)
5067 {
5068 struct de4x5_private *lp = netdev_priv(dev);
5069 del_timer_sync(&lp->timer);
5070 }
5071
5072 static long
de4x5_switch_mac_port(struct net_device * dev)5073 de4x5_switch_mac_port(struct net_device *dev)
5074 {
5075 struct de4x5_private *lp = netdev_priv(dev);
5076 u_long iobase = dev->base_addr;
5077 s32 omr;
5078
5079 STOP_DE4X5;
5080
5081 /* Assert the OMR_PS bit in CSR6 */
5082 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5083 OMR_FDX));
5084 omr |= lp->infoblock_csr6;
5085 if (omr & OMR_PS) omr |= OMR_HBD;
5086 outl(omr, DE4X5_OMR);
5087
5088 /* Soft Reset */
5089 RESET_DE4X5;
5090
5091 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5092 if (lp->chipset == DC21140) {
5093 gep_wr(lp->cache.gepc, dev);
5094 gep_wr(lp->cache.gep, dev);
5095 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5096 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5097 }
5098
5099 /* Restore CSR6 */
5100 outl(omr, DE4X5_OMR);
5101
5102 /* Reset CSR8 */
5103 inl(DE4X5_MFC);
5104
5105 return omr;
5106 }
5107
5108 static void
gep_wr(s32 data,struct net_device * dev)5109 gep_wr(s32 data, struct net_device *dev)
5110 {
5111 struct de4x5_private *lp = netdev_priv(dev);
5112 u_long iobase = dev->base_addr;
5113
5114 if (lp->chipset == DC21140) {
5115 outl(data, DE4X5_GEP);
5116 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5117 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5118 }
5119 }
5120
5121 static int
gep_rd(struct net_device * dev)5122 gep_rd(struct net_device *dev)
5123 {
5124 struct de4x5_private *lp = netdev_priv(dev);
5125 u_long iobase = dev->base_addr;
5126
5127 if (lp->chipset == DC21140) {
5128 return inl(DE4X5_GEP);
5129 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5130 return inl(DE4X5_SIGR) & 0x000fffff;
5131 }
5132
5133 return 0;
5134 }
5135
5136 static void
yawn(struct net_device * dev,int state)5137 yawn(struct net_device *dev, int state)
5138 {
5139 struct de4x5_private *lp = netdev_priv(dev);
5140 u_long iobase = dev->base_addr;
5141
5142 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5143
5144 if(lp->bus == EISA) {
5145 switch(state) {
5146 case WAKEUP:
5147 outb(WAKEUP, PCI_CFPM);
5148 mdelay(10);
5149 break;
5150
5151 case SNOOZE:
5152 outb(SNOOZE, PCI_CFPM);
5153 break;
5154
5155 case SLEEP:
5156 outl(0, DE4X5_SICR);
5157 outb(SLEEP, PCI_CFPM);
5158 break;
5159 }
5160 } else {
5161 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5162 switch(state) {
5163 case WAKEUP:
5164 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5165 mdelay(10);
5166 break;
5167
5168 case SNOOZE:
5169 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5170 break;
5171
5172 case SLEEP:
5173 outl(0, DE4X5_SICR);
5174 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5175 break;
5176 }
5177 }
5178 }
5179
5180 static void
de4x5_parse_params(struct net_device * dev)5181 de4x5_parse_params(struct net_device *dev)
5182 {
5183 struct de4x5_private *lp = netdev_priv(dev);
5184 char *p, *q, t;
5185
5186 lp->params.fdx = false;
5187 lp->params.autosense = AUTO;
5188
5189 if (args == NULL) return;
5190
5191 if ((p = strstr(args, dev->name))) {
5192 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5193 t = *q;
5194 *q = '\0';
5195
5196 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = true;
5197
5198 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5199 if (strstr(p, "TP_NW")) {
5200 lp->params.autosense = TP_NW;
5201 } else if (strstr(p, "TP")) {
5202 lp->params.autosense = TP;
5203 } else if (strstr(p, "BNC_AUI")) {
5204 lp->params.autosense = BNC;
5205 } else if (strstr(p, "BNC")) {
5206 lp->params.autosense = BNC;
5207 } else if (strstr(p, "AUI")) {
5208 lp->params.autosense = AUI;
5209 } else if (strstr(p, "10Mb")) {
5210 lp->params.autosense = _10Mb;
5211 } else if (strstr(p, "100Mb")) {
5212 lp->params.autosense = _100Mb;
5213 } else if (strstr(p, "AUTO")) {
5214 lp->params.autosense = AUTO;
5215 }
5216 }
5217 *q = t;
5218 }
5219 }
5220
5221 static void
de4x5_dbg_open(struct net_device * dev)5222 de4x5_dbg_open(struct net_device *dev)
5223 {
5224 struct de4x5_private *lp = netdev_priv(dev);
5225 int i;
5226
5227 if (de4x5_debug & DEBUG_OPEN) {
5228 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5229 printk("\tphysical address: %pM\n", dev->dev_addr);
5230 printk("Descriptor head addresses:\n");
5231 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5232 printk("Descriptor addresses:\nRX: ");
5233 for (i=0;i<lp->rxRingSize-1;i++){
5234 if (i < 3) {
5235 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5236 }
5237 }
5238 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5239 printk("TX: ");
5240 for (i=0;i<lp->txRingSize-1;i++){
5241 if (i < 3) {
5242 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5243 }
5244 }
5245 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5246 printk("Descriptor buffers:\nRX: ");
5247 for (i=0;i<lp->rxRingSize-1;i++){
5248 if (i < 3) {
5249 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5250 }
5251 }
5252 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5253 printk("TX: ");
5254 for (i=0;i<lp->txRingSize-1;i++){
5255 if (i < 3) {
5256 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5257 }
5258 }
5259 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5260 printk("Ring size:\nRX: %d\nTX: %d\n",
5261 (short)lp->rxRingSize,
5262 (short)lp->txRingSize);
5263 }
5264 }
5265
5266 static void
de4x5_dbg_mii(struct net_device * dev,int k)5267 de4x5_dbg_mii(struct net_device *dev, int k)
5268 {
5269 struct de4x5_private *lp = netdev_priv(dev);
5270 u_long iobase = dev->base_addr;
5271
5272 if (de4x5_debug & DEBUG_MII) {
5273 printk("\nMII device address: %d\n", lp->phy[k].addr);
5274 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5275 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5276 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5277 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5278 if (lp->phy[k].id != BROADCOM_T4) {
5279 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5280 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5281 }
5282 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5283 if (lp->phy[k].id != BROADCOM_T4) {
5284 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5285 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5286 } else {
5287 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5288 }
5289 }
5290 }
5291
5292 static void
de4x5_dbg_media(struct net_device * dev)5293 de4x5_dbg_media(struct net_device *dev)
5294 {
5295 struct de4x5_private *lp = netdev_priv(dev);
5296
5297 if (lp->media != lp->c_media) {
5298 if (de4x5_debug & DEBUG_MEDIA) {
5299 printk("%s: media is %s%s\n", dev->name,
5300 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5301 (lp->media == TP ? "TP" :
5302 (lp->media == ANS ? "TP/Nway" :
5303 (lp->media == BNC ? "BNC" :
5304 (lp->media == AUI ? "AUI" :
5305 (lp->media == BNC_AUI ? "BNC/AUI" :
5306 (lp->media == EXT_SIA ? "EXT SIA" :
5307 (lp->media == _100Mb ? "100Mb/s" :
5308 (lp->media == _10Mb ? "10Mb/s" :
5309 "???"
5310 ))))))))), (lp->fdx?" full duplex.":"."));
5311 }
5312 lp->c_media = lp->media;
5313 }
5314 }
5315
5316 static void
de4x5_dbg_srom(struct de4x5_srom * p)5317 de4x5_dbg_srom(struct de4x5_srom *p)
5318 {
5319 int i;
5320
5321 if (de4x5_debug & DEBUG_SROM) {
5322 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5323 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5324 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5325 printk("SROM version: %02x\n", (u_char)(p->version));
5326 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5327
5328 printk("Hardware Address: %pM\n", p->ieee_addr);
5329 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5330 for (i=0; i<64; i++) {
5331 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5332 }
5333 }
5334 }
5335
5336 static void
de4x5_dbg_rx(struct sk_buff * skb,int len)5337 de4x5_dbg_rx(struct sk_buff *skb, int len)
5338 {
5339 int i, j;
5340
5341 if (de4x5_debug & DEBUG_RX) {
5342 printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n",
5343 skb->data, &skb->data[6],
5344 (u_char)skb->data[12],
5345 (u_char)skb->data[13],
5346 len);
5347 for (j=0; len>0;j+=16, len-=16) {
5348 printk(" %03x: ",j);
5349 for (i=0; i<16 && i<len; i++) {
5350 printk("%02x ",(u_char)skb->data[i+j]);
5351 }
5352 printk("\n");
5353 }
5354 }
5355 }
5356
5357 /*
5358 ** Perform IOCTL call functions here. Some are privileged operations and the
5359 ** effective uid is checked in those cases. In the normal course of events
5360 ** this function is only used for my testing.
5361 */
5362 static int
de4x5_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)5363 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5364 {
5365 struct de4x5_private *lp = netdev_priv(dev);
5366 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5367 u_long iobase = dev->base_addr;
5368 int i, j, status = 0;
5369 s32 omr;
5370 union {
5371 u8 addr[144];
5372 u16 sval[72];
5373 u32 lval[36];
5374 } tmp;
5375 u_long flags = 0;
5376
5377 switch(ioc->cmd) {
5378 case DE4X5_GET_HWADDR: /* Get the hardware address */
5379 ioc->len = ETH_ALEN;
5380 for (i=0; i<ETH_ALEN; i++) {
5381 tmp.addr[i] = dev->dev_addr[i];
5382 }
5383 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5384 break;
5385
5386 case DE4X5_SET_HWADDR: /* Set the hardware address */
5387 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5388 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5389 if (netif_queue_stopped(dev))
5390 return -EBUSY;
5391 netif_stop_queue(dev);
5392 for (i=0; i<ETH_ALEN; i++) {
5393 dev->dev_addr[i] = tmp.addr[i];
5394 }
5395 build_setup_frame(dev, PHYS_ADDR_ONLY);
5396 /* Set up the descriptor and give ownership to the card */
5397 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5398 SETUP_FRAME_LEN, (struct sk_buff *)1);
5399 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
5400 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5401 netif_wake_queue(dev); /* Unlock the TX ring */
5402 break;
5403
5404 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5405 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5406 printk("%s: Boo!\n", dev->name);
5407 break;
5408
5409 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5410 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5411 omr = inl(DE4X5_OMR);
5412 omr |= OMR_PM;
5413 outl(omr, DE4X5_OMR);
5414 break;
5415
5416 case DE4X5_GET_STATS: /* Get the driver statistics */
5417 {
5418 struct pkt_stats statbuf;
5419 ioc->len = sizeof(statbuf);
5420 spin_lock_irqsave(&lp->lock, flags);
5421 memcpy(&statbuf, &lp->pktStats, ioc->len);
5422 spin_unlock_irqrestore(&lp->lock, flags);
5423 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5424 return -EFAULT;
5425 break;
5426 }
5427 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5428 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5429 spin_lock_irqsave(&lp->lock, flags);
5430 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5431 spin_unlock_irqrestore(&lp->lock, flags);
5432 break;
5433
5434 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5435 tmp.addr[0] = inl(DE4X5_OMR);
5436 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5437 break;
5438
5439 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5440 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5441 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5442 outl(tmp.addr[0], DE4X5_OMR);
5443 break;
5444
5445 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5446 j = 0;
5447 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5448 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5449 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5450 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5451 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5452 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5453 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5454 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5455 ioc->len = j;
5456 if (copy_to_user(ioc->data, tmp.lval, ioc->len))
5457 return -EFAULT;
5458 break;
5459
5460 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5461 /*
5462 case DE4X5_DUMP:
5463 j = 0;
5464 tmp.addr[j++] = dev->irq;
5465 for (i=0; i<ETH_ALEN; i++) {
5466 tmp.addr[j++] = dev->dev_addr[i];
5467 }
5468 tmp.addr[j++] = lp->rxRingSize;
5469 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5470 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5471
5472 for (i=0;i<lp->rxRingSize-1;i++){
5473 if (i < 3) {
5474 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5475 }
5476 }
5477 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5478 for (i=0;i<lp->txRingSize-1;i++){
5479 if (i < 3) {
5480 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5481 }
5482 }
5483 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5484
5485 for (i=0;i<lp->rxRingSize-1;i++){
5486 if (i < 3) {
5487 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5488 }
5489 }
5490 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5491 for (i=0;i<lp->txRingSize-1;i++){
5492 if (i < 3) {
5493 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5494 }
5495 }
5496 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5497
5498 for (i=0;i<lp->rxRingSize;i++){
5499 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5500 }
5501 for (i=0;i<lp->txRingSize;i++){
5502 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5503 }
5504
5505 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5506 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5507 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5508 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5509 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5510 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5511 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5512 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5513 tmp.lval[j>>2] = lp->chipset; j+=4;
5514 if (lp->chipset == DC21140) {
5515 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5516 } else {
5517 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5518 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5519 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5520 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5521 }
5522 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5523 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5524 tmp.lval[j>>2] = lp->active; j+=4;
5525 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5526 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5527 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5528 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5529 if (lp->phy[lp->active].id != BROADCOM_T4) {
5530 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5531 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5532 }
5533 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5534 if (lp->phy[lp->active].id != BROADCOM_T4) {
5535 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5536 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5537 } else {
5538 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5539 }
5540 }
5541
5542 tmp.addr[j++] = lp->txRingSize;
5543 tmp.addr[j++] = netif_queue_stopped(dev);
5544
5545 ioc->len = j;
5546 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5547 break;
5548
5549 */
5550 default:
5551 return -EOPNOTSUPP;
5552 }
5553
5554 return status;
5555 }
5556
de4x5_module_init(void)5557 static int __init de4x5_module_init (void)
5558 {
5559 int err = 0;
5560
5561 #ifdef CONFIG_PCI
5562 err = pci_register_driver(&de4x5_pci_driver);
5563 #endif
5564 #ifdef CONFIG_EISA
5565 err |= eisa_driver_register (&de4x5_eisa_driver);
5566 #endif
5567
5568 return err;
5569 }
5570
de4x5_module_exit(void)5571 static void __exit de4x5_module_exit (void)
5572 {
5573 #ifdef CONFIG_PCI
5574 pci_unregister_driver (&de4x5_pci_driver);
5575 #endif
5576 #ifdef CONFIG_EISA
5577 eisa_driver_unregister (&de4x5_eisa_driver);
5578 #endif
5579 }
5580
5581 module_init (de4x5_module_init);
5582 module_exit (de4x5_module_exit);
5583