1 /*
2 * QorIQ 10G MDIO Controller
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * Authors: Andy Fleming <afleming@freescale.com>
7 * Timur Tabi <timur@freescale.com>
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/phy.h>
19 #include <linux/mdio.h>
20 #include <linux/of_address.h>
21 #include <linux/of_platform.h>
22 #include <linux/of_mdio.h>
23
24 /* Number of microseconds to wait for a register to respond */
25 #define TIMEOUT 1000
26
27 struct tgec_mdio_controller {
28 __be32 reserved[12];
29 __be32 mdio_stat; /* MDIO configuration and status */
30 __be32 mdio_ctl; /* MDIO control */
31 __be32 mdio_data; /* MDIO data */
32 __be32 mdio_addr; /* MDIO address */
33 } __packed;
34
35 #define MDIO_STAT_ENC BIT(6)
36 #define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
37 #define MDIO_STAT_BSY BIT(0)
38 #define MDIO_STAT_RD_ER BIT(1)
39 #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
40 #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
41 #define MDIO_CTL_PRE_DIS BIT(10)
42 #define MDIO_CTL_SCAN_EN BIT(11)
43 #define MDIO_CTL_POST_INC BIT(14)
44 #define MDIO_CTL_READ BIT(15)
45
46 #define MDIO_DATA(x) (x & 0xffff)
47 #define MDIO_DATA_BSY BIT(31)
48
49 struct mdio_fsl_priv {
50 struct tgec_mdio_controller __iomem *mdio_base;
51 bool is_little_endian;
52 bool has_a011043;
53 };
54
xgmac_read32(void __iomem * regs,bool is_little_endian)55 static u32 xgmac_read32(void __iomem *regs,
56 bool is_little_endian)
57 {
58 if (is_little_endian)
59 return ioread32(regs);
60 else
61 return ioread32be(regs);
62 }
63
xgmac_write32(u32 value,void __iomem * regs,bool is_little_endian)64 static void xgmac_write32(u32 value,
65 void __iomem *regs,
66 bool is_little_endian)
67 {
68 if (is_little_endian)
69 iowrite32(value, regs);
70 else
71 iowrite32be(value, regs);
72 }
73
74 /*
75 * Wait until the MDIO bus is free
76 */
xgmac_wait_until_free(struct device * dev,struct tgec_mdio_controller __iomem * regs,bool is_little_endian)77 static int xgmac_wait_until_free(struct device *dev,
78 struct tgec_mdio_controller __iomem *regs,
79 bool is_little_endian)
80 {
81 unsigned int timeout;
82
83 /* Wait till the bus is free */
84 timeout = TIMEOUT;
85 while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
86 MDIO_STAT_BSY) && timeout) {
87 cpu_relax();
88 timeout--;
89 }
90
91 if (!timeout) {
92 dev_err(dev, "timeout waiting for bus to be free\n");
93 return -ETIMEDOUT;
94 }
95
96 return 0;
97 }
98
99 /*
100 * Wait till the MDIO read or write operation is complete
101 */
xgmac_wait_until_done(struct device * dev,struct tgec_mdio_controller __iomem * regs,bool is_little_endian)102 static int xgmac_wait_until_done(struct device *dev,
103 struct tgec_mdio_controller __iomem *regs,
104 bool is_little_endian)
105 {
106 unsigned int timeout;
107
108 /* Wait till the MDIO write is complete */
109 timeout = TIMEOUT;
110 while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
111 MDIO_STAT_BSY) && timeout) {
112 cpu_relax();
113 timeout--;
114 }
115
116 if (!timeout) {
117 dev_err(dev, "timeout waiting for operation to complete\n");
118 return -ETIMEDOUT;
119 }
120
121 return 0;
122 }
123
124 /*
125 * Write value to the PHY for this device to the register at regnum,waiting
126 * until the write is done before it returns. All PHY configuration has to be
127 * done through the TSEC1 MIIM regs.
128 */
xgmac_mdio_write(struct mii_bus * bus,int phy_id,int regnum,u16 value)129 static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
130 {
131 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
132 struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
133 uint16_t dev_addr;
134 u32 mdio_ctl, mdio_stat;
135 int ret;
136 bool endian = priv->is_little_endian;
137
138 mdio_stat = xgmac_read32(®s->mdio_stat, endian);
139 if (regnum & MII_ADDR_C45) {
140 /* Clause 45 (ie 10G) */
141 dev_addr = (regnum >> 16) & 0x1f;
142 mdio_stat |= MDIO_STAT_ENC;
143 } else {
144 /* Clause 22 (ie 1G) */
145 dev_addr = regnum & 0x1f;
146 mdio_stat &= ~MDIO_STAT_ENC;
147 }
148
149 xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
150
151 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
152 if (ret)
153 return ret;
154
155 /* Set the port and dev addr */
156 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
157 xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
158
159 /* Set the register address */
160 if (regnum & MII_ADDR_C45) {
161 xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
162
163 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
164 if (ret)
165 return ret;
166 }
167
168 /* Write the value to the register */
169 xgmac_write32(MDIO_DATA(value), ®s->mdio_data, endian);
170
171 ret = xgmac_wait_until_done(&bus->dev, regs, endian);
172 if (ret)
173 return ret;
174
175 return 0;
176 }
177
178 /*
179 * Reads from register regnum in the PHY for device dev, returning the value.
180 * Clears miimcom first. All PHY configuration has to be done through the
181 * TSEC1 MIIM regs.
182 */
xgmac_mdio_read(struct mii_bus * bus,int phy_id,int regnum)183 static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
184 {
185 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
186 struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
187 uint16_t dev_addr;
188 uint32_t mdio_stat;
189 uint32_t mdio_ctl;
190 uint16_t value;
191 int ret;
192 bool endian = priv->is_little_endian;
193
194 mdio_stat = xgmac_read32(®s->mdio_stat, endian);
195 if (regnum & MII_ADDR_C45) {
196 dev_addr = (regnum >> 16) & 0x1f;
197 mdio_stat |= MDIO_STAT_ENC;
198 } else {
199 dev_addr = regnum & 0x1f;
200 mdio_stat &= ~MDIO_STAT_ENC;
201 }
202
203 xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
204
205 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
206 if (ret)
207 return ret;
208
209 /* Set the Port and Device Addrs */
210 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
211 xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
212
213 /* Set the register address */
214 if (regnum & MII_ADDR_C45) {
215 xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
216
217 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
218 if (ret)
219 return ret;
220 }
221
222 /* Initiate the read */
223 xgmac_write32(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl, endian);
224
225 ret = xgmac_wait_until_done(&bus->dev, regs, endian);
226 if (ret)
227 return ret;
228
229 /* Return all Fs if nothing was there */
230 if ((xgmac_read32(®s->mdio_stat, endian) & MDIO_STAT_RD_ER) &&
231 !priv->has_a011043) {
232 dev_err(&bus->dev,
233 "Error while reading PHY%d reg at %d.%hhu\n",
234 phy_id, dev_addr, regnum);
235 return 0xffff;
236 }
237
238 value = xgmac_read32(®s->mdio_data, endian) & 0xffff;
239 dev_dbg(&bus->dev, "read %04x\n", value);
240
241 return value;
242 }
243
xgmac_mdio_probe(struct platform_device * pdev)244 static int xgmac_mdio_probe(struct platform_device *pdev)
245 {
246 struct device_node *np = pdev->dev.of_node;
247 struct mii_bus *bus;
248 struct resource res;
249 struct mdio_fsl_priv *priv;
250 int ret;
251
252 ret = of_address_to_resource(np, 0, &res);
253 if (ret) {
254 dev_err(&pdev->dev, "could not obtain address\n");
255 return ret;
256 }
257
258 bus = mdiobus_alloc_size(sizeof(struct mdio_fsl_priv));
259 if (!bus)
260 return -ENOMEM;
261
262 bus->name = "Freescale XGMAC MDIO Bus";
263 bus->read = xgmac_mdio_read;
264 bus->write = xgmac_mdio_write;
265 bus->parent = &pdev->dev;
266 snprintf(bus->id, MII_BUS_ID_SIZE, "%llx", (unsigned long long)res.start);
267
268 /* Set the PHY base address */
269 priv = bus->priv;
270 priv->mdio_base = of_iomap(np, 0);
271 if (!priv->mdio_base) {
272 ret = -ENOMEM;
273 goto err_ioremap;
274 }
275
276 if (of_get_property(pdev->dev.of_node,
277 "little-endian", NULL))
278 priv->is_little_endian = true;
279 else
280 priv->is_little_endian = false;
281
282 priv->has_a011043 = of_property_read_bool(pdev->dev.of_node,
283 "fsl,erratum-a011043");
284
285 ret = of_mdiobus_register(bus, np);
286 if (ret) {
287 dev_err(&pdev->dev, "cannot register MDIO bus\n");
288 goto err_registration;
289 }
290
291 platform_set_drvdata(pdev, bus);
292
293 return 0;
294
295 err_registration:
296 iounmap(priv->mdio_base);
297
298 err_ioremap:
299 mdiobus_free(bus);
300
301 return ret;
302 }
303
xgmac_mdio_remove(struct platform_device * pdev)304 static int xgmac_mdio_remove(struct platform_device *pdev)
305 {
306 struct mii_bus *bus = platform_get_drvdata(pdev);
307 struct mdio_fsl_priv *priv = bus->priv;
308
309 mdiobus_unregister(bus);
310 iounmap(priv->mdio_base);
311 mdiobus_free(bus);
312
313 return 0;
314 }
315
316 static const struct of_device_id xgmac_mdio_match[] = {
317 {
318 .compatible = "fsl,fman-xmdio",
319 },
320 {
321 .compatible = "fsl,fman-memac-mdio",
322 },
323 {},
324 };
325 MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
326
327 static struct platform_driver xgmac_mdio_driver = {
328 .driver = {
329 .name = "fsl-fman_xmdio",
330 .of_match_table = xgmac_mdio_match,
331 },
332 .probe = xgmac_mdio_probe,
333 .remove = xgmac_mdio_remove,
334 };
335
336 module_platform_driver(xgmac_mdio_driver);
337
338 MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
339 MODULE_LICENSE("GPL v2");
340