1 /*
2 * Copyright (c) 2014-2015 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #include <linux/errno.h>
11 #include <linux/etherdevice.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/netdevice.h>
18 #include <linux/of_address.h>
19 #include <linux/of.h>
20 #include <linux/of_mdio.h>
21 #include <linux/of_platform.h>
22 #include <linux/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/spinlock_types.h>
26
27 #define MDIO_DRV_NAME "Hi-HNS_MDIO"
28 #define MDIO_BUS_NAME "Hisilicon MII Bus"
29 #define MDIO_DRV_VERSION "1.3.0"
30 #define MDIO_COPYRIGHT "Copyright(c) 2015 Huawei Corporation."
31 #define MDIO_DRV_STRING MDIO_BUS_NAME
32 #define MDIO_DEFAULT_DEVICE_DESCR MDIO_BUS_NAME
33
34 #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
35 #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
36
37 #define MDIO_TIMEOUT 1000000
38
39 struct hns_mdio_device {
40 void *vbase; /* mdio reg base address */
41 struct regmap *subctrl_vbase;
42 };
43
44 /* mdio reg */
45 #define MDIO_COMMAND_REG 0x0
46 #define MDIO_ADDR_REG 0x4
47 #define MDIO_WDATA_REG 0x8
48 #define MDIO_RDATA_REG 0xc
49 #define MDIO_STA_REG 0x10
50
51 /* cfg phy bit map */
52 #define MDIO_CMD_DEVAD_M 0x1f
53 #define MDIO_CMD_DEVAD_S 0
54 #define MDIO_CMD_PRTAD_M 0x1f
55 #define MDIO_CMD_PRTAD_S 5
56 #define MDIO_CMD_OP_M 0x3
57 #define MDIO_CMD_OP_S 10
58 #define MDIO_CMD_ST_M 0x3
59 #define MDIO_CMD_ST_S 12
60 #define MDIO_CMD_START_B 14
61
62 #define MDIO_ADDR_DATA_M 0xffff
63 #define MDIO_ADDR_DATA_S 0
64
65 #define MDIO_WDATA_DATA_M 0xffff
66 #define MDIO_WDATA_DATA_S 0
67
68 #define MDIO_RDATA_DATA_M 0xffff
69 #define MDIO_RDATA_DATA_S 0
70
71 #define MDIO_STATE_STA_B 0
72
73 enum mdio_st_clause {
74 MDIO_ST_CLAUSE_45 = 0,
75 MDIO_ST_CLAUSE_22
76 };
77
78 enum mdio_c22_op_seq {
79 MDIO_C22_WRITE = 1,
80 MDIO_C22_READ = 2
81 };
82
83 enum mdio_c45_op_seq {
84 MDIO_C45_WRITE_ADDR = 0,
85 MDIO_C45_WRITE_DATA,
86 MDIO_C45_READ_INCREMENT,
87 MDIO_C45_READ
88 };
89
90 /* peri subctrl reg */
91 #define MDIO_SC_CLK_EN 0x338
92 #define MDIO_SC_CLK_DIS 0x33C
93 #define MDIO_SC_RESET_REQ 0xA38
94 #define MDIO_SC_RESET_DREQ 0xA3C
95 #define MDIO_SC_CTRL 0x2010
96 #define MDIO_SC_CLK_ST 0x531C
97 #define MDIO_SC_RESET_ST 0x5A1C
98
mdio_write_reg(void * base,u32 reg,u32 value)99 static void mdio_write_reg(void *base, u32 reg, u32 value)
100 {
101 u8 __iomem *reg_addr = (u8 __iomem *)base;
102
103 writel_relaxed(value, reg_addr + reg);
104 }
105
106 #define MDIO_WRITE_REG(a, reg, value) \
107 mdio_write_reg((a)->vbase, (reg), (value))
108
mdio_read_reg(void * base,u32 reg)109 static u32 mdio_read_reg(void *base, u32 reg)
110 {
111 u8 __iomem *reg_addr = (u8 __iomem *)base;
112
113 return readl_relaxed(reg_addr + reg);
114 }
115
116 #define mdio_set_field(origin, mask, shift, val) \
117 do { \
118 (origin) &= (~((mask) << (shift))); \
119 (origin) |= (((val) & (mask)) << (shift)); \
120 } while (0)
121
122 #define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))
123
mdio_set_reg_field(void * base,u32 reg,u32 mask,u32 shift,u32 val)124 static void mdio_set_reg_field(void *base, u32 reg, u32 mask, u32 shift,
125 u32 val)
126 {
127 u32 origin = mdio_read_reg(base, reg);
128
129 mdio_set_field(origin, mask, shift, val);
130 mdio_write_reg(base, reg, origin);
131 }
132
133 #define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
134 mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))
135
mdio_get_reg_field(void * base,u32 reg,u32 mask,u32 shift)136 static u32 mdio_get_reg_field(void *base, u32 reg, u32 mask, u32 shift)
137 {
138 u32 origin;
139
140 origin = mdio_read_reg(base, reg);
141 return mdio_get_field(origin, mask, shift);
142 }
143
144 #define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
145 mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))
146
147 #define MDIO_GET_REG_BIT(dev, reg, bit) \
148 mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))
149
150 #define MDIO_CHECK_SET_ST 1
151 #define MDIO_CHECK_CLR_ST 0
152
mdio_sc_cfg_reg_write(struct hns_mdio_device * mdio_dev,u32 cfg_reg,u32 set_val,u32 st_reg,u32 st_msk,u8 check_st)153 static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev,
154 u32 cfg_reg, u32 set_val,
155 u32 st_reg, u32 st_msk, u8 check_st)
156 {
157 u32 time_cnt;
158 u32 reg_value;
159 int ret;
160
161 regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);
162
163 for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) {
164 ret = regmap_read(mdio_dev->subctrl_vbase, st_reg, ®_value);
165 if (ret)
166 return ret;
167
168 reg_value &= st_msk;
169 if ((!!check_st) == (!!reg_value))
170 break;
171 }
172
173 if ((!!check_st) != (!!reg_value))
174 return -EBUSY;
175
176 return 0;
177 }
178
hns_mdio_wait_ready(struct mii_bus * bus)179 static int hns_mdio_wait_ready(struct mii_bus *bus)
180 {
181 struct hns_mdio_device *mdio_dev = bus->priv;
182 int i;
183 u32 cmd_reg_value = 1;
184
185 /* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
186 /* after that can do read or write*/
187 for (i = 0; cmd_reg_value; i++) {
188 cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev,
189 MDIO_COMMAND_REG,
190 MDIO_CMD_START_B);
191 if (i == MDIO_TIMEOUT)
192 return -ETIMEDOUT;
193 }
194
195 return 0;
196 }
197
hns_mdio_cmd_write(struct hns_mdio_device * mdio_dev,u8 is_c45,u8 op,u8 phy_id,u16 cmd)198 static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev,
199 u8 is_c45, u8 op, u8 phy_id, u16 cmd)
200 {
201 u32 cmd_reg_value;
202 u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22;
203
204 cmd_reg_value = st << MDIO_CMD_ST_S;
205 cmd_reg_value |= op << MDIO_CMD_OP_S;
206 cmd_reg_value |=
207 (phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S;
208 cmd_reg_value |= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S;
209 cmd_reg_value |= 1 << MDIO_CMD_START_B;
210
211 MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value);
212 }
213
214 /**
215 * hns_mdio_write - access phy register
216 * @bus: mdio bus
217 * @phy_id: phy id
218 * @regnum: register num
219 * @value: register value
220 *
221 * Return 0 on success, negative on failure
222 */
hns_mdio_write(struct mii_bus * bus,int phy_id,int regnum,u16 data)223 static int hns_mdio_write(struct mii_bus *bus,
224 int phy_id, int regnum, u16 data)
225 {
226 int ret;
227 struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
228 u8 devad = ((regnum >> 16) & 0x1f);
229 u8 is_c45 = !!(regnum & MII_ADDR_C45);
230 u16 reg = (u16)(regnum & 0xffff);
231 u8 op;
232 u16 cmd_reg_cfg;
233
234 dev_dbg(&bus->dev, "mdio write %s,base is %p\n",
235 bus->id, mdio_dev->vbase);
236 dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
237 phy_id, is_c45, devad, reg, data);
238
239 /* wait for ready */
240 ret = hns_mdio_wait_ready(bus);
241 if (ret) {
242 dev_err(&bus->dev, "MDIO bus is busy\n");
243 return ret;
244 }
245
246 if (!is_c45) {
247 cmd_reg_cfg = reg;
248 op = MDIO_C22_WRITE;
249 } else {
250 /* config the cmd-reg to write addr*/
251 MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
252 MDIO_ADDR_DATA_S, reg);
253
254 hns_mdio_cmd_write(mdio_dev, is_c45,
255 MDIO_C45_WRITE_ADDR, phy_id, devad);
256
257 /* check for read or write opt is finished */
258 ret = hns_mdio_wait_ready(bus);
259 if (ret) {
260 dev_err(&bus->dev, "MDIO bus is busy\n");
261 return ret;
262 }
263
264 /* config the data needed writing */
265 cmd_reg_cfg = devad;
266 op = MDIO_C45_WRITE_ADDR;
267 }
268
269 MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M,
270 MDIO_WDATA_DATA_S, data);
271
272 hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg);
273
274 return 0;
275 }
276
277 /**
278 * hns_mdio_read - access phy register
279 * @bus: mdio bus
280 * @phy_id: phy id
281 * @regnum: register num
282 * @value: register value
283 *
284 * Return phy register value
285 */
hns_mdio_read(struct mii_bus * bus,int phy_id,int regnum)286 static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
287 {
288 int ret;
289 u16 reg_val = 0;
290 u8 devad = ((regnum >> 16) & 0x1f);
291 u8 is_c45 = !!(regnum & MII_ADDR_C45);
292 u16 reg = (u16)(regnum & 0xffff);
293 struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
294
295 dev_dbg(&bus->dev, "mdio read %s,base is %p\n",
296 bus->id, mdio_dev->vbase);
297 dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
298 phy_id, is_c45, devad, reg);
299
300 /* Step 1: wait for ready */
301 ret = hns_mdio_wait_ready(bus);
302 if (ret) {
303 dev_err(&bus->dev, "MDIO bus is busy\n");
304 return ret;
305 }
306
307 if (!is_c45) {
308 hns_mdio_cmd_write(mdio_dev, is_c45,
309 MDIO_C22_READ, phy_id, reg);
310 } else {
311 MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
312 MDIO_ADDR_DATA_S, reg);
313
314 /* Step 2; config the cmd-reg to write addr*/
315 hns_mdio_cmd_write(mdio_dev, is_c45,
316 MDIO_C45_WRITE_ADDR, phy_id, devad);
317
318 /* Step 3: check for read or write opt is finished */
319 ret = hns_mdio_wait_ready(bus);
320 if (ret) {
321 dev_err(&bus->dev, "MDIO bus is busy\n");
322 return ret;
323 }
324
325 hns_mdio_cmd_write(mdio_dev, is_c45,
326 MDIO_C45_READ, phy_id, devad);
327 }
328
329 /* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
330 /* check for read or write opt is finished */
331 ret = hns_mdio_wait_ready(bus);
332 if (ret) {
333 dev_err(&bus->dev, "MDIO bus is busy\n");
334 return ret;
335 }
336
337 reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);
338 if (reg_val) {
339 dev_err(&bus->dev, " ERROR! MDIO Read failed!\n");
340 return -EBUSY;
341 }
342
343 /* Step 6; get out data*/
344 reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,
345 MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S);
346
347 return reg_val;
348 }
349
350 /**
351 * hns_mdio_reset - reset mdio bus
352 * @bus: mdio bus
353 *
354 * Return 0 on success, negative on failure
355 */
hns_mdio_reset(struct mii_bus * bus)356 static int hns_mdio_reset(struct mii_bus *bus)
357 {
358 struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
359 int ret;
360
361 if (!mdio_dev->subctrl_vbase) {
362 dev_err(&bus->dev, "mdio sys ctl reg has not maped\n");
363 return -ENODEV;
364 }
365
366 /*1. reset req, and read reset st check*/
367 ret = mdio_sc_cfg_reg_write(mdio_dev, MDIO_SC_RESET_REQ, 0x1,
368 MDIO_SC_RESET_ST, 0x1,
369 MDIO_CHECK_SET_ST);
370 if (ret) {
371 dev_err(&bus->dev, "MDIO reset fail\n");
372 return ret;
373 }
374
375 /*2. dis clk, and read clk st check*/
376 ret = mdio_sc_cfg_reg_write(mdio_dev, MDIO_SC_CLK_DIS,
377 0x1, MDIO_SC_CLK_ST, 0x1,
378 MDIO_CHECK_CLR_ST);
379 if (ret) {
380 dev_err(&bus->dev, "MDIO dis clk fail\n");
381 return ret;
382 }
383
384 /*3. reset dreq, and read reset st check*/
385 ret = mdio_sc_cfg_reg_write(mdio_dev, MDIO_SC_RESET_DREQ, 0x1,
386 MDIO_SC_RESET_ST, 0x1,
387 MDIO_CHECK_CLR_ST);
388 if (ret) {
389 dev_err(&bus->dev, "MDIO dis clk fail\n");
390 return ret;
391 }
392
393 /*4. en clk, and read clk st check*/
394 ret = mdio_sc_cfg_reg_write(mdio_dev, MDIO_SC_CLK_EN,
395 0x1, MDIO_SC_CLK_ST, 0x1,
396 MDIO_CHECK_SET_ST);
397 if (ret)
398 dev_err(&bus->dev, "MDIO en clk fail\n");
399
400 return ret;
401 }
402
403 /**
404 * hns_mdio_bus_name - get mdio bus name
405 * @name: mdio bus name
406 * @np: mdio device node pointer
407 */
hns_mdio_bus_name(char * name,struct device_node * np)408 static void hns_mdio_bus_name(char *name, struct device_node *np)
409 {
410 const u32 *addr;
411 u64 taddr = OF_BAD_ADDR;
412
413 addr = of_get_address(np, 0, NULL, NULL);
414 if (addr)
415 taddr = of_translate_address(np, addr);
416
417 snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
418 (unsigned long long)taddr);
419 }
420
421 /**
422 * hns_mdio_probe - probe mdio device
423 * @pdev: mdio platform device
424 *
425 * Return 0 on success, negative on failure
426 */
hns_mdio_probe(struct platform_device * pdev)427 static int hns_mdio_probe(struct platform_device *pdev)
428 {
429 struct device_node *np;
430 struct hns_mdio_device *mdio_dev;
431 struct mii_bus *new_bus;
432 struct resource *res;
433 int ret;
434
435 if (!pdev) {
436 dev_err(NULL, "pdev is NULL!\r\n");
437 return -ENODEV;
438 }
439 np = pdev->dev.of_node;
440 mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL);
441 if (!mdio_dev)
442 return -ENOMEM;
443
444 new_bus = devm_mdiobus_alloc(&pdev->dev);
445 if (!new_bus) {
446 dev_err(&pdev->dev, "mdiobus_alloc fail!\n");
447 return -ENOMEM;
448 }
449
450 new_bus->name = MDIO_BUS_NAME;
451 new_bus->read = hns_mdio_read;
452 new_bus->write = hns_mdio_write;
453 new_bus->reset = hns_mdio_reset;
454 new_bus->priv = mdio_dev;
455 hns_mdio_bus_name(new_bus->id, np);
456
457 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
458 mdio_dev->vbase = devm_ioremap_resource(&pdev->dev, res);
459 if (IS_ERR(mdio_dev->vbase)) {
460 ret = PTR_ERR(mdio_dev->vbase);
461 return ret;
462 }
463
464 mdio_dev->subctrl_vbase =
465 syscon_node_to_regmap(of_parse_phandle(np, "subctrl_vbase", 0));
466 if (IS_ERR(mdio_dev->subctrl_vbase)) {
467 dev_warn(&pdev->dev, "no syscon hisilicon,peri-c-subctrl\n");
468 mdio_dev->subctrl_vbase = NULL;
469 }
470 new_bus->irq = devm_kcalloc(&pdev->dev, PHY_MAX_ADDR,
471 sizeof(int), GFP_KERNEL);
472 if (!new_bus->irq)
473 return -ENOMEM;
474
475 new_bus->parent = &pdev->dev;
476 platform_set_drvdata(pdev, new_bus);
477
478 ret = of_mdiobus_register(new_bus, np);
479 if (ret) {
480 dev_err(&pdev->dev, "Cannot register as MDIO bus!\n");
481 platform_set_drvdata(pdev, NULL);
482 return ret;
483 }
484
485 return 0;
486 }
487
488 /**
489 * hns_mdio_remove - remove mdio device
490 * @pdev: mdio platform device
491 *
492 * Return 0 on success, negative on failure
493 */
hns_mdio_remove(struct platform_device * pdev)494 static int hns_mdio_remove(struct platform_device *pdev)
495 {
496 struct mii_bus *bus;
497
498 bus = platform_get_drvdata(pdev);
499
500 mdiobus_unregister(bus);
501 platform_set_drvdata(pdev, NULL);
502 return 0;
503 }
504
505 static const struct of_device_id hns_mdio_match[] = {
506 {.compatible = "hisilicon,mdio"},
507 {.compatible = "hisilicon,hns-mdio"},
508 {}
509 };
510
511 static struct platform_driver hns_mdio_driver = {
512 .probe = hns_mdio_probe,
513 .remove = hns_mdio_remove,
514 .driver = {
515 .name = MDIO_DRV_NAME,
516 .of_match_table = hns_mdio_match,
517 },
518 };
519
520 module_platform_driver(hns_mdio_driver);
521
522 MODULE_LICENSE("GPL");
523 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
524 MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
525 MODULE_ALIAS("platform:" MDIO_DRV_NAME);
526