1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 /* e1000_82575
25 * e1000_82576
26 */
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/types.h>
31 #include <linux/if_ether.h>
32 #include <linux/i2c.h>
33
34 #include "e1000_mac.h"
35 #include "e1000_82575.h"
36 #include "e1000_i210.h"
37
38 static s32 igb_get_invariants_82575(struct e1000_hw *);
39 static s32 igb_acquire_phy_82575(struct e1000_hw *);
40 static void igb_release_phy_82575(struct e1000_hw *);
41 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
42 static void igb_release_nvm_82575(struct e1000_hw *);
43 static s32 igb_check_for_link_82575(struct e1000_hw *);
44 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45 static s32 igb_init_hw_82575(struct e1000_hw *);
46 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
48 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
49 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
50 static s32 igb_reset_hw_82575(struct e1000_hw *);
51 static s32 igb_reset_hw_82580(struct e1000_hw *);
52 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
53 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
54 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
55 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
56 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
57 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
58 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
59 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
60 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
61 u16 *);
62 static s32 igb_get_phy_id_82575(struct e1000_hw *);
63 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
64 static bool igb_sgmii_active_82575(struct e1000_hw *);
65 static s32 igb_reset_init_script_82575(struct e1000_hw *);
66 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
67 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
68 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
69 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
70 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
71 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
72 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
73 static const u16 e1000_82580_rxpbs_table[] = {
74 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
75
76 /**
77 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
78 * @hw: pointer to the HW structure
79 *
80 * Called to determine if the I2C pins are being used for I2C or as an
81 * external MDIO interface since the two options are mutually exclusive.
82 **/
igb_sgmii_uses_mdio_82575(struct e1000_hw * hw)83 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
84 {
85 u32 reg = 0;
86 bool ext_mdio = false;
87
88 switch (hw->mac.type) {
89 case e1000_82575:
90 case e1000_82576:
91 reg = rd32(E1000_MDIC);
92 ext_mdio = !!(reg & E1000_MDIC_DEST);
93 break;
94 case e1000_82580:
95 case e1000_i350:
96 case e1000_i354:
97 case e1000_i210:
98 case e1000_i211:
99 reg = rd32(E1000_MDICNFG);
100 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
101 break;
102 default:
103 break;
104 }
105 return ext_mdio;
106 }
107
108 /**
109 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
110 * @hw: pointer to the HW structure
111 *
112 * Poll the M88E1112 interfaces to see which interface achieved link.
113 */
igb_check_for_link_media_swap(struct e1000_hw * hw)114 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
115 {
116 struct e1000_phy_info *phy = &hw->phy;
117 s32 ret_val;
118 u16 data;
119 u8 port = 0;
120
121 /* Check the copper medium. */
122 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
123 if (ret_val)
124 return ret_val;
125
126 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
127 if (ret_val)
128 return ret_val;
129
130 if (data & E1000_M88E1112_STATUS_LINK)
131 port = E1000_MEDIA_PORT_COPPER;
132
133 /* Check the other medium. */
134 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
135 if (ret_val)
136 return ret_val;
137
138 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
139 if (ret_val)
140 return ret_val;
141
142
143 if (data & E1000_M88E1112_STATUS_LINK)
144 port = E1000_MEDIA_PORT_OTHER;
145
146 /* Determine if a swap needs to happen. */
147 if (port && (hw->dev_spec._82575.media_port != port)) {
148 hw->dev_spec._82575.media_port = port;
149 hw->dev_spec._82575.media_changed = true;
150 }
151
152 if (port == E1000_MEDIA_PORT_COPPER) {
153 /* reset page to 0 */
154 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
155 if (ret_val)
156 return ret_val;
157 igb_check_for_link_82575(hw);
158 } else {
159 igb_check_for_link_82575(hw);
160 /* reset page to 0 */
161 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
162 if (ret_val)
163 return ret_val;
164 }
165
166 return 0;
167 }
168
169 /**
170 * igb_init_phy_params_82575 - Init PHY func ptrs.
171 * @hw: pointer to the HW structure
172 **/
igb_init_phy_params_82575(struct e1000_hw * hw)173 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
174 {
175 struct e1000_phy_info *phy = &hw->phy;
176 s32 ret_val = 0;
177 u32 ctrl_ext;
178
179 if (hw->phy.media_type != e1000_media_type_copper) {
180 phy->type = e1000_phy_none;
181 goto out;
182 }
183
184 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
185 phy->reset_delay_us = 100;
186
187 ctrl_ext = rd32(E1000_CTRL_EXT);
188
189 if (igb_sgmii_active_82575(hw)) {
190 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
191 ctrl_ext |= E1000_CTRL_I2C_ENA;
192 } else {
193 phy->ops.reset = igb_phy_hw_reset;
194 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
195 }
196
197 wr32(E1000_CTRL_EXT, ctrl_ext);
198 igb_reset_mdicnfg_82580(hw);
199
200 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
201 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
202 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
203 } else {
204 switch (hw->mac.type) {
205 case e1000_82580:
206 case e1000_i350:
207 case e1000_i354:
208 phy->ops.read_reg = igb_read_phy_reg_82580;
209 phy->ops.write_reg = igb_write_phy_reg_82580;
210 break;
211 case e1000_i210:
212 case e1000_i211:
213 phy->ops.read_reg = igb_read_phy_reg_gs40g;
214 phy->ops.write_reg = igb_write_phy_reg_gs40g;
215 break;
216 default:
217 phy->ops.read_reg = igb_read_phy_reg_igp;
218 phy->ops.write_reg = igb_write_phy_reg_igp;
219 }
220 }
221
222 /* set lan id */
223 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
224 E1000_STATUS_FUNC_SHIFT;
225
226 /* Set phy->phy_addr and phy->id. */
227 ret_val = igb_get_phy_id_82575(hw);
228 if (ret_val)
229 return ret_val;
230
231 /* Verify phy id and set remaining function pointers */
232 switch (phy->id) {
233 case M88E1543_E_PHY_ID:
234 case M88E1512_E_PHY_ID:
235 case I347AT4_E_PHY_ID:
236 case M88E1112_E_PHY_ID:
237 case M88E1111_I_PHY_ID:
238 phy->type = e1000_phy_m88;
239 phy->ops.check_polarity = igb_check_polarity_m88;
240 phy->ops.get_phy_info = igb_get_phy_info_m88;
241 if (phy->id != M88E1111_I_PHY_ID)
242 phy->ops.get_cable_length =
243 igb_get_cable_length_m88_gen2;
244 else
245 phy->ops.get_cable_length = igb_get_cable_length_m88;
246 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
247 /* Check if this PHY is configured for media swap. */
248 if (phy->id == M88E1112_E_PHY_ID) {
249 u16 data;
250
251 ret_val = phy->ops.write_reg(hw,
252 E1000_M88E1112_PAGE_ADDR,
253 2);
254 if (ret_val)
255 goto out;
256
257 ret_val = phy->ops.read_reg(hw,
258 E1000_M88E1112_MAC_CTRL_1,
259 &data);
260 if (ret_val)
261 goto out;
262
263 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
264 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
265 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
266 data == E1000_M88E1112_AUTO_COPPER_BASEX)
267 hw->mac.ops.check_for_link =
268 igb_check_for_link_media_swap;
269 }
270 if (phy->id == M88E1512_E_PHY_ID) {
271 ret_val = igb_initialize_M88E1512_phy(hw);
272 if (ret_val)
273 goto out;
274 }
275 break;
276 case IGP03E1000_E_PHY_ID:
277 phy->type = e1000_phy_igp_3;
278 phy->ops.get_phy_info = igb_get_phy_info_igp;
279 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
280 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
281 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
282 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
283 break;
284 case I82580_I_PHY_ID:
285 case I350_I_PHY_ID:
286 phy->type = e1000_phy_82580;
287 phy->ops.force_speed_duplex =
288 igb_phy_force_speed_duplex_82580;
289 phy->ops.get_cable_length = igb_get_cable_length_82580;
290 phy->ops.get_phy_info = igb_get_phy_info_82580;
291 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
292 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
293 break;
294 case I210_I_PHY_ID:
295 phy->type = e1000_phy_i210;
296 phy->ops.check_polarity = igb_check_polarity_m88;
297 phy->ops.get_cfg_done = igb_get_cfg_done_i210;
298 phy->ops.get_phy_info = igb_get_phy_info_m88;
299 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
300 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
301 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
302 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
303 break;
304 default:
305 ret_val = -E1000_ERR_PHY;
306 goto out;
307 }
308
309 out:
310 return ret_val;
311 }
312
313 /**
314 * igb_init_nvm_params_82575 - Init NVM func ptrs.
315 * @hw: pointer to the HW structure
316 **/
igb_init_nvm_params_82575(struct e1000_hw * hw)317 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
318 {
319 struct e1000_nvm_info *nvm = &hw->nvm;
320 u32 eecd = rd32(E1000_EECD);
321 u16 size;
322
323 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
324 E1000_EECD_SIZE_EX_SHIFT);
325
326 /* Added to a constant, "size" becomes the left-shift value
327 * for setting word_size.
328 */
329 size += NVM_WORD_SIZE_BASE_SHIFT;
330
331 /* Just in case size is out of range, cap it to the largest
332 * EEPROM size supported
333 */
334 if (size > 15)
335 size = 15;
336
337 nvm->word_size = 1 << size;
338 nvm->opcode_bits = 8;
339 nvm->delay_usec = 1;
340
341 switch (nvm->override) {
342 case e1000_nvm_override_spi_large:
343 nvm->page_size = 32;
344 nvm->address_bits = 16;
345 break;
346 case e1000_nvm_override_spi_small:
347 nvm->page_size = 8;
348 nvm->address_bits = 8;
349 break;
350 default:
351 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
352 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
353 16 : 8;
354 break;
355 }
356 if (nvm->word_size == (1 << 15))
357 nvm->page_size = 128;
358
359 nvm->type = e1000_nvm_eeprom_spi;
360
361 /* NVM Function Pointers */
362 nvm->ops.acquire = igb_acquire_nvm_82575;
363 nvm->ops.release = igb_release_nvm_82575;
364 nvm->ops.write = igb_write_nvm_spi;
365 nvm->ops.validate = igb_validate_nvm_checksum;
366 nvm->ops.update = igb_update_nvm_checksum;
367 if (nvm->word_size < (1 << 15))
368 nvm->ops.read = igb_read_nvm_eerd;
369 else
370 nvm->ops.read = igb_read_nvm_spi;
371
372 /* override generic family function pointers for specific descendants */
373 switch (hw->mac.type) {
374 case e1000_82580:
375 nvm->ops.validate = igb_validate_nvm_checksum_82580;
376 nvm->ops.update = igb_update_nvm_checksum_82580;
377 break;
378 case e1000_i354:
379 case e1000_i350:
380 nvm->ops.validate = igb_validate_nvm_checksum_i350;
381 nvm->ops.update = igb_update_nvm_checksum_i350;
382 break;
383 default:
384 break;
385 }
386
387 return 0;
388 }
389
390 /**
391 * igb_init_mac_params_82575 - Init MAC func ptrs.
392 * @hw: pointer to the HW structure
393 **/
igb_init_mac_params_82575(struct e1000_hw * hw)394 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
395 {
396 struct e1000_mac_info *mac = &hw->mac;
397 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
398
399 /* Set mta register count */
400 mac->mta_reg_count = 128;
401 /* Set rar entry count */
402 switch (mac->type) {
403 case e1000_82576:
404 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
405 break;
406 case e1000_82580:
407 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
408 break;
409 case e1000_i350:
410 case e1000_i354:
411 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
412 break;
413 default:
414 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
415 break;
416 }
417 /* reset */
418 if (mac->type >= e1000_82580)
419 mac->ops.reset_hw = igb_reset_hw_82580;
420 else
421 mac->ops.reset_hw = igb_reset_hw_82575;
422
423 if (mac->type >= e1000_i210) {
424 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
425 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
426
427 } else {
428 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
429 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
430 }
431
432 /* Set if part includes ASF firmware */
433 mac->asf_firmware_present = true;
434 /* Set if manageability features are enabled. */
435 mac->arc_subsystem_valid =
436 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
437 ? true : false;
438 /* enable EEE on i350 parts and later parts */
439 if (mac->type >= e1000_i350)
440 dev_spec->eee_disable = false;
441 else
442 dev_spec->eee_disable = true;
443 /* Allow a single clear of the SW semaphore on I210 and newer */
444 if (mac->type >= e1000_i210)
445 dev_spec->clear_semaphore_once = true;
446 /* physical interface link setup */
447 mac->ops.setup_physical_interface =
448 (hw->phy.media_type == e1000_media_type_copper)
449 ? igb_setup_copper_link_82575
450 : igb_setup_serdes_link_82575;
451
452 if (mac->type == e1000_82580) {
453 switch (hw->device_id) {
454 /* feature not supported on these id's */
455 case E1000_DEV_ID_DH89XXCC_SGMII:
456 case E1000_DEV_ID_DH89XXCC_SERDES:
457 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
458 case E1000_DEV_ID_DH89XXCC_SFP:
459 break;
460 default:
461 hw->dev_spec._82575.mas_capable = true;
462 break;
463 }
464 }
465 return 0;
466 }
467
468 /**
469 * igb_set_sfp_media_type_82575 - derives SFP module media type.
470 * @hw: pointer to the HW structure
471 *
472 * The media type is chosen based on SFP module.
473 * compatibility flags retrieved from SFP ID EEPROM.
474 **/
igb_set_sfp_media_type_82575(struct e1000_hw * hw)475 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
476 {
477 s32 ret_val = E1000_ERR_CONFIG;
478 u32 ctrl_ext = 0;
479 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
480 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
481 u8 tranceiver_type = 0;
482 s32 timeout = 3;
483
484 /* Turn I2C interface ON and power on sfp cage */
485 ctrl_ext = rd32(E1000_CTRL_EXT);
486 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
487 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
488
489 wrfl();
490
491 /* Read SFP module data */
492 while (timeout) {
493 ret_val = igb_read_sfp_data_byte(hw,
494 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
495 &tranceiver_type);
496 if (ret_val == 0)
497 break;
498 msleep(100);
499 timeout--;
500 }
501 if (ret_val != 0)
502 goto out;
503
504 ret_val = igb_read_sfp_data_byte(hw,
505 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
506 (u8 *)eth_flags);
507 if (ret_val != 0)
508 goto out;
509
510 /* Check if there is some SFP module plugged and powered */
511 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
512 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
513 dev_spec->module_plugged = true;
514 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
515 hw->phy.media_type = e1000_media_type_internal_serdes;
516 } else if (eth_flags->e100_base_fx) {
517 dev_spec->sgmii_active = true;
518 hw->phy.media_type = e1000_media_type_internal_serdes;
519 } else if (eth_flags->e1000_base_t) {
520 dev_spec->sgmii_active = true;
521 hw->phy.media_type = e1000_media_type_copper;
522 } else {
523 hw->phy.media_type = e1000_media_type_unknown;
524 hw_dbg("PHY module has not been recognized\n");
525 goto out;
526 }
527 } else {
528 hw->phy.media_type = e1000_media_type_unknown;
529 }
530 ret_val = 0;
531 out:
532 /* Restore I2C interface setting */
533 wr32(E1000_CTRL_EXT, ctrl_ext);
534 return ret_val;
535 }
536
igb_get_invariants_82575(struct e1000_hw * hw)537 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
538 {
539 struct e1000_mac_info *mac = &hw->mac;
540 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
541 s32 ret_val;
542 u32 ctrl_ext = 0;
543 u32 link_mode = 0;
544
545 switch (hw->device_id) {
546 case E1000_DEV_ID_82575EB_COPPER:
547 case E1000_DEV_ID_82575EB_FIBER_SERDES:
548 case E1000_DEV_ID_82575GB_QUAD_COPPER:
549 mac->type = e1000_82575;
550 break;
551 case E1000_DEV_ID_82576:
552 case E1000_DEV_ID_82576_NS:
553 case E1000_DEV_ID_82576_NS_SERDES:
554 case E1000_DEV_ID_82576_FIBER:
555 case E1000_DEV_ID_82576_SERDES:
556 case E1000_DEV_ID_82576_QUAD_COPPER:
557 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
558 case E1000_DEV_ID_82576_SERDES_QUAD:
559 mac->type = e1000_82576;
560 break;
561 case E1000_DEV_ID_82580_COPPER:
562 case E1000_DEV_ID_82580_FIBER:
563 case E1000_DEV_ID_82580_QUAD_FIBER:
564 case E1000_DEV_ID_82580_SERDES:
565 case E1000_DEV_ID_82580_SGMII:
566 case E1000_DEV_ID_82580_COPPER_DUAL:
567 case E1000_DEV_ID_DH89XXCC_SGMII:
568 case E1000_DEV_ID_DH89XXCC_SERDES:
569 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
570 case E1000_DEV_ID_DH89XXCC_SFP:
571 mac->type = e1000_82580;
572 break;
573 case E1000_DEV_ID_I350_COPPER:
574 case E1000_DEV_ID_I350_FIBER:
575 case E1000_DEV_ID_I350_SERDES:
576 case E1000_DEV_ID_I350_SGMII:
577 mac->type = e1000_i350;
578 break;
579 case E1000_DEV_ID_I210_COPPER:
580 case E1000_DEV_ID_I210_FIBER:
581 case E1000_DEV_ID_I210_SERDES:
582 case E1000_DEV_ID_I210_SGMII:
583 case E1000_DEV_ID_I210_COPPER_FLASHLESS:
584 case E1000_DEV_ID_I210_SERDES_FLASHLESS:
585 mac->type = e1000_i210;
586 break;
587 case E1000_DEV_ID_I211_COPPER:
588 mac->type = e1000_i211;
589 break;
590 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
591 case E1000_DEV_ID_I354_SGMII:
592 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
593 mac->type = e1000_i354;
594 break;
595 default:
596 return -E1000_ERR_MAC_INIT;
597 }
598
599 /* Set media type */
600 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
601 * based on the EEPROM. We cannot rely upon device ID. There
602 * is no distinguishable difference between fiber and internal
603 * SerDes mode on the 82575. There can be an external PHY attached
604 * on the SGMII interface. For this, we'll set sgmii_active to true.
605 */
606 hw->phy.media_type = e1000_media_type_copper;
607 dev_spec->sgmii_active = false;
608 dev_spec->module_plugged = false;
609
610 ctrl_ext = rd32(E1000_CTRL_EXT);
611
612 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
613 switch (link_mode) {
614 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
615 hw->phy.media_type = e1000_media_type_internal_serdes;
616 break;
617 case E1000_CTRL_EXT_LINK_MODE_SGMII:
618 /* Get phy control interface type set (MDIO vs. I2C)*/
619 if (igb_sgmii_uses_mdio_82575(hw)) {
620 hw->phy.media_type = e1000_media_type_copper;
621 dev_spec->sgmii_active = true;
622 break;
623 }
624 /* fall through for I2C based SGMII */
625 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
626 /* read media type from SFP EEPROM */
627 ret_val = igb_set_sfp_media_type_82575(hw);
628 if ((ret_val != 0) ||
629 (hw->phy.media_type == e1000_media_type_unknown)) {
630 /* If media type was not identified then return media
631 * type defined by the CTRL_EXT settings.
632 */
633 hw->phy.media_type = e1000_media_type_internal_serdes;
634
635 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
636 hw->phy.media_type = e1000_media_type_copper;
637 dev_spec->sgmii_active = true;
638 }
639
640 break;
641 }
642
643 /* do not change link mode for 100BaseFX */
644 if (dev_spec->eth_flags.e100_base_fx)
645 break;
646
647 /* change current link mode setting */
648 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
649
650 if (hw->phy.media_type == e1000_media_type_copper)
651 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
652 else
653 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
654
655 wr32(E1000_CTRL_EXT, ctrl_ext);
656
657 break;
658 default:
659 break;
660 }
661
662 /* mac initialization and operations */
663 ret_val = igb_init_mac_params_82575(hw);
664 if (ret_val)
665 goto out;
666
667 /* NVM initialization */
668 ret_val = igb_init_nvm_params_82575(hw);
669 switch (hw->mac.type) {
670 case e1000_i210:
671 case e1000_i211:
672 ret_val = igb_init_nvm_params_i210(hw);
673 break;
674 default:
675 break;
676 }
677
678 if (ret_val)
679 goto out;
680
681 /* if part supports SR-IOV then initialize mailbox parameters */
682 switch (mac->type) {
683 case e1000_82576:
684 case e1000_i350:
685 igb_init_mbx_params_pf(hw);
686 break;
687 default:
688 break;
689 }
690
691 /* setup PHY parameters */
692 ret_val = igb_init_phy_params_82575(hw);
693
694 out:
695 return ret_val;
696 }
697
698 /**
699 * igb_acquire_phy_82575 - Acquire rights to access PHY
700 * @hw: pointer to the HW structure
701 *
702 * Acquire access rights to the correct PHY. This is a
703 * function pointer entry point called by the api module.
704 **/
igb_acquire_phy_82575(struct e1000_hw * hw)705 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
706 {
707 u16 mask = E1000_SWFW_PHY0_SM;
708
709 if (hw->bus.func == E1000_FUNC_1)
710 mask = E1000_SWFW_PHY1_SM;
711 else if (hw->bus.func == E1000_FUNC_2)
712 mask = E1000_SWFW_PHY2_SM;
713 else if (hw->bus.func == E1000_FUNC_3)
714 mask = E1000_SWFW_PHY3_SM;
715
716 return hw->mac.ops.acquire_swfw_sync(hw, mask);
717 }
718
719 /**
720 * igb_release_phy_82575 - Release rights to access PHY
721 * @hw: pointer to the HW structure
722 *
723 * A wrapper to release access rights to the correct PHY. This is a
724 * function pointer entry point called by the api module.
725 **/
igb_release_phy_82575(struct e1000_hw * hw)726 static void igb_release_phy_82575(struct e1000_hw *hw)
727 {
728 u16 mask = E1000_SWFW_PHY0_SM;
729
730 if (hw->bus.func == E1000_FUNC_1)
731 mask = E1000_SWFW_PHY1_SM;
732 else if (hw->bus.func == E1000_FUNC_2)
733 mask = E1000_SWFW_PHY2_SM;
734 else if (hw->bus.func == E1000_FUNC_3)
735 mask = E1000_SWFW_PHY3_SM;
736
737 hw->mac.ops.release_swfw_sync(hw, mask);
738 }
739
740 /**
741 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
742 * @hw: pointer to the HW structure
743 * @offset: register offset to be read
744 * @data: pointer to the read data
745 *
746 * Reads the PHY register at offset using the serial gigabit media independent
747 * interface and stores the retrieved information in data.
748 **/
igb_read_phy_reg_sgmii_82575(struct e1000_hw * hw,u32 offset,u16 * data)749 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
750 u16 *data)
751 {
752 s32 ret_val = -E1000_ERR_PARAM;
753
754 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
755 hw_dbg("PHY Address %u is out of range\n", offset);
756 goto out;
757 }
758
759 ret_val = hw->phy.ops.acquire(hw);
760 if (ret_val)
761 goto out;
762
763 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
764
765 hw->phy.ops.release(hw);
766
767 out:
768 return ret_val;
769 }
770
771 /**
772 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
773 * @hw: pointer to the HW structure
774 * @offset: register offset to write to
775 * @data: data to write at register offset
776 *
777 * Writes the data to PHY register at the offset using the serial gigabit
778 * media independent interface.
779 **/
igb_write_phy_reg_sgmii_82575(struct e1000_hw * hw,u32 offset,u16 data)780 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
781 u16 data)
782 {
783 s32 ret_val = -E1000_ERR_PARAM;
784
785
786 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
787 hw_dbg("PHY Address %d is out of range\n", offset);
788 goto out;
789 }
790
791 ret_val = hw->phy.ops.acquire(hw);
792 if (ret_val)
793 goto out;
794
795 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
796
797 hw->phy.ops.release(hw);
798
799 out:
800 return ret_val;
801 }
802
803 /**
804 * igb_get_phy_id_82575 - Retrieve PHY addr and id
805 * @hw: pointer to the HW structure
806 *
807 * Retrieves the PHY address and ID for both PHY's which do and do not use
808 * sgmi interface.
809 **/
igb_get_phy_id_82575(struct e1000_hw * hw)810 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
811 {
812 struct e1000_phy_info *phy = &hw->phy;
813 s32 ret_val = 0;
814 u16 phy_id;
815 u32 ctrl_ext;
816 u32 mdic;
817
818 /* Extra read required for some PHY's on i354 */
819 if (hw->mac.type == e1000_i354)
820 igb_get_phy_id(hw);
821
822 /* For SGMII PHYs, we try the list of possible addresses until
823 * we find one that works. For non-SGMII PHYs
824 * (e.g. integrated copper PHYs), an address of 1 should
825 * work. The result of this function should mean phy->phy_addr
826 * and phy->id are set correctly.
827 */
828 if (!(igb_sgmii_active_82575(hw))) {
829 phy->addr = 1;
830 ret_val = igb_get_phy_id(hw);
831 goto out;
832 }
833
834 if (igb_sgmii_uses_mdio_82575(hw)) {
835 switch (hw->mac.type) {
836 case e1000_82575:
837 case e1000_82576:
838 mdic = rd32(E1000_MDIC);
839 mdic &= E1000_MDIC_PHY_MASK;
840 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
841 break;
842 case e1000_82580:
843 case e1000_i350:
844 case e1000_i354:
845 case e1000_i210:
846 case e1000_i211:
847 mdic = rd32(E1000_MDICNFG);
848 mdic &= E1000_MDICNFG_PHY_MASK;
849 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
850 break;
851 default:
852 ret_val = -E1000_ERR_PHY;
853 goto out;
854 }
855 ret_val = igb_get_phy_id(hw);
856 goto out;
857 }
858
859 /* Power on sgmii phy if it is disabled */
860 ctrl_ext = rd32(E1000_CTRL_EXT);
861 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
862 wrfl();
863 msleep(300);
864
865 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
866 * Therefore, we need to test 1-7
867 */
868 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
869 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
870 if (ret_val == 0) {
871 hw_dbg("Vendor ID 0x%08X read at address %u\n",
872 phy_id, phy->addr);
873 /* At the time of this writing, The M88 part is
874 * the only supported SGMII PHY product.
875 */
876 if (phy_id == M88_VENDOR)
877 break;
878 } else {
879 hw_dbg("PHY address %u was unreadable\n", phy->addr);
880 }
881 }
882
883 /* A valid PHY type couldn't be found. */
884 if (phy->addr == 8) {
885 phy->addr = 0;
886 ret_val = -E1000_ERR_PHY;
887 goto out;
888 } else {
889 ret_val = igb_get_phy_id(hw);
890 }
891
892 /* restore previous sfp cage power state */
893 wr32(E1000_CTRL_EXT, ctrl_ext);
894
895 out:
896 return ret_val;
897 }
898
899 /**
900 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
901 * @hw: pointer to the HW structure
902 *
903 * Resets the PHY using the serial gigabit media independent interface.
904 **/
igb_phy_hw_reset_sgmii_82575(struct e1000_hw * hw)905 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
906 {
907 struct e1000_phy_info *phy = &hw->phy;
908 s32 ret_val;
909
910 /* This isn't a true "hard" reset, but is the only reset
911 * available to us at this time.
912 */
913
914 hw_dbg("Soft resetting SGMII attached PHY...\n");
915
916 /* SFP documentation requires the following to configure the SPF module
917 * to work on SGMII. No further documentation is given.
918 */
919 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
920 if (ret_val)
921 goto out;
922
923 ret_val = igb_phy_sw_reset(hw);
924 if (ret_val)
925 goto out;
926
927 if (phy->id == M88E1512_E_PHY_ID)
928 ret_val = igb_initialize_M88E1512_phy(hw);
929 out:
930 return ret_val;
931 }
932
933 /**
934 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
935 * @hw: pointer to the HW structure
936 * @active: true to enable LPLU, false to disable
937 *
938 * Sets the LPLU D0 state according to the active flag. When
939 * activating LPLU this function also disables smart speed
940 * and vice versa. LPLU will not be activated unless the
941 * device autonegotiation advertisement meets standards of
942 * either 10 or 10/100 or 10/100/1000 at all duplexes.
943 * This is a function pointer entry point only called by
944 * PHY setup routines.
945 **/
igb_set_d0_lplu_state_82575(struct e1000_hw * hw,bool active)946 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
947 {
948 struct e1000_phy_info *phy = &hw->phy;
949 s32 ret_val;
950 u16 data;
951
952 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
953 if (ret_val)
954 goto out;
955
956 if (active) {
957 data |= IGP02E1000_PM_D0_LPLU;
958 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
959 data);
960 if (ret_val)
961 goto out;
962
963 /* When LPLU is enabled, we should disable SmartSpeed */
964 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
965 &data);
966 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
967 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
968 data);
969 if (ret_val)
970 goto out;
971 } else {
972 data &= ~IGP02E1000_PM_D0_LPLU;
973 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
974 data);
975 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
976 * during Dx states where the power conservation is most
977 * important. During driver activity we should enable
978 * SmartSpeed, so performance is maintained.
979 */
980 if (phy->smart_speed == e1000_smart_speed_on) {
981 ret_val = phy->ops.read_reg(hw,
982 IGP01E1000_PHY_PORT_CONFIG, &data);
983 if (ret_val)
984 goto out;
985
986 data |= IGP01E1000_PSCFR_SMART_SPEED;
987 ret_val = phy->ops.write_reg(hw,
988 IGP01E1000_PHY_PORT_CONFIG, data);
989 if (ret_val)
990 goto out;
991 } else if (phy->smart_speed == e1000_smart_speed_off) {
992 ret_val = phy->ops.read_reg(hw,
993 IGP01E1000_PHY_PORT_CONFIG, &data);
994 if (ret_val)
995 goto out;
996
997 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
998 ret_val = phy->ops.write_reg(hw,
999 IGP01E1000_PHY_PORT_CONFIG, data);
1000 if (ret_val)
1001 goto out;
1002 }
1003 }
1004
1005 out:
1006 return ret_val;
1007 }
1008
1009 /**
1010 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
1011 * @hw: pointer to the HW structure
1012 * @active: true to enable LPLU, false to disable
1013 *
1014 * Sets the LPLU D0 state according to the active flag. When
1015 * activating LPLU this function also disables smart speed
1016 * and vice versa. LPLU will not be activated unless the
1017 * device autonegotiation advertisement meets standards of
1018 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1019 * This is a function pointer entry point only called by
1020 * PHY setup routines.
1021 **/
igb_set_d0_lplu_state_82580(struct e1000_hw * hw,bool active)1022 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1023 {
1024 struct e1000_phy_info *phy = &hw->phy;
1025 u16 data;
1026
1027 data = rd32(E1000_82580_PHY_POWER_MGMT);
1028
1029 if (active) {
1030 data |= E1000_82580_PM_D0_LPLU;
1031
1032 /* When LPLU is enabled, we should disable SmartSpeed */
1033 data &= ~E1000_82580_PM_SPD;
1034 } else {
1035 data &= ~E1000_82580_PM_D0_LPLU;
1036
1037 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1038 * during Dx states where the power conservation is most
1039 * important. During driver activity we should enable
1040 * SmartSpeed, so performance is maintained.
1041 */
1042 if (phy->smart_speed == e1000_smart_speed_on)
1043 data |= E1000_82580_PM_SPD;
1044 else if (phy->smart_speed == e1000_smart_speed_off)
1045 data &= ~E1000_82580_PM_SPD; }
1046
1047 wr32(E1000_82580_PHY_POWER_MGMT, data);
1048 return 0;
1049 }
1050
1051 /**
1052 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1053 * @hw: pointer to the HW structure
1054 * @active: boolean used to enable/disable lplu
1055 *
1056 * Success returns 0, Failure returns 1
1057 *
1058 * The low power link up (lplu) state is set to the power management level D3
1059 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1060 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1061 * is used during Dx states where the power conservation is most important.
1062 * During driver activity, SmartSpeed should be enabled so performance is
1063 * maintained.
1064 **/
igb_set_d3_lplu_state_82580(struct e1000_hw * hw,bool active)1065 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1066 {
1067 struct e1000_phy_info *phy = &hw->phy;
1068 u16 data;
1069
1070 data = rd32(E1000_82580_PHY_POWER_MGMT);
1071
1072 if (!active) {
1073 data &= ~E1000_82580_PM_D3_LPLU;
1074 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1075 * during Dx states where the power conservation is most
1076 * important. During driver activity we should enable
1077 * SmartSpeed, so performance is maintained.
1078 */
1079 if (phy->smart_speed == e1000_smart_speed_on)
1080 data |= E1000_82580_PM_SPD;
1081 else if (phy->smart_speed == e1000_smart_speed_off)
1082 data &= ~E1000_82580_PM_SPD;
1083 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1084 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1085 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1086 data |= E1000_82580_PM_D3_LPLU;
1087 /* When LPLU is enabled, we should disable SmartSpeed */
1088 data &= ~E1000_82580_PM_SPD;
1089 }
1090
1091 wr32(E1000_82580_PHY_POWER_MGMT, data);
1092 return 0;
1093 }
1094
1095 /**
1096 * igb_acquire_nvm_82575 - Request for access to EEPROM
1097 * @hw: pointer to the HW structure
1098 *
1099 * Acquire the necessary semaphores for exclusive access to the EEPROM.
1100 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1101 * Return successful if access grant bit set, else clear the request for
1102 * EEPROM access and return -E1000_ERR_NVM (-1).
1103 **/
igb_acquire_nvm_82575(struct e1000_hw * hw)1104 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1105 {
1106 s32 ret_val;
1107
1108 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1109 if (ret_val)
1110 goto out;
1111
1112 ret_val = igb_acquire_nvm(hw);
1113
1114 if (ret_val)
1115 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1116
1117 out:
1118 return ret_val;
1119 }
1120
1121 /**
1122 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1123 * @hw: pointer to the HW structure
1124 *
1125 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1126 * then release the semaphores acquired.
1127 **/
igb_release_nvm_82575(struct e1000_hw * hw)1128 static void igb_release_nvm_82575(struct e1000_hw *hw)
1129 {
1130 igb_release_nvm(hw);
1131 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1132 }
1133
1134 /**
1135 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1136 * @hw: pointer to the HW structure
1137 * @mask: specifies which semaphore to acquire
1138 *
1139 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1140 * will also specify which port we're acquiring the lock for.
1141 **/
igb_acquire_swfw_sync_82575(struct e1000_hw * hw,u16 mask)1142 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1143 {
1144 u32 swfw_sync;
1145 u32 swmask = mask;
1146 u32 fwmask = mask << 16;
1147 s32 ret_val = 0;
1148 s32 i = 0, timeout = 200;
1149
1150 while (i < timeout) {
1151 if (igb_get_hw_semaphore(hw)) {
1152 ret_val = -E1000_ERR_SWFW_SYNC;
1153 goto out;
1154 }
1155
1156 swfw_sync = rd32(E1000_SW_FW_SYNC);
1157 if (!(swfw_sync & (fwmask | swmask)))
1158 break;
1159
1160 /* Firmware currently using resource (fwmask)
1161 * or other software thread using resource (swmask)
1162 */
1163 igb_put_hw_semaphore(hw);
1164 mdelay(5);
1165 i++;
1166 }
1167
1168 if (i == timeout) {
1169 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1170 ret_val = -E1000_ERR_SWFW_SYNC;
1171 goto out;
1172 }
1173
1174 swfw_sync |= swmask;
1175 wr32(E1000_SW_FW_SYNC, swfw_sync);
1176
1177 igb_put_hw_semaphore(hw);
1178
1179 out:
1180 return ret_val;
1181 }
1182
1183 /**
1184 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1185 * @hw: pointer to the HW structure
1186 * @mask: specifies which semaphore to acquire
1187 *
1188 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1189 * will also specify which port we're releasing the lock for.
1190 **/
igb_release_swfw_sync_82575(struct e1000_hw * hw,u16 mask)1191 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1192 {
1193 u32 swfw_sync;
1194
1195 while (igb_get_hw_semaphore(hw) != 0)
1196 ; /* Empty */
1197
1198 swfw_sync = rd32(E1000_SW_FW_SYNC);
1199 swfw_sync &= ~mask;
1200 wr32(E1000_SW_FW_SYNC, swfw_sync);
1201
1202 igb_put_hw_semaphore(hw);
1203 }
1204
1205 /**
1206 * igb_get_cfg_done_82575 - Read config done bit
1207 * @hw: pointer to the HW structure
1208 *
1209 * Read the management control register for the config done bit for
1210 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1211 * to read the config done bit, so an error is *ONLY* logged and returns
1212 * 0. If we were to return with error, EEPROM-less silicon
1213 * would not be able to be reset or change link.
1214 **/
igb_get_cfg_done_82575(struct e1000_hw * hw)1215 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1216 {
1217 s32 timeout = PHY_CFG_TIMEOUT;
1218 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1219
1220 if (hw->bus.func == 1)
1221 mask = E1000_NVM_CFG_DONE_PORT_1;
1222 else if (hw->bus.func == E1000_FUNC_2)
1223 mask = E1000_NVM_CFG_DONE_PORT_2;
1224 else if (hw->bus.func == E1000_FUNC_3)
1225 mask = E1000_NVM_CFG_DONE_PORT_3;
1226
1227 while (timeout) {
1228 if (rd32(E1000_EEMNGCTL) & mask)
1229 break;
1230 usleep_range(1000, 2000);
1231 timeout--;
1232 }
1233 if (!timeout)
1234 hw_dbg("MNG configuration cycle has not completed.\n");
1235
1236 /* If EEPROM is not marked present, init the PHY manually */
1237 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1238 (hw->phy.type == e1000_phy_igp_3))
1239 igb_phy_init_script_igp3(hw);
1240
1241 return 0;
1242 }
1243
1244 /**
1245 * igb_get_link_up_info_82575 - Get link speed/duplex info
1246 * @hw: pointer to the HW structure
1247 * @speed: stores the current speed
1248 * @duplex: stores the current duplex
1249 *
1250 * This is a wrapper function, if using the serial gigabit media independent
1251 * interface, use PCS to retrieve the link speed and duplex information.
1252 * Otherwise, use the generic function to get the link speed and duplex info.
1253 **/
igb_get_link_up_info_82575(struct e1000_hw * hw,u16 * speed,u16 * duplex)1254 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1255 u16 *duplex)
1256 {
1257 s32 ret_val;
1258
1259 if (hw->phy.media_type != e1000_media_type_copper)
1260 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1261 duplex);
1262 else
1263 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1264 duplex);
1265
1266 return ret_val;
1267 }
1268
1269 /**
1270 * igb_check_for_link_82575 - Check for link
1271 * @hw: pointer to the HW structure
1272 *
1273 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1274 * use the generic interface for determining link.
1275 **/
igb_check_for_link_82575(struct e1000_hw * hw)1276 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1277 {
1278 s32 ret_val;
1279 u16 speed, duplex;
1280
1281 if (hw->phy.media_type != e1000_media_type_copper) {
1282 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1283 &duplex);
1284 /* Use this flag to determine if link needs to be checked or
1285 * not. If we have link clear the flag so that we do not
1286 * continue to check for link.
1287 */
1288 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1289
1290 /* Configure Flow Control now that Auto-Neg has completed.
1291 * First, we need to restore the desired flow control
1292 * settings because we may have had to re-autoneg with a
1293 * different link partner.
1294 */
1295 ret_val = igb_config_fc_after_link_up(hw);
1296 if (ret_val)
1297 hw_dbg("Error configuring flow control\n");
1298 } else {
1299 ret_val = igb_check_for_copper_link(hw);
1300 }
1301
1302 return ret_val;
1303 }
1304
1305 /**
1306 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1307 * @hw: pointer to the HW structure
1308 **/
igb_power_up_serdes_link_82575(struct e1000_hw * hw)1309 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1310 {
1311 u32 reg;
1312
1313
1314 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1315 !igb_sgmii_active_82575(hw))
1316 return;
1317
1318 /* Enable PCS to turn on link */
1319 reg = rd32(E1000_PCS_CFG0);
1320 reg |= E1000_PCS_CFG_PCS_EN;
1321 wr32(E1000_PCS_CFG0, reg);
1322
1323 /* Power up the laser */
1324 reg = rd32(E1000_CTRL_EXT);
1325 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1326 wr32(E1000_CTRL_EXT, reg);
1327
1328 /* flush the write to verify completion */
1329 wrfl();
1330 usleep_range(1000, 2000);
1331 }
1332
1333 /**
1334 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1335 * @hw: pointer to the HW structure
1336 * @speed: stores the current speed
1337 * @duplex: stores the current duplex
1338 *
1339 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1340 * duplex, then store the values in the pointers provided.
1341 **/
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw * hw,u16 * speed,u16 * duplex)1342 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1343 u16 *duplex)
1344 {
1345 struct e1000_mac_info *mac = &hw->mac;
1346 u32 pcs, status;
1347
1348 /* Set up defaults for the return values of this function */
1349 mac->serdes_has_link = false;
1350 *speed = 0;
1351 *duplex = 0;
1352
1353 /* Read the PCS Status register for link state. For non-copper mode,
1354 * the status register is not accurate. The PCS status register is
1355 * used instead.
1356 */
1357 pcs = rd32(E1000_PCS_LSTAT);
1358
1359 /* The link up bit determines when link is up on autoneg. The sync ok
1360 * gets set once both sides sync up and agree upon link. Stable link
1361 * can be determined by checking for both link up and link sync ok
1362 */
1363 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1364 mac->serdes_has_link = true;
1365
1366 /* Detect and store PCS speed */
1367 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1368 *speed = SPEED_1000;
1369 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1370 *speed = SPEED_100;
1371 else
1372 *speed = SPEED_10;
1373
1374 /* Detect and store PCS duplex */
1375 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1376 *duplex = FULL_DUPLEX;
1377 else
1378 *duplex = HALF_DUPLEX;
1379
1380 /* Check if it is an I354 2.5Gb backplane connection. */
1381 if (mac->type == e1000_i354) {
1382 status = rd32(E1000_STATUS);
1383 if ((status & E1000_STATUS_2P5_SKU) &&
1384 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1385 *speed = SPEED_2500;
1386 *duplex = FULL_DUPLEX;
1387 hw_dbg("2500 Mbs, ");
1388 hw_dbg("Full Duplex\n");
1389 }
1390 }
1391
1392 }
1393
1394 return 0;
1395 }
1396
1397 /**
1398 * igb_shutdown_serdes_link_82575 - Remove link during power down
1399 * @hw: pointer to the HW structure
1400 *
1401 * In the case of fiber serdes, shut down optics and PCS on driver unload
1402 * when management pass thru is not enabled.
1403 **/
igb_shutdown_serdes_link_82575(struct e1000_hw * hw)1404 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1405 {
1406 u32 reg;
1407
1408 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1409 igb_sgmii_active_82575(hw))
1410 return;
1411
1412 if (!igb_enable_mng_pass_thru(hw)) {
1413 /* Disable PCS to turn off link */
1414 reg = rd32(E1000_PCS_CFG0);
1415 reg &= ~E1000_PCS_CFG_PCS_EN;
1416 wr32(E1000_PCS_CFG0, reg);
1417
1418 /* shutdown the laser */
1419 reg = rd32(E1000_CTRL_EXT);
1420 reg |= E1000_CTRL_EXT_SDP3_DATA;
1421 wr32(E1000_CTRL_EXT, reg);
1422
1423 /* flush the write to verify completion */
1424 wrfl();
1425 usleep_range(1000, 2000);
1426 }
1427 }
1428
1429 /**
1430 * igb_reset_hw_82575 - Reset hardware
1431 * @hw: pointer to the HW structure
1432 *
1433 * This resets the hardware into a known state. This is a
1434 * function pointer entry point called by the api module.
1435 **/
igb_reset_hw_82575(struct e1000_hw * hw)1436 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1437 {
1438 u32 ctrl;
1439 s32 ret_val;
1440
1441 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1442 * on the last TLP read/write transaction when MAC is reset.
1443 */
1444 ret_val = igb_disable_pcie_master(hw);
1445 if (ret_val)
1446 hw_dbg("PCI-E Master disable polling has failed.\n");
1447
1448 /* set the completion timeout for interface */
1449 ret_val = igb_set_pcie_completion_timeout(hw);
1450 if (ret_val)
1451 hw_dbg("PCI-E Set completion timeout has failed.\n");
1452
1453 hw_dbg("Masking off all interrupts\n");
1454 wr32(E1000_IMC, 0xffffffff);
1455
1456 wr32(E1000_RCTL, 0);
1457 wr32(E1000_TCTL, E1000_TCTL_PSP);
1458 wrfl();
1459
1460 usleep_range(10000, 20000);
1461
1462 ctrl = rd32(E1000_CTRL);
1463
1464 hw_dbg("Issuing a global reset to MAC\n");
1465 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1466
1467 ret_val = igb_get_auto_rd_done(hw);
1468 if (ret_val) {
1469 /* When auto config read does not complete, do not
1470 * return with an error. This can happen in situations
1471 * where there is no eeprom and prevents getting link.
1472 */
1473 hw_dbg("Auto Read Done did not complete\n");
1474 }
1475
1476 /* If EEPROM is not present, run manual init scripts */
1477 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1478 igb_reset_init_script_82575(hw);
1479
1480 /* Clear any pending interrupt events. */
1481 wr32(E1000_IMC, 0xffffffff);
1482 rd32(E1000_ICR);
1483
1484 /* Install any alternate MAC address into RAR0 */
1485 ret_val = igb_check_alt_mac_addr(hw);
1486
1487 return ret_val;
1488 }
1489
1490 /**
1491 * igb_init_hw_82575 - Initialize hardware
1492 * @hw: pointer to the HW structure
1493 *
1494 * This inits the hardware readying it for operation.
1495 **/
igb_init_hw_82575(struct e1000_hw * hw)1496 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1497 {
1498 struct e1000_mac_info *mac = &hw->mac;
1499 s32 ret_val;
1500 u16 i, rar_count = mac->rar_entry_count;
1501
1502 if ((hw->mac.type >= e1000_i210) &&
1503 !(igb_get_flash_presence_i210(hw))) {
1504 ret_val = igb_pll_workaround_i210(hw);
1505 if (ret_val)
1506 return ret_val;
1507 }
1508
1509 /* Initialize identification LED */
1510 ret_val = igb_id_led_init(hw);
1511 if (ret_val) {
1512 hw_dbg("Error initializing identification LED\n");
1513 /* This is not fatal and we should not stop init due to this */
1514 }
1515
1516 /* Disabling VLAN filtering */
1517 hw_dbg("Initializing the IEEE VLAN\n");
1518 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1519 igb_clear_vfta_i350(hw);
1520 else
1521 igb_clear_vfta(hw);
1522
1523 /* Setup the receive address */
1524 igb_init_rx_addrs(hw, rar_count);
1525
1526 /* Zero out the Multicast HASH table */
1527 hw_dbg("Zeroing the MTA\n");
1528 for (i = 0; i < mac->mta_reg_count; i++)
1529 array_wr32(E1000_MTA, i, 0);
1530
1531 /* Zero out the Unicast HASH table */
1532 hw_dbg("Zeroing the UTA\n");
1533 for (i = 0; i < mac->uta_reg_count; i++)
1534 array_wr32(E1000_UTA, i, 0);
1535
1536 /* Setup link and flow control */
1537 ret_val = igb_setup_link(hw);
1538
1539 /* Clear all of the statistics registers (clear on read). It is
1540 * important that we do this after we have tried to establish link
1541 * because the symbol error count will increment wildly if there
1542 * is no link.
1543 */
1544 igb_clear_hw_cntrs_82575(hw);
1545 return ret_val;
1546 }
1547
1548 /**
1549 * igb_setup_copper_link_82575 - Configure copper link settings
1550 * @hw: pointer to the HW structure
1551 *
1552 * Configures the link for auto-neg or forced speed and duplex. Then we check
1553 * for link, once link is established calls to configure collision distance
1554 * and flow control are called.
1555 **/
igb_setup_copper_link_82575(struct e1000_hw * hw)1556 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1557 {
1558 u32 ctrl;
1559 s32 ret_val;
1560 u32 phpm_reg;
1561
1562 ctrl = rd32(E1000_CTRL);
1563 ctrl |= E1000_CTRL_SLU;
1564 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1565 wr32(E1000_CTRL, ctrl);
1566
1567 /* Clear Go Link Disconnect bit on supported devices */
1568 switch (hw->mac.type) {
1569 case e1000_82580:
1570 case e1000_i350:
1571 case e1000_i210:
1572 case e1000_i211:
1573 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1574 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1575 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1576 break;
1577 default:
1578 break;
1579 }
1580
1581 ret_val = igb_setup_serdes_link_82575(hw);
1582 if (ret_val)
1583 goto out;
1584
1585 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1586 /* allow time for SFP cage time to power up phy */
1587 msleep(300);
1588
1589 ret_val = hw->phy.ops.reset(hw);
1590 if (ret_val) {
1591 hw_dbg("Error resetting the PHY.\n");
1592 goto out;
1593 }
1594 }
1595 switch (hw->phy.type) {
1596 case e1000_phy_i210:
1597 case e1000_phy_m88:
1598 switch (hw->phy.id) {
1599 case I347AT4_E_PHY_ID:
1600 case M88E1112_E_PHY_ID:
1601 case M88E1543_E_PHY_ID:
1602 case M88E1512_E_PHY_ID:
1603 case I210_I_PHY_ID:
1604 ret_val = igb_copper_link_setup_m88_gen2(hw);
1605 break;
1606 default:
1607 ret_val = igb_copper_link_setup_m88(hw);
1608 break;
1609 }
1610 break;
1611 case e1000_phy_igp_3:
1612 ret_val = igb_copper_link_setup_igp(hw);
1613 break;
1614 case e1000_phy_82580:
1615 ret_val = igb_copper_link_setup_82580(hw);
1616 break;
1617 default:
1618 ret_val = -E1000_ERR_PHY;
1619 break;
1620 }
1621
1622 if (ret_val)
1623 goto out;
1624
1625 ret_val = igb_setup_copper_link(hw);
1626 out:
1627 return ret_val;
1628 }
1629
1630 /**
1631 * igb_setup_serdes_link_82575 - Setup link for serdes
1632 * @hw: pointer to the HW structure
1633 *
1634 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1635 * used on copper connections where the serialized gigabit media independent
1636 * interface (sgmii), or serdes fiber is being used. Configures the link
1637 * for auto-negotiation or forces speed/duplex.
1638 **/
igb_setup_serdes_link_82575(struct e1000_hw * hw)1639 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1640 {
1641 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1642 bool pcs_autoneg;
1643 s32 ret_val = 0;
1644 u16 data;
1645
1646 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1647 !igb_sgmii_active_82575(hw))
1648 return ret_val;
1649
1650
1651 /* On the 82575, SerDes loopback mode persists until it is
1652 * explicitly turned off or a power cycle is performed. A read to
1653 * the register does not indicate its status. Therefore, we ensure
1654 * loopback mode is disabled during initialization.
1655 */
1656 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1657
1658 /* power on the sfp cage if present and turn on I2C */
1659 ctrl_ext = rd32(E1000_CTRL_EXT);
1660 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1661 ctrl_ext |= E1000_CTRL_I2C_ENA;
1662 wr32(E1000_CTRL_EXT, ctrl_ext);
1663
1664 ctrl_reg = rd32(E1000_CTRL);
1665 ctrl_reg |= E1000_CTRL_SLU;
1666
1667 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1668 /* set both sw defined pins */
1669 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1670
1671 /* Set switch control to serdes energy detect */
1672 reg = rd32(E1000_CONNSW);
1673 reg |= E1000_CONNSW_ENRGSRC;
1674 wr32(E1000_CONNSW, reg);
1675 }
1676
1677 reg = rd32(E1000_PCS_LCTL);
1678
1679 /* default pcs_autoneg to the same setting as mac autoneg */
1680 pcs_autoneg = hw->mac.autoneg;
1681
1682 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1683 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1684 /* sgmii mode lets the phy handle forcing speed/duplex */
1685 pcs_autoneg = true;
1686 /* autoneg time out should be disabled for SGMII mode */
1687 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1688 break;
1689 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1690 /* disable PCS autoneg and support parallel detect only */
1691 pcs_autoneg = false;
1692 default:
1693 if (hw->mac.type == e1000_82575 ||
1694 hw->mac.type == e1000_82576) {
1695 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1696 if (ret_val) {
1697 hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
1698 return ret_val;
1699 }
1700
1701 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1702 pcs_autoneg = false;
1703 }
1704
1705 /* non-SGMII modes only supports a speed of 1000/Full for the
1706 * link so it is best to just force the MAC and let the pcs
1707 * link either autoneg or be forced to 1000/Full
1708 */
1709 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1710 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1711
1712 /* set speed of 1000/Full if speed/duplex is forced */
1713 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1714 break;
1715 }
1716
1717 wr32(E1000_CTRL, ctrl_reg);
1718
1719 /* New SerDes mode allows for forcing speed or autonegotiating speed
1720 * at 1gb. Autoneg should be default set by most drivers. This is the
1721 * mode that will be compatible with older link partners and switches.
1722 * However, both are supported by the hardware and some drivers/tools.
1723 */
1724 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1725 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1726
1727 if (pcs_autoneg) {
1728 /* Set PCS register for autoneg */
1729 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1730 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1731
1732 /* Disable force flow control for autoneg */
1733 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1734
1735 /* Configure flow control advertisement for autoneg */
1736 anadv_reg = rd32(E1000_PCS_ANADV);
1737 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1738 switch (hw->fc.requested_mode) {
1739 case e1000_fc_full:
1740 case e1000_fc_rx_pause:
1741 anadv_reg |= E1000_TXCW_ASM_DIR;
1742 anadv_reg |= E1000_TXCW_PAUSE;
1743 break;
1744 case e1000_fc_tx_pause:
1745 anadv_reg |= E1000_TXCW_ASM_DIR;
1746 break;
1747 default:
1748 break;
1749 }
1750 wr32(E1000_PCS_ANADV, anadv_reg);
1751
1752 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1753 } else {
1754 /* Set PCS register for forced link */
1755 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1756
1757 /* Force flow control for forced link */
1758 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1759
1760 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1761 }
1762
1763 wr32(E1000_PCS_LCTL, reg);
1764
1765 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1766 igb_force_mac_fc(hw);
1767
1768 return ret_val;
1769 }
1770
1771 /**
1772 * igb_sgmii_active_82575 - Return sgmii state
1773 * @hw: pointer to the HW structure
1774 *
1775 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1776 * which can be enabled for use in the embedded applications. Simply
1777 * return the current state of the sgmii interface.
1778 **/
igb_sgmii_active_82575(struct e1000_hw * hw)1779 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1780 {
1781 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1782 return dev_spec->sgmii_active;
1783 }
1784
1785 /**
1786 * igb_reset_init_script_82575 - Inits HW defaults after reset
1787 * @hw: pointer to the HW structure
1788 *
1789 * Inits recommended HW defaults after a reset when there is no EEPROM
1790 * detected. This is only for the 82575.
1791 **/
igb_reset_init_script_82575(struct e1000_hw * hw)1792 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1793 {
1794 if (hw->mac.type == e1000_82575) {
1795 hw_dbg("Running reset init script for 82575\n");
1796 /* SerDes configuration via SERDESCTRL */
1797 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1798 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1799 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1800 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1801
1802 /* CCM configuration via CCMCTL register */
1803 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1804 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1805
1806 /* PCIe lanes configuration */
1807 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1808 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1809 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1810 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1811
1812 /* PCIe PLL Configuration */
1813 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1814 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1815 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1816 }
1817
1818 return 0;
1819 }
1820
1821 /**
1822 * igb_read_mac_addr_82575 - Read device MAC address
1823 * @hw: pointer to the HW structure
1824 **/
igb_read_mac_addr_82575(struct e1000_hw * hw)1825 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1826 {
1827 s32 ret_val = 0;
1828
1829 /* If there's an alternate MAC address place it in RAR0
1830 * so that it will override the Si installed default perm
1831 * address.
1832 */
1833 ret_val = igb_check_alt_mac_addr(hw);
1834 if (ret_val)
1835 goto out;
1836
1837 ret_val = igb_read_mac_addr(hw);
1838
1839 out:
1840 return ret_val;
1841 }
1842
1843 /**
1844 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1845 * @hw: pointer to the HW structure
1846 *
1847 * In the case of a PHY power down to save power, or to turn off link during a
1848 * driver unload, or wake on lan is not enabled, remove the link.
1849 **/
igb_power_down_phy_copper_82575(struct e1000_hw * hw)1850 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1851 {
1852 /* If the management interface is not enabled, then power down */
1853 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1854 igb_power_down_phy_copper(hw);
1855 }
1856
1857 /**
1858 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1859 * @hw: pointer to the HW structure
1860 *
1861 * Clears the hardware counters by reading the counter registers.
1862 **/
igb_clear_hw_cntrs_82575(struct e1000_hw * hw)1863 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1864 {
1865 igb_clear_hw_cntrs_base(hw);
1866
1867 rd32(E1000_PRC64);
1868 rd32(E1000_PRC127);
1869 rd32(E1000_PRC255);
1870 rd32(E1000_PRC511);
1871 rd32(E1000_PRC1023);
1872 rd32(E1000_PRC1522);
1873 rd32(E1000_PTC64);
1874 rd32(E1000_PTC127);
1875 rd32(E1000_PTC255);
1876 rd32(E1000_PTC511);
1877 rd32(E1000_PTC1023);
1878 rd32(E1000_PTC1522);
1879
1880 rd32(E1000_ALGNERRC);
1881 rd32(E1000_RXERRC);
1882 rd32(E1000_TNCRS);
1883 rd32(E1000_CEXTERR);
1884 rd32(E1000_TSCTC);
1885 rd32(E1000_TSCTFC);
1886
1887 rd32(E1000_MGTPRC);
1888 rd32(E1000_MGTPDC);
1889 rd32(E1000_MGTPTC);
1890
1891 rd32(E1000_IAC);
1892 rd32(E1000_ICRXOC);
1893
1894 rd32(E1000_ICRXPTC);
1895 rd32(E1000_ICRXATC);
1896 rd32(E1000_ICTXPTC);
1897 rd32(E1000_ICTXATC);
1898 rd32(E1000_ICTXQEC);
1899 rd32(E1000_ICTXQMTC);
1900 rd32(E1000_ICRXDMTC);
1901
1902 rd32(E1000_CBTMPC);
1903 rd32(E1000_HTDPMC);
1904 rd32(E1000_CBRMPC);
1905 rd32(E1000_RPTHC);
1906 rd32(E1000_HGPTC);
1907 rd32(E1000_HTCBDPC);
1908 rd32(E1000_HGORCL);
1909 rd32(E1000_HGORCH);
1910 rd32(E1000_HGOTCL);
1911 rd32(E1000_HGOTCH);
1912 rd32(E1000_LENERRS);
1913
1914 /* This register should not be read in copper configurations */
1915 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1916 igb_sgmii_active_82575(hw))
1917 rd32(E1000_SCVPC);
1918 }
1919
1920 /**
1921 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1922 * @hw: pointer to the HW structure
1923 *
1924 * After rx enable if manageability is enabled then there is likely some
1925 * bad data at the start of the fifo and possibly in the DMA fifo. This
1926 * function clears the fifos and flushes any packets that came in as rx was
1927 * being enabled.
1928 **/
igb_rx_fifo_flush_82575(struct e1000_hw * hw)1929 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1930 {
1931 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1932 int i, ms_wait;
1933
1934 /* disable IPv6 options as per hardware errata */
1935 rfctl = rd32(E1000_RFCTL);
1936 rfctl |= E1000_RFCTL_IPV6_EX_DIS;
1937 wr32(E1000_RFCTL, rfctl);
1938
1939 if (hw->mac.type != e1000_82575 ||
1940 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1941 return;
1942
1943 /* Disable all RX queues */
1944 for (i = 0; i < 4; i++) {
1945 rxdctl[i] = rd32(E1000_RXDCTL(i));
1946 wr32(E1000_RXDCTL(i),
1947 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1948 }
1949 /* Poll all queues to verify they have shut down */
1950 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1951 usleep_range(1000, 2000);
1952 rx_enabled = 0;
1953 for (i = 0; i < 4; i++)
1954 rx_enabled |= rd32(E1000_RXDCTL(i));
1955 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1956 break;
1957 }
1958
1959 if (ms_wait == 10)
1960 hw_dbg("Queue disable timed out after 10ms\n");
1961
1962 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1963 * incoming packets are rejected. Set enable and wait 2ms so that
1964 * any packet that was coming in as RCTL.EN was set is flushed
1965 */
1966 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1967
1968 rlpml = rd32(E1000_RLPML);
1969 wr32(E1000_RLPML, 0);
1970
1971 rctl = rd32(E1000_RCTL);
1972 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1973 temp_rctl |= E1000_RCTL_LPE;
1974
1975 wr32(E1000_RCTL, temp_rctl);
1976 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1977 wrfl();
1978 usleep_range(2000, 3000);
1979
1980 /* Enable RX queues that were previously enabled and restore our
1981 * previous state
1982 */
1983 for (i = 0; i < 4; i++)
1984 wr32(E1000_RXDCTL(i), rxdctl[i]);
1985 wr32(E1000_RCTL, rctl);
1986 wrfl();
1987
1988 wr32(E1000_RLPML, rlpml);
1989 wr32(E1000_RFCTL, rfctl);
1990
1991 /* Flush receive errors generated by workaround */
1992 rd32(E1000_ROC);
1993 rd32(E1000_RNBC);
1994 rd32(E1000_MPC);
1995 }
1996
1997 /**
1998 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1999 * @hw: pointer to the HW structure
2000 *
2001 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2002 * however the hardware default for these parts is 500us to 1ms which is less
2003 * than the 10ms recommended by the pci-e spec. To address this we need to
2004 * increase the value to either 10ms to 200ms for capability version 1 config,
2005 * or 16ms to 55ms for version 2.
2006 **/
igb_set_pcie_completion_timeout(struct e1000_hw * hw)2007 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
2008 {
2009 u32 gcr = rd32(E1000_GCR);
2010 s32 ret_val = 0;
2011 u16 pcie_devctl2;
2012
2013 /* only take action if timeout value is defaulted to 0 */
2014 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2015 goto out;
2016
2017 /* if capabilities version is type 1 we can write the
2018 * timeout of 10ms to 200ms through the GCR register
2019 */
2020 if (!(gcr & E1000_GCR_CAP_VER2)) {
2021 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2022 goto out;
2023 }
2024
2025 /* for version 2 capabilities we need to write the config space
2026 * directly in order to set the completion timeout value for
2027 * 16ms to 55ms
2028 */
2029 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2030 &pcie_devctl2);
2031 if (ret_val)
2032 goto out;
2033
2034 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2035
2036 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2037 &pcie_devctl2);
2038 out:
2039 /* disable completion timeout resend */
2040 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2041
2042 wr32(E1000_GCR, gcr);
2043 return ret_val;
2044 }
2045
2046 /**
2047 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2048 * @hw: pointer to the hardware struct
2049 * @enable: state to enter, either enabled or disabled
2050 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2051 *
2052 * enables/disables L2 switch anti-spoofing functionality.
2053 **/
igb_vmdq_set_anti_spoofing_pf(struct e1000_hw * hw,bool enable,int pf)2054 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2055 {
2056 u32 reg_val, reg_offset;
2057
2058 switch (hw->mac.type) {
2059 case e1000_82576:
2060 reg_offset = E1000_DTXSWC;
2061 break;
2062 case e1000_i350:
2063 case e1000_i354:
2064 reg_offset = E1000_TXSWC;
2065 break;
2066 default:
2067 return;
2068 }
2069
2070 reg_val = rd32(reg_offset);
2071 if (enable) {
2072 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2073 E1000_DTXSWC_VLAN_SPOOF_MASK);
2074 /* The PF can spoof - it has to in order to
2075 * support emulation mode NICs
2076 */
2077 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2078 } else {
2079 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2080 E1000_DTXSWC_VLAN_SPOOF_MASK);
2081 }
2082 wr32(reg_offset, reg_val);
2083 }
2084
2085 /**
2086 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2087 * @hw: pointer to the hardware struct
2088 * @enable: state to enter, either enabled or disabled
2089 *
2090 * enables/disables L2 switch loopback functionality.
2091 **/
igb_vmdq_set_loopback_pf(struct e1000_hw * hw,bool enable)2092 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2093 {
2094 u32 dtxswc;
2095
2096 switch (hw->mac.type) {
2097 case e1000_82576:
2098 dtxswc = rd32(E1000_DTXSWC);
2099 if (enable)
2100 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2101 else
2102 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2103 wr32(E1000_DTXSWC, dtxswc);
2104 break;
2105 case e1000_i354:
2106 case e1000_i350:
2107 dtxswc = rd32(E1000_TXSWC);
2108 if (enable)
2109 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2110 else
2111 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2112 wr32(E1000_TXSWC, dtxswc);
2113 break;
2114 default:
2115 /* Currently no other hardware supports loopback */
2116 break;
2117 }
2118
2119 }
2120
2121 /**
2122 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2123 * @hw: pointer to the hardware struct
2124 * @enable: state to enter, either enabled or disabled
2125 *
2126 * enables/disables replication of packets across multiple pools.
2127 **/
igb_vmdq_set_replication_pf(struct e1000_hw * hw,bool enable)2128 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2129 {
2130 u32 vt_ctl = rd32(E1000_VT_CTL);
2131
2132 if (enable)
2133 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2134 else
2135 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2136
2137 wr32(E1000_VT_CTL, vt_ctl);
2138 }
2139
2140 /**
2141 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2142 * @hw: pointer to the HW structure
2143 * @offset: register offset to be read
2144 * @data: pointer to the read data
2145 *
2146 * Reads the MDI control register in the PHY at offset and stores the
2147 * information read to data.
2148 **/
igb_read_phy_reg_82580(struct e1000_hw * hw,u32 offset,u16 * data)2149 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2150 {
2151 s32 ret_val;
2152
2153 ret_val = hw->phy.ops.acquire(hw);
2154 if (ret_val)
2155 goto out;
2156
2157 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2158
2159 hw->phy.ops.release(hw);
2160
2161 out:
2162 return ret_val;
2163 }
2164
2165 /**
2166 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2167 * @hw: pointer to the HW structure
2168 * @offset: register offset to write to
2169 * @data: data to write to register at offset
2170 *
2171 * Writes data to MDI control register in the PHY at offset.
2172 **/
igb_write_phy_reg_82580(struct e1000_hw * hw,u32 offset,u16 data)2173 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2174 {
2175 s32 ret_val;
2176
2177
2178 ret_val = hw->phy.ops.acquire(hw);
2179 if (ret_val)
2180 goto out;
2181
2182 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2183
2184 hw->phy.ops.release(hw);
2185
2186 out:
2187 return ret_val;
2188 }
2189
2190 /**
2191 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2192 * @hw: pointer to the HW structure
2193 *
2194 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2195 * the values found in the EEPROM. This addresses an issue in which these
2196 * bits are not restored from EEPROM after reset.
2197 **/
igb_reset_mdicnfg_82580(struct e1000_hw * hw)2198 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2199 {
2200 s32 ret_val = 0;
2201 u32 mdicnfg;
2202 u16 nvm_data = 0;
2203
2204 if (hw->mac.type != e1000_82580)
2205 goto out;
2206 if (!igb_sgmii_active_82575(hw))
2207 goto out;
2208
2209 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2210 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2211 &nvm_data);
2212 if (ret_val) {
2213 hw_dbg("NVM Read Error\n");
2214 goto out;
2215 }
2216
2217 mdicnfg = rd32(E1000_MDICNFG);
2218 if (nvm_data & NVM_WORD24_EXT_MDIO)
2219 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2220 if (nvm_data & NVM_WORD24_COM_MDIO)
2221 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2222 wr32(E1000_MDICNFG, mdicnfg);
2223 out:
2224 return ret_val;
2225 }
2226
2227 /**
2228 * igb_reset_hw_82580 - Reset hardware
2229 * @hw: pointer to the HW structure
2230 *
2231 * This resets function or entire device (all ports, etc.)
2232 * to a known state.
2233 **/
igb_reset_hw_82580(struct e1000_hw * hw)2234 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2235 {
2236 s32 ret_val = 0;
2237 /* BH SW mailbox bit in SW_FW_SYNC */
2238 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2239 u32 ctrl;
2240 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2241
2242 hw->dev_spec._82575.global_device_reset = false;
2243
2244 /* due to hw errata, global device reset doesn't always
2245 * work on 82580
2246 */
2247 if (hw->mac.type == e1000_82580)
2248 global_device_reset = false;
2249
2250 /* Get current control state. */
2251 ctrl = rd32(E1000_CTRL);
2252
2253 /* Prevent the PCI-E bus from sticking if there is no TLP connection
2254 * on the last TLP read/write transaction when MAC is reset.
2255 */
2256 ret_val = igb_disable_pcie_master(hw);
2257 if (ret_val)
2258 hw_dbg("PCI-E Master disable polling has failed.\n");
2259
2260 hw_dbg("Masking off all interrupts\n");
2261 wr32(E1000_IMC, 0xffffffff);
2262 wr32(E1000_RCTL, 0);
2263 wr32(E1000_TCTL, E1000_TCTL_PSP);
2264 wrfl();
2265
2266 usleep_range(10000, 11000);
2267
2268 /* Determine whether or not a global dev reset is requested */
2269 if (global_device_reset &&
2270 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2271 global_device_reset = false;
2272
2273 if (global_device_reset &&
2274 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2275 ctrl |= E1000_CTRL_DEV_RST;
2276 else
2277 ctrl |= E1000_CTRL_RST;
2278
2279 wr32(E1000_CTRL, ctrl);
2280 wrfl();
2281
2282 /* Add delay to insure DEV_RST has time to complete */
2283 if (global_device_reset)
2284 usleep_range(5000, 6000);
2285
2286 ret_val = igb_get_auto_rd_done(hw);
2287 if (ret_val) {
2288 /* When auto config read does not complete, do not
2289 * return with an error. This can happen in situations
2290 * where there is no eeprom and prevents getting link.
2291 */
2292 hw_dbg("Auto Read Done did not complete\n");
2293 }
2294
2295 /* clear global device reset status bit */
2296 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2297
2298 /* Clear any pending interrupt events. */
2299 wr32(E1000_IMC, 0xffffffff);
2300 rd32(E1000_ICR);
2301
2302 ret_val = igb_reset_mdicnfg_82580(hw);
2303 if (ret_val)
2304 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2305
2306 /* Install any alternate MAC address into RAR0 */
2307 ret_val = igb_check_alt_mac_addr(hw);
2308
2309 /* Release semaphore */
2310 if (global_device_reset)
2311 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2312
2313 return ret_val;
2314 }
2315
2316 /**
2317 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2318 * @data: data received by reading RXPBS register
2319 *
2320 * The 82580 uses a table based approach for packet buffer allocation sizes.
2321 * This function converts the retrieved value into the correct table value
2322 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2323 * 0x0 36 72 144 1 2 4 8 16
2324 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2325 */
igb_rxpbs_adjust_82580(u32 data)2326 u16 igb_rxpbs_adjust_82580(u32 data)
2327 {
2328 u16 ret_val = 0;
2329
2330 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
2331 ret_val = e1000_82580_rxpbs_table[data];
2332
2333 return ret_val;
2334 }
2335
2336 /**
2337 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2338 * checksum
2339 * @hw: pointer to the HW structure
2340 * @offset: offset in words of the checksum protected region
2341 *
2342 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2343 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2344 **/
igb_validate_nvm_checksum_with_offset(struct e1000_hw * hw,u16 offset)2345 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2346 u16 offset)
2347 {
2348 s32 ret_val = 0;
2349 u16 checksum = 0;
2350 u16 i, nvm_data;
2351
2352 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2353 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2354 if (ret_val) {
2355 hw_dbg("NVM Read Error\n");
2356 goto out;
2357 }
2358 checksum += nvm_data;
2359 }
2360
2361 if (checksum != (u16) NVM_SUM) {
2362 hw_dbg("NVM Checksum Invalid\n");
2363 ret_val = -E1000_ERR_NVM;
2364 goto out;
2365 }
2366
2367 out:
2368 return ret_val;
2369 }
2370
2371 /**
2372 * igb_update_nvm_checksum_with_offset - Update EEPROM
2373 * checksum
2374 * @hw: pointer to the HW structure
2375 * @offset: offset in words of the checksum protected region
2376 *
2377 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2378 * up to the checksum. Then calculates the EEPROM checksum and writes the
2379 * value to the EEPROM.
2380 **/
igb_update_nvm_checksum_with_offset(struct e1000_hw * hw,u16 offset)2381 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2382 {
2383 s32 ret_val;
2384 u16 checksum = 0;
2385 u16 i, nvm_data;
2386
2387 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2388 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2389 if (ret_val) {
2390 hw_dbg("NVM Read Error while updating checksum.\n");
2391 goto out;
2392 }
2393 checksum += nvm_data;
2394 }
2395 checksum = (u16) NVM_SUM - checksum;
2396 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2397 &checksum);
2398 if (ret_val)
2399 hw_dbg("NVM Write Error while updating checksum.\n");
2400
2401 out:
2402 return ret_val;
2403 }
2404
2405 /**
2406 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2407 * @hw: pointer to the HW structure
2408 *
2409 * Calculates the EEPROM section checksum by reading/adding each word of
2410 * the EEPROM and then verifies that the sum of the EEPROM is
2411 * equal to 0xBABA.
2412 **/
igb_validate_nvm_checksum_82580(struct e1000_hw * hw)2413 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2414 {
2415 s32 ret_val = 0;
2416 u16 eeprom_regions_count = 1;
2417 u16 j, nvm_data;
2418 u16 nvm_offset;
2419
2420 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2421 if (ret_val) {
2422 hw_dbg("NVM Read Error\n");
2423 goto out;
2424 }
2425
2426 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2427 /* if checksums compatibility bit is set validate checksums
2428 * for all 4 ports.
2429 */
2430 eeprom_regions_count = 4;
2431 }
2432
2433 for (j = 0; j < eeprom_regions_count; j++) {
2434 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2435 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2436 nvm_offset);
2437 if (ret_val != 0)
2438 goto out;
2439 }
2440
2441 out:
2442 return ret_val;
2443 }
2444
2445 /**
2446 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2447 * @hw: pointer to the HW structure
2448 *
2449 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2450 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2451 * checksum and writes the value to the EEPROM.
2452 **/
igb_update_nvm_checksum_82580(struct e1000_hw * hw)2453 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2454 {
2455 s32 ret_val;
2456 u16 j, nvm_data;
2457 u16 nvm_offset;
2458
2459 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2460 if (ret_val) {
2461 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
2462 goto out;
2463 }
2464
2465 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2466 /* set compatibility bit to validate checksums appropriately */
2467 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2468 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2469 &nvm_data);
2470 if (ret_val) {
2471 hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
2472 goto out;
2473 }
2474 }
2475
2476 for (j = 0; j < 4; j++) {
2477 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2478 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2479 if (ret_val)
2480 goto out;
2481 }
2482
2483 out:
2484 return ret_val;
2485 }
2486
2487 /**
2488 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2489 * @hw: pointer to the HW structure
2490 *
2491 * Calculates the EEPROM section checksum by reading/adding each word of
2492 * the EEPROM and then verifies that the sum of the EEPROM is
2493 * equal to 0xBABA.
2494 **/
igb_validate_nvm_checksum_i350(struct e1000_hw * hw)2495 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2496 {
2497 s32 ret_val = 0;
2498 u16 j;
2499 u16 nvm_offset;
2500
2501 for (j = 0; j < 4; j++) {
2502 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2503 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2504 nvm_offset);
2505 if (ret_val != 0)
2506 goto out;
2507 }
2508
2509 out:
2510 return ret_val;
2511 }
2512
2513 /**
2514 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2515 * @hw: pointer to the HW structure
2516 *
2517 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2518 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2519 * checksum and writes the value to the EEPROM.
2520 **/
igb_update_nvm_checksum_i350(struct e1000_hw * hw)2521 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2522 {
2523 s32 ret_val = 0;
2524 u16 j;
2525 u16 nvm_offset;
2526
2527 for (j = 0; j < 4; j++) {
2528 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2529 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2530 if (ret_val != 0)
2531 goto out;
2532 }
2533
2534 out:
2535 return ret_val;
2536 }
2537
2538 /**
2539 * __igb_access_emi_reg - Read/write EMI register
2540 * @hw: pointer to the HW structure
2541 * @addr: EMI address to program
2542 * @data: pointer to value to read/write from/to the EMI address
2543 * @read: boolean flag to indicate read or write
2544 **/
__igb_access_emi_reg(struct e1000_hw * hw,u16 address,u16 * data,bool read)2545 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2546 u16 *data, bool read)
2547 {
2548 s32 ret_val = 0;
2549
2550 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2551 if (ret_val)
2552 return ret_val;
2553
2554 if (read)
2555 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2556 else
2557 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2558
2559 return ret_val;
2560 }
2561
2562 /**
2563 * igb_read_emi_reg - Read Extended Management Interface register
2564 * @hw: pointer to the HW structure
2565 * @addr: EMI address to program
2566 * @data: value to be read from the EMI address
2567 **/
igb_read_emi_reg(struct e1000_hw * hw,u16 addr,u16 * data)2568 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2569 {
2570 return __igb_access_emi_reg(hw, addr, data, true);
2571 }
2572
2573 /**
2574 * igb_set_eee_i350 - Enable/disable EEE support
2575 * @hw: pointer to the HW structure
2576 * @adv1G: boolean flag enabling 1G EEE advertisement
2577 * @adv100m: boolean flag enabling 100M EEE advertisement
2578 *
2579 * Enable/disable EEE based on setting in dev_spec structure.
2580 *
2581 **/
igb_set_eee_i350(struct e1000_hw * hw,bool adv1G,bool adv100M)2582 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2583 {
2584 u32 ipcnfg, eeer;
2585
2586 if ((hw->mac.type < e1000_i350) ||
2587 (hw->phy.media_type != e1000_media_type_copper))
2588 goto out;
2589 ipcnfg = rd32(E1000_IPCNFG);
2590 eeer = rd32(E1000_EEER);
2591
2592 /* enable or disable per user setting */
2593 if (!(hw->dev_spec._82575.eee_disable)) {
2594 u32 eee_su = rd32(E1000_EEE_SU);
2595
2596 if (adv100M)
2597 ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2598 else
2599 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2600
2601 if (adv1G)
2602 ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2603 else
2604 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2605
2606 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2607 E1000_EEER_LPI_FC);
2608
2609 /* This bit should not be set in normal operation. */
2610 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2611 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2612
2613 } else {
2614 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2615 E1000_IPCNFG_EEE_100M_AN);
2616 eeer &= ~(E1000_EEER_TX_LPI_EN |
2617 E1000_EEER_RX_LPI_EN |
2618 E1000_EEER_LPI_FC);
2619 }
2620 wr32(E1000_IPCNFG, ipcnfg);
2621 wr32(E1000_EEER, eeer);
2622 rd32(E1000_IPCNFG);
2623 rd32(E1000_EEER);
2624 out:
2625
2626 return 0;
2627 }
2628
2629 /**
2630 * igb_set_eee_i354 - Enable/disable EEE support
2631 * @hw: pointer to the HW structure
2632 * @adv1G: boolean flag enabling 1G EEE advertisement
2633 * @adv100m: boolean flag enabling 100M EEE advertisement
2634 *
2635 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2636 *
2637 **/
igb_set_eee_i354(struct e1000_hw * hw,bool adv1G,bool adv100M)2638 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2639 {
2640 struct e1000_phy_info *phy = &hw->phy;
2641 s32 ret_val = 0;
2642 u16 phy_data;
2643
2644 if ((hw->phy.media_type != e1000_media_type_copper) ||
2645 ((phy->id != M88E1543_E_PHY_ID) &&
2646 (phy->id != M88E1512_E_PHY_ID)))
2647 goto out;
2648
2649 if (!hw->dev_spec._82575.eee_disable) {
2650 /* Switch to PHY page 18. */
2651 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2652 if (ret_val)
2653 goto out;
2654
2655 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2656 &phy_data);
2657 if (ret_val)
2658 goto out;
2659
2660 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2661 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2662 phy_data);
2663 if (ret_val)
2664 goto out;
2665
2666 /* Return the PHY to page 0. */
2667 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2668 if (ret_val)
2669 goto out;
2670
2671 /* Turn on EEE advertisement. */
2672 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2673 E1000_EEE_ADV_DEV_I354,
2674 &phy_data);
2675 if (ret_val)
2676 goto out;
2677
2678 if (adv100M)
2679 phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2680 else
2681 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2682
2683 if (adv1G)
2684 phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2685 else
2686 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2687
2688 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2689 E1000_EEE_ADV_DEV_I354,
2690 phy_data);
2691 } else {
2692 /* Turn off EEE advertisement. */
2693 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2694 E1000_EEE_ADV_DEV_I354,
2695 &phy_data);
2696 if (ret_val)
2697 goto out;
2698
2699 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2700 E1000_EEE_ADV_1000_SUPPORTED);
2701 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2702 E1000_EEE_ADV_DEV_I354,
2703 phy_data);
2704 }
2705
2706 out:
2707 return ret_val;
2708 }
2709
2710 /**
2711 * igb_get_eee_status_i354 - Get EEE status
2712 * @hw: pointer to the HW structure
2713 * @status: EEE status
2714 *
2715 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2716 * been received.
2717 **/
igb_get_eee_status_i354(struct e1000_hw * hw,bool * status)2718 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2719 {
2720 struct e1000_phy_info *phy = &hw->phy;
2721 s32 ret_val = 0;
2722 u16 phy_data;
2723
2724 /* Check if EEE is supported on this device. */
2725 if ((hw->phy.media_type != e1000_media_type_copper) ||
2726 ((phy->id != M88E1543_E_PHY_ID) &&
2727 (phy->id != M88E1512_E_PHY_ID)))
2728 goto out;
2729
2730 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2731 E1000_PCS_STATUS_DEV_I354,
2732 &phy_data);
2733 if (ret_val)
2734 goto out;
2735
2736 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2737 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2738
2739 out:
2740 return ret_val;
2741 }
2742
2743 static const u8 e1000_emc_temp_data[4] = {
2744 E1000_EMC_INTERNAL_DATA,
2745 E1000_EMC_DIODE1_DATA,
2746 E1000_EMC_DIODE2_DATA,
2747 E1000_EMC_DIODE3_DATA
2748 };
2749 static const u8 e1000_emc_therm_limit[4] = {
2750 E1000_EMC_INTERNAL_THERM_LIMIT,
2751 E1000_EMC_DIODE1_THERM_LIMIT,
2752 E1000_EMC_DIODE2_THERM_LIMIT,
2753 E1000_EMC_DIODE3_THERM_LIMIT
2754 };
2755
2756 #ifdef CONFIG_IGB_HWMON
2757 /**
2758 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2759 * @hw: pointer to hardware structure
2760 *
2761 * Updates the temperatures in mac.thermal_sensor_data
2762 **/
igb_get_thermal_sensor_data_generic(struct e1000_hw * hw)2763 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2764 {
2765 u16 ets_offset;
2766 u16 ets_cfg;
2767 u16 ets_sensor;
2768 u8 num_sensors;
2769 u8 sensor_index;
2770 u8 sensor_location;
2771 u8 i;
2772 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2773
2774 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2775 return E1000_NOT_IMPLEMENTED;
2776
2777 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2778
2779 /* Return the internal sensor only if ETS is unsupported */
2780 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2781 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2782 return 0;
2783
2784 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2785 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2786 != NVM_ETS_TYPE_EMC)
2787 return E1000_NOT_IMPLEMENTED;
2788
2789 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2790 if (num_sensors > E1000_MAX_SENSORS)
2791 num_sensors = E1000_MAX_SENSORS;
2792
2793 for (i = 1; i < num_sensors; i++) {
2794 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2795 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2796 NVM_ETS_DATA_INDEX_SHIFT);
2797 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2798 NVM_ETS_DATA_LOC_SHIFT);
2799
2800 if (sensor_location != 0)
2801 hw->phy.ops.read_i2c_byte(hw,
2802 e1000_emc_temp_data[sensor_index],
2803 E1000_I2C_THERMAL_SENSOR_ADDR,
2804 &data->sensor[i].temp);
2805 }
2806 return 0;
2807 }
2808
2809 /**
2810 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2811 * @hw: pointer to hardware structure
2812 *
2813 * Sets the thermal sensor thresholds according to the NVM map
2814 * and save off the threshold and location values into mac.thermal_sensor_data
2815 **/
igb_init_thermal_sensor_thresh_generic(struct e1000_hw * hw)2816 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2817 {
2818 u16 ets_offset;
2819 u16 ets_cfg;
2820 u16 ets_sensor;
2821 u8 low_thresh_delta;
2822 u8 num_sensors;
2823 u8 sensor_index;
2824 u8 sensor_location;
2825 u8 therm_limit;
2826 u8 i;
2827 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2828
2829 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2830 return E1000_NOT_IMPLEMENTED;
2831
2832 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2833
2834 data->sensor[0].location = 0x1;
2835 data->sensor[0].caution_thresh =
2836 (rd32(E1000_THHIGHTC) & 0xFF);
2837 data->sensor[0].max_op_thresh =
2838 (rd32(E1000_THLOWTC) & 0xFF);
2839
2840 /* Return the internal sensor only if ETS is unsupported */
2841 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2842 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2843 return 0;
2844
2845 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2846 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2847 != NVM_ETS_TYPE_EMC)
2848 return E1000_NOT_IMPLEMENTED;
2849
2850 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2851 NVM_ETS_LTHRES_DELTA_SHIFT);
2852 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2853
2854 for (i = 1; i <= num_sensors; i++) {
2855 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2856 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2857 NVM_ETS_DATA_INDEX_SHIFT);
2858 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2859 NVM_ETS_DATA_LOC_SHIFT);
2860 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2861
2862 hw->phy.ops.write_i2c_byte(hw,
2863 e1000_emc_therm_limit[sensor_index],
2864 E1000_I2C_THERMAL_SENSOR_ADDR,
2865 therm_limit);
2866
2867 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2868 data->sensor[i].location = sensor_location;
2869 data->sensor[i].caution_thresh = therm_limit;
2870 data->sensor[i].max_op_thresh = therm_limit -
2871 low_thresh_delta;
2872 }
2873 }
2874 return 0;
2875 }
2876
2877 #endif
2878 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2879 .init_hw = igb_init_hw_82575,
2880 .check_for_link = igb_check_for_link_82575,
2881 .rar_set = igb_rar_set,
2882 .read_mac_addr = igb_read_mac_addr_82575,
2883 .get_speed_and_duplex = igb_get_link_up_info_82575,
2884 #ifdef CONFIG_IGB_HWMON
2885 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2886 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2887 #endif
2888 };
2889
2890 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2891 .acquire = igb_acquire_phy_82575,
2892 .get_cfg_done = igb_get_cfg_done_82575,
2893 .release = igb_release_phy_82575,
2894 .write_i2c_byte = igb_write_i2c_byte,
2895 .read_i2c_byte = igb_read_i2c_byte,
2896 };
2897
2898 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2899 .acquire = igb_acquire_nvm_82575,
2900 .read = igb_read_nvm_eerd,
2901 .release = igb_release_nvm_82575,
2902 .write = igb_write_nvm_spi,
2903 };
2904
2905 const struct e1000_info e1000_82575_info = {
2906 .get_invariants = igb_get_invariants_82575,
2907 .mac_ops = &e1000_mac_ops_82575,
2908 .phy_ops = &e1000_phy_ops_82575,
2909 .nvm_ops = &e1000_nvm_ops_82575,
2910 };
2911
2912