1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28 #include "ixgbe.h"
29 #include <linux/ptp_classify.h>
30
31 /*
32 * The 82599 and the X540 do not have true 64bit nanosecond scale
33 * counter registers. Instead, SYSTIME is defined by a fixed point
34 * system which allows the user to define the scale counter increment
35 * value at every level change of the oscillator driving the SYSTIME
36 * value. For both devices the TIMINCA:IV field defines this
37 * increment. On the X540 device, 31 bits are provided. However on the
38 * 82599 only provides 24 bits. The time unit is determined by the
39 * clock frequency of the oscillator in combination with the TIMINCA
40 * register. When these devices link at 10Gb the oscillator has a
41 * period of 6.4ns. In order to convert the scale counter into
42 * nanoseconds the cyclecounter and timecounter structures are
43 * used. The SYSTIME registers need to be converted to ns values by use
44 * of only a right shift (division by power of 2). The following math
45 * determines the largest incvalue that will fit into the available
46 * bits in the TIMINCA register.
47 *
48 * PeriodWidth: Number of bits to store the clock period
49 * MaxWidth: The maximum width value of the TIMINCA register
50 * Period: The clock period for the oscillator
51 * round(): discard the fractional portion of the calculation
52 *
53 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
54 *
55 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
56 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
57 *
58 * The period also changes based on the link speed:
59 * At 10Gb link or no link, the period remains the same.
60 * At 1Gb link, the period is multiplied by 10. (64ns)
61 * At 100Mb link, the period is multiplied by 100. (640ns)
62 *
63 * The calculated value allows us to right shift the SYSTIME register
64 * value in order to quickly convert it into a nanosecond clock,
65 * while allowing for the maximum possible adjustment value.
66 *
67 * These diagrams are only for the 10Gb link period
68 *
69 * SYSTIMEH SYSTIMEL
70 * +--------------+ +--------------+
71 * X540 | 32 | | 1 | 3 | 28 |
72 * *--------------+ +--------------+
73 * \________ 36 bits ______/ fract
74 *
75 * +--------------+ +--------------+
76 * 82599 | 32 | | 8 | 3 | 21 |
77 * *--------------+ +--------------+
78 * \________ 43 bits ______/ fract
79 *
80 * The 36 bit X540 SYSTIME overflows every
81 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
82 *
83 * The 43 bit 82599 SYSTIME overflows every
84 * 2^43 * 10^-9 / 3600 = 2.4 hours
85 */
86 #define IXGBE_INCVAL_10GB 0x66666666
87 #define IXGBE_INCVAL_1GB 0x40000000
88 #define IXGBE_INCVAL_100 0x50000000
89
90 #define IXGBE_INCVAL_SHIFT_10GB 28
91 #define IXGBE_INCVAL_SHIFT_1GB 24
92 #define IXGBE_INCVAL_SHIFT_100 21
93
94 #define IXGBE_INCVAL_SHIFT_82599 7
95 #define IXGBE_INCPER_SHIFT_82599 24
96 #define IXGBE_MAX_TIMEADJ_VALUE 0x7FFFFFFFFFFFFFFFULL
97
98 #define IXGBE_OVERFLOW_PERIOD (HZ * 30)
99 #define IXGBE_PTP_TX_TIMEOUT (HZ * 15)
100
101 /* half of a one second clock period, for use with PPS signal. We have to use
102 * this instead of something pre-defined like IXGBE_PTP_PPS_HALF_SECOND, in
103 * order to force at least 64bits of precision for shifting
104 */
105 #define IXGBE_PTP_PPS_HALF_SECOND 500000000ULL
106
107 /**
108 * ixgbe_ptp_setup_sdp
109 * @hw: the hardware private structure
110 *
111 * this function enables or disables the clock out feature on SDP0 for
112 * the X540 device. It will create a 1second periodic output that can
113 * be used as the PPS (via an interrupt).
114 *
115 * It calculates when the systime will be on an exact second, and then
116 * aligns the start of the PPS signal to that value. The shift is
117 * necessary because it can change based on the link speed.
118 */
ixgbe_ptp_setup_sdp(struct ixgbe_adapter * adapter)119 static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
120 {
121 struct ixgbe_hw *hw = &adapter->hw;
122 int shift = adapter->cc.shift;
123 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
124 u64 ns = 0, clock_edge = 0;
125
126 if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
127 (hw->mac.type == ixgbe_mac_X540)) {
128
129 /* disable the pin first */
130 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
131 IXGBE_WRITE_FLUSH(hw);
132
133 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
134
135 /*
136 * enable the SDP0 pin as output, and connected to the
137 * native function for Timesync (ClockOut)
138 */
139 esdp |= (IXGBE_ESDP_SDP0_DIR |
140 IXGBE_ESDP_SDP0_NATIVE);
141
142 /*
143 * enable the Clock Out feature on SDP0, and allow
144 * interrupts to occur when the pin changes
145 */
146 tsauxc = (IXGBE_TSAUXC_EN_CLK |
147 IXGBE_TSAUXC_SYNCLK |
148 IXGBE_TSAUXC_SDP0_INT);
149
150 /* clock period (or pulse length) */
151 clktiml = (u32)(IXGBE_PTP_PPS_HALF_SECOND << shift);
152 clktimh = (u32)((IXGBE_PTP_PPS_HALF_SECOND << shift) >> 32);
153
154 /*
155 * Account for the cyclecounter wrap-around value by
156 * using the converted ns value of the current time to
157 * check for when the next aligned second would occur.
158 */
159 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
160 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
161 ns = timecounter_cyc2time(&adapter->tc, clock_edge);
162
163 div_u64_rem(ns, IXGBE_PTP_PPS_HALF_SECOND, &rem);
164 clock_edge += ((IXGBE_PTP_PPS_HALF_SECOND - (u64)rem) << shift);
165
166 /* specify the initial clock start time */
167 trgttiml = (u32)clock_edge;
168 trgttimh = (u32)(clock_edge >> 32);
169
170 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
171 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
172 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
173 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
174
175 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
176 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
177 } else {
178 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
179 }
180
181 IXGBE_WRITE_FLUSH(hw);
182 }
183
184 /**
185 * ixgbe_ptp_read - read raw cycle counter (to be used by time counter)
186 * @cc: the cyclecounter structure
187 *
188 * this function reads the cyclecounter registers and is called by the
189 * cyclecounter structure used to construct a ns counter from the
190 * arbitrary fixed point registers
191 */
ixgbe_ptp_read(const struct cyclecounter * cc)192 static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc)
193 {
194 struct ixgbe_adapter *adapter =
195 container_of(cc, struct ixgbe_adapter, cc);
196 struct ixgbe_hw *hw = &adapter->hw;
197 u64 stamp = 0;
198
199 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
200 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
201
202 return stamp;
203 }
204
205 /**
206 * ixgbe_ptp_adjfreq
207 * @ptp: the ptp clock structure
208 * @ppb: parts per billion adjustment from base
209 *
210 * adjust the frequency of the ptp cycle counter by the
211 * indicated ppb from the base frequency.
212 */
ixgbe_ptp_adjfreq(struct ptp_clock_info * ptp,s32 ppb)213 static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
214 {
215 struct ixgbe_adapter *adapter =
216 container_of(ptp, struct ixgbe_adapter, ptp_caps);
217 struct ixgbe_hw *hw = &adapter->hw;
218 u64 freq;
219 u32 diff, incval;
220 int neg_adj = 0;
221
222 if (ppb < 0) {
223 neg_adj = 1;
224 ppb = -ppb;
225 }
226
227 smp_mb();
228 incval = ACCESS_ONCE(adapter->base_incval);
229
230 freq = incval;
231 freq *= ppb;
232 diff = div_u64(freq, 1000000000ULL);
233
234 incval = neg_adj ? (incval - diff) : (incval + diff);
235
236 switch (hw->mac.type) {
237 case ixgbe_mac_X540:
238 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
239 break;
240 case ixgbe_mac_82599EB:
241 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
242 (1 << IXGBE_INCPER_SHIFT_82599) |
243 incval);
244 break;
245 default:
246 break;
247 }
248
249 return 0;
250 }
251
252 /**
253 * ixgbe_ptp_adjtime
254 * @ptp: the ptp clock structure
255 * @delta: offset to adjust the cycle counter by
256 *
257 * adjust the timer by resetting the timecounter structure.
258 */
ixgbe_ptp_adjtime(struct ptp_clock_info * ptp,s64 delta)259 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
260 {
261 struct ixgbe_adapter *adapter =
262 container_of(ptp, struct ixgbe_adapter, ptp_caps);
263 unsigned long flags;
264
265 spin_lock_irqsave(&adapter->tmreg_lock, flags);
266 timecounter_adjtime(&adapter->tc, delta);
267 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
268
269 ixgbe_ptp_setup_sdp(adapter);
270
271 return 0;
272 }
273
274 /**
275 * ixgbe_ptp_gettime
276 * @ptp: the ptp clock structure
277 * @ts: timespec structure to hold the current time value
278 *
279 * read the timecounter and return the correct value on ns,
280 * after converting it into a struct timespec.
281 */
ixgbe_ptp_gettime(struct ptp_clock_info * ptp,struct timespec64 * ts)282 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
283 {
284 struct ixgbe_adapter *adapter =
285 container_of(ptp, struct ixgbe_adapter, ptp_caps);
286 u64 ns;
287 unsigned long flags;
288
289 spin_lock_irqsave(&adapter->tmreg_lock, flags);
290 ns = timecounter_read(&adapter->tc);
291 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
292
293 *ts = ns_to_timespec64(ns);
294
295 return 0;
296 }
297
298 /**
299 * ixgbe_ptp_settime
300 * @ptp: the ptp clock structure
301 * @ts: the timespec containing the new time for the cycle counter
302 *
303 * reset the timecounter to use a new base value instead of the kernel
304 * wall timer value.
305 */
ixgbe_ptp_settime(struct ptp_clock_info * ptp,const struct timespec64 * ts)306 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
307 const struct timespec64 *ts)
308 {
309 struct ixgbe_adapter *adapter =
310 container_of(ptp, struct ixgbe_adapter, ptp_caps);
311 u64 ns;
312 unsigned long flags;
313
314 ns = timespec64_to_ns(ts);
315
316 /* reset the timecounter */
317 spin_lock_irqsave(&adapter->tmreg_lock, flags);
318 timecounter_init(&adapter->tc, &adapter->cc, ns);
319 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
320
321 ixgbe_ptp_setup_sdp(adapter);
322 return 0;
323 }
324
325 /**
326 * ixgbe_ptp_feature_enable
327 * @ptp: the ptp clock structure
328 * @rq: the requested feature to change
329 * @on: whether to enable or disable the feature
330 *
331 * enable (or disable) ancillary features of the phc subsystem.
332 * our driver only supports the PPS feature on the X540
333 */
ixgbe_ptp_feature_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)334 static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
335 struct ptp_clock_request *rq, int on)
336 {
337 struct ixgbe_adapter *adapter =
338 container_of(ptp, struct ixgbe_adapter, ptp_caps);
339
340 /**
341 * When PPS is enabled, unmask the interrupt for the ClockOut
342 * feature, so that the interrupt handler can send the PPS
343 * event when the clock SDP triggers. Clear mask when PPS is
344 * disabled
345 */
346 if (rq->type == PTP_CLK_REQ_PPS) {
347 switch (adapter->hw.mac.type) {
348 case ixgbe_mac_X540:
349 if (on)
350 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
351 else
352 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
353
354 ixgbe_ptp_setup_sdp(adapter);
355 return 0;
356 default:
357 break;
358 }
359 }
360
361 return -ENOTSUPP;
362 }
363
364 /**
365 * ixgbe_ptp_check_pps_event
366 * @adapter: the private adapter structure
367 * @eicr: the interrupt cause register value
368 *
369 * This function is called by the interrupt routine when checking for
370 * interrupts. It will check and handle a pps event.
371 */
ixgbe_ptp_check_pps_event(struct ixgbe_adapter * adapter,u32 eicr)372 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
373 {
374 struct ixgbe_hw *hw = &adapter->hw;
375 struct ptp_clock_event event;
376
377 event.type = PTP_CLOCK_PPS;
378
379 /* this check is necessary in case the interrupt was enabled via some
380 * alternative means (ex. debug_fs). Better to check here than
381 * everywhere that calls this function.
382 */
383 if (!adapter->ptp_clock)
384 return;
385
386 switch (hw->mac.type) {
387 case ixgbe_mac_X540:
388 ptp_clock_event(adapter->ptp_clock, &event);
389 break;
390 default:
391 break;
392 }
393 }
394
395 /**
396 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
397 * @adapter: private adapter struct
398 *
399 * this watchdog task periodically reads the timecounter
400 * in order to prevent missing when the system time registers wrap
401 * around. This needs to be run approximately twice a minute.
402 */
ixgbe_ptp_overflow_check(struct ixgbe_adapter * adapter)403 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
404 {
405 bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
406 IXGBE_OVERFLOW_PERIOD);
407 struct timespec64 ts;
408
409 if (timeout) {
410 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
411 adapter->last_overflow_check = jiffies;
412 }
413 }
414
415 /**
416 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
417 * @adapter: private network adapter structure
418 *
419 * this watchdog task is scheduled to detect error case where hardware has
420 * dropped an Rx packet that was timestamped when the ring is full. The
421 * particular error is rare but leaves the device in a state unable to timestamp
422 * any future packets.
423 */
ixgbe_ptp_rx_hang(struct ixgbe_adapter * adapter)424 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
425 {
426 struct ixgbe_hw *hw = &adapter->hw;
427 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
428 unsigned long rx_event;
429
430 /* if we don't have a valid timestamp in the registers, just update the
431 * timeout counter and exit
432 */
433 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
434 adapter->last_rx_ptp_check = jiffies;
435 return;
436 }
437
438 /* determine the most recent watchdog or rx_timestamp event */
439 rx_event = adapter->last_rx_ptp_check;
440 if (time_after(adapter->last_rx_timestamp, rx_event))
441 rx_event = adapter->last_rx_timestamp;
442
443 /* only need to read the high RXSTMP register to clear the lock */
444 if (time_is_before_jiffies(rx_event + 5*HZ)) {
445 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
446 adapter->last_rx_ptp_check = jiffies;
447
448 e_warn(drv, "clearing RX Timestamp hang\n");
449 }
450 }
451
452 /**
453 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
454 * @adapter: the private adapter struct
455 *
456 * if the timestamp is valid, we convert it into the timecounter ns
457 * value, then store that result into the shhwtstamps structure which
458 * is passed up the network stack
459 */
ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter * adapter)460 static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
461 {
462 struct ixgbe_hw *hw = &adapter->hw;
463 struct skb_shared_hwtstamps shhwtstamps;
464 u64 regval = 0, ns;
465 unsigned long flags;
466
467 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
468 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
469
470 spin_lock_irqsave(&adapter->tmreg_lock, flags);
471 ns = timecounter_cyc2time(&adapter->tc, regval);
472 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
473
474 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
475 shhwtstamps.hwtstamp = ns_to_ktime(ns);
476 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
477
478 dev_kfree_skb_any(adapter->ptp_tx_skb);
479 adapter->ptp_tx_skb = NULL;
480 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
481 }
482
483 /**
484 * ixgbe_ptp_tx_hwtstamp_work
485 * @work: pointer to the work struct
486 *
487 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
488 * timestamp has been taken for the current skb. It is necessary, because the
489 * descriptor's "done" bit does not correlate with the timestamp event.
490 */
ixgbe_ptp_tx_hwtstamp_work(struct work_struct * work)491 static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
492 {
493 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
494 ptp_tx_work);
495 struct ixgbe_hw *hw = &adapter->hw;
496 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
497 IXGBE_PTP_TX_TIMEOUT);
498 u32 tsynctxctl;
499
500 if (timeout) {
501 dev_kfree_skb_any(adapter->ptp_tx_skb);
502 adapter->ptp_tx_skb = NULL;
503 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
504 e_warn(drv, "clearing Tx Timestamp hang\n");
505 return;
506 }
507
508 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
509 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID)
510 ixgbe_ptp_tx_hwtstamp(adapter);
511 else
512 /* reschedule to keep checking if it's not available yet */
513 schedule_work(&adapter->ptp_tx_work);
514 }
515
516 /**
517 * ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp
518 * @adapter: pointer to adapter struct
519 * @skb: particular skb to send timestamp with
520 *
521 * if the timestamp is valid, we convert it into the timecounter ns
522 * value, then store that result into the shhwtstamps structure which
523 * is passed up the network stack
524 */
ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter * adapter,struct sk_buff * skb)525 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb)
526 {
527 struct ixgbe_hw *hw = &adapter->hw;
528 struct skb_shared_hwtstamps *shhwtstamps;
529 u64 regval = 0, ns;
530 u32 tsyncrxctl;
531 unsigned long flags;
532
533 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
534 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
535 return;
536
537 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
538 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
539
540 spin_lock_irqsave(&adapter->tmreg_lock, flags);
541 ns = timecounter_cyc2time(&adapter->tc, regval);
542 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
543
544 shhwtstamps = skb_hwtstamps(skb);
545 shhwtstamps->hwtstamp = ns_to_ktime(ns);
546
547 /* Update the last_rx_timestamp timer in order to enable watchdog check
548 * for error case of latched timestamp on a dropped packet.
549 */
550 adapter->last_rx_timestamp = jiffies;
551 }
552
ixgbe_ptp_get_ts_config(struct ixgbe_adapter * adapter,struct ifreq * ifr)553 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
554 {
555 struct hwtstamp_config *config = &adapter->tstamp_config;
556
557 return copy_to_user(ifr->ifr_data, config,
558 sizeof(*config)) ? -EFAULT : 0;
559 }
560
561 /**
562 * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
563 * @adapter: the private ixgbe adapter structure
564 * @config: the hwtstamp configuration requested
565 *
566 * Outgoing time stamping can be enabled and disabled. Play nice and
567 * disable it when requested, although it shouldn't cause any overhead
568 * when no packet needs it. At most one packet in the queue may be
569 * marked for time stamping, otherwise it would be impossible to tell
570 * for sure to which packet the hardware time stamp belongs.
571 *
572 * Incoming time stamping has to be configured via the hardware
573 * filters. Not all combinations are supported, in particular event
574 * type has to be specified. Matching the kind of event packet is
575 * not supported, with the exception of "all V2 events regardless of
576 * level 2 or 4".
577 *
578 * Since hardware always timestamps Path delay packets when timestamping V2
579 * packets, regardless of the type specified in the register, only use V2
580 * Event mode. This more accurately tells the user what the hardware is going
581 * to do anyways.
582 *
583 * Note: this may modify the hwtstamp configuration towards a more general
584 * mode, if required to support the specifically requested mode.
585 */
ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter * adapter,struct hwtstamp_config * config)586 static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
587 struct hwtstamp_config *config)
588 {
589 struct ixgbe_hw *hw = &adapter->hw;
590 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
591 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
592 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
593 bool is_l2 = false;
594 u32 regval;
595
596 /* reserved for future extensions */
597 if (config->flags)
598 return -EINVAL;
599
600 switch (config->tx_type) {
601 case HWTSTAMP_TX_OFF:
602 tsync_tx_ctl = 0;
603 case HWTSTAMP_TX_ON:
604 break;
605 default:
606 return -ERANGE;
607 }
608
609 switch (config->rx_filter) {
610 case HWTSTAMP_FILTER_NONE:
611 tsync_rx_ctl = 0;
612 tsync_rx_mtrl = 0;
613 break;
614 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
615 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
616 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
617 break;
618 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
619 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
620 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
621 break;
622 case HWTSTAMP_FILTER_PTP_V2_EVENT:
623 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
624 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
625 case HWTSTAMP_FILTER_PTP_V2_SYNC:
626 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
627 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
628 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
629 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
630 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
631 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
632 is_l2 = true;
633 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
634 break;
635 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
636 case HWTSTAMP_FILTER_ALL:
637 default:
638 /*
639 * register RXMTRL must be set in order to do V1 packets,
640 * therefore it is not possible to time stamp both V1 Sync and
641 * Delay_Req messages and hardware does not support
642 * timestamping all packets => return error
643 */
644 config->rx_filter = HWTSTAMP_FILTER_NONE;
645 return -ERANGE;
646 }
647
648 if (hw->mac.type == ixgbe_mac_82598EB) {
649 if (tsync_rx_ctl | tsync_tx_ctl)
650 return -ERANGE;
651 return 0;
652 }
653
654 /* define ethertype filter for timestamping L2 packets */
655 if (is_l2)
656 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
657 (IXGBE_ETQF_FILTER_EN | /* enable filter */
658 IXGBE_ETQF_1588 | /* enable timestamping */
659 ETH_P_1588)); /* 1588 eth protocol type */
660 else
661 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
662
663 /* enable/disable TX */
664 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
665 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
666 regval |= tsync_tx_ctl;
667 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
668
669 /* enable/disable RX */
670 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
671 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
672 regval |= tsync_rx_ctl;
673 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
674
675 /* define which PTP packets are time stamped */
676 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
677
678 IXGBE_WRITE_FLUSH(hw);
679
680 /* clear TX/RX time stamp registers, just to be sure */
681 regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
682 regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
683
684 return 0;
685 }
686
687 /**
688 * ixgbe_ptp_set_ts_config - user entry point for timestamp mode
689 * @adapter: pointer to adapter struct
690 * @ifreq: ioctl data
691 *
692 * Set hardware to requested mode. If unsupported, return an error with no
693 * changes. Otherwise, store the mode for future reference.
694 */
ixgbe_ptp_set_ts_config(struct ixgbe_adapter * adapter,struct ifreq * ifr)695 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
696 {
697 struct hwtstamp_config config;
698 int err;
699
700 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
701 return -EFAULT;
702
703 err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
704 if (err)
705 return err;
706
707 /* save these settings for future reference */
708 memcpy(&adapter->tstamp_config, &config,
709 sizeof(adapter->tstamp_config));
710
711 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
712 -EFAULT : 0;
713 }
714
715 /**
716 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
717 * @adapter: pointer to the adapter structure
718 *
719 * This function should be called to set the proper values for the TIMINCA
720 * register and tell the cyclecounter structure what the tick rate of SYSTIME
721 * is. It does not directly modify SYSTIME registers or the timecounter
722 * structure. It should be called whenever a new TIMINCA value is necessary,
723 * such as during initialization or when the link speed changes.
724 */
ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter * adapter)725 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
726 {
727 struct ixgbe_hw *hw = &adapter->hw;
728 u32 incval = 0;
729 u32 shift = 0;
730 unsigned long flags;
731
732 /**
733 * Scale the NIC cycle counter by a large factor so that
734 * relatively small corrections to the frequency can be added
735 * or subtracted. The drawbacks of a large factor include
736 * (a) the clock register overflows more quickly, (b) the cycle
737 * counter structure must be able to convert the systime value
738 * to nanoseconds using only a multiplier and a right-shift,
739 * and (c) the value must fit within the timinca register space
740 * => math based on internal DMA clock rate and available bits
741 *
742 * Note that when there is no link, internal DMA clock is same as when
743 * link speed is 10Gb. Set the registers correctly even when link is
744 * down to preserve the clock setting
745 */
746 switch (adapter->link_speed) {
747 case IXGBE_LINK_SPEED_100_FULL:
748 incval = IXGBE_INCVAL_100;
749 shift = IXGBE_INCVAL_SHIFT_100;
750 break;
751 case IXGBE_LINK_SPEED_1GB_FULL:
752 incval = IXGBE_INCVAL_1GB;
753 shift = IXGBE_INCVAL_SHIFT_1GB;
754 break;
755 case IXGBE_LINK_SPEED_10GB_FULL:
756 default:
757 incval = IXGBE_INCVAL_10GB;
758 shift = IXGBE_INCVAL_SHIFT_10GB;
759 break;
760 }
761
762 /**
763 * Modify the calculated values to fit within the correct
764 * number of bits specified by the hardware. The 82599 doesn't
765 * have the same space as the X540, so bitshift the calculated
766 * values to fit.
767 */
768 switch (hw->mac.type) {
769 case ixgbe_mac_X540:
770 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
771 break;
772 case ixgbe_mac_82599EB:
773 incval >>= IXGBE_INCVAL_SHIFT_82599;
774 shift -= IXGBE_INCVAL_SHIFT_82599;
775 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
776 (1 << IXGBE_INCPER_SHIFT_82599) |
777 incval);
778 break;
779 default:
780 /* other devices aren't supported */
781 return;
782 }
783
784 /* update the base incval used to calculate frequency adjustment */
785 ACCESS_ONCE(adapter->base_incval) = incval;
786 smp_mb();
787
788 /* need lock to prevent incorrect read while modifying cyclecounter */
789 spin_lock_irqsave(&adapter->tmreg_lock, flags);
790
791 memset(&adapter->cc, 0, sizeof(adapter->cc));
792 adapter->cc.read = ixgbe_ptp_read;
793 adapter->cc.mask = CYCLECOUNTER_MASK(64);
794 adapter->cc.shift = shift;
795 adapter->cc.mult = 1;
796
797 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
798 }
799
800 /**
801 * ixgbe_ptp_reset
802 * @adapter: the ixgbe private board structure
803 *
804 * When the MAC resets, all the hardware bits for timesync are reset. This
805 * function is used to re-enable the device for PTP based on current settings.
806 * We do lose the current clock time, so just reset the cyclecounter to the
807 * system real clock time.
808 *
809 * This function will maintain hwtstamp_config settings, and resets the SDP
810 * output if it was enabled.
811 */
ixgbe_ptp_reset(struct ixgbe_adapter * adapter)812 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
813 {
814 struct ixgbe_hw *hw = &adapter->hw;
815 unsigned long flags;
816
817 /* set SYSTIME registers to 0 just in case */
818 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000);
819 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
820 IXGBE_WRITE_FLUSH(hw);
821
822 /* reset the hardware timestamping mode */
823 ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
824
825 ixgbe_ptp_start_cyclecounter(adapter);
826
827 spin_lock_irqsave(&adapter->tmreg_lock, flags);
828
829 /* reset the ns time counter */
830 timecounter_init(&adapter->tc, &adapter->cc,
831 ktime_to_ns(ktime_get_real()));
832
833 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
834
835 /*
836 * Now that the shift has been calculated and the systime
837 * registers reset, (re-)enable the Clock out feature
838 */
839 ixgbe_ptp_setup_sdp(adapter);
840 }
841
842 /**
843 * ixgbe_ptp_create_clock
844 * @adapter: the ixgbe private adapter structure
845 *
846 * This function performs setup of the user entry point function table and
847 * initializes the PTP clock device, which is used to access the clock-like
848 * features of the PTP core. It will be called by ixgbe_ptp_init, only if
849 * there isn't already a clock device (such as after a suspend/resume cycle,
850 * where the clock device wasn't destroyed).
851 */
ixgbe_ptp_create_clock(struct ixgbe_adapter * adapter)852 static int ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
853 {
854 struct net_device *netdev = adapter->netdev;
855 long err;
856
857 /* do nothing if we already have a clock device */
858 if (!IS_ERR_OR_NULL(adapter->ptp_clock))
859 return 0;
860
861 switch (adapter->hw.mac.type) {
862 case ixgbe_mac_X540:
863 snprintf(adapter->ptp_caps.name,
864 sizeof(adapter->ptp_caps.name),
865 "%s", netdev->name);
866 adapter->ptp_caps.owner = THIS_MODULE;
867 adapter->ptp_caps.max_adj = 250000000;
868 adapter->ptp_caps.n_alarm = 0;
869 adapter->ptp_caps.n_ext_ts = 0;
870 adapter->ptp_caps.n_per_out = 0;
871 adapter->ptp_caps.pps = 1;
872 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
873 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
874 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
875 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
876 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
877 break;
878 case ixgbe_mac_82599EB:
879 snprintf(adapter->ptp_caps.name,
880 sizeof(adapter->ptp_caps.name),
881 "%s", netdev->name);
882 adapter->ptp_caps.owner = THIS_MODULE;
883 adapter->ptp_caps.max_adj = 250000000;
884 adapter->ptp_caps.n_alarm = 0;
885 adapter->ptp_caps.n_ext_ts = 0;
886 adapter->ptp_caps.n_per_out = 0;
887 adapter->ptp_caps.pps = 0;
888 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
889 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
890 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
891 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
892 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
893 break;
894 default:
895 adapter->ptp_clock = NULL;
896 return -EOPNOTSUPP;
897 }
898
899 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
900 &adapter->pdev->dev);
901 if (IS_ERR(adapter->ptp_clock)) {
902 err = PTR_ERR(adapter->ptp_clock);
903 adapter->ptp_clock = NULL;
904 e_dev_err("ptp_clock_register failed\n");
905 return err;
906 } else
907 e_dev_info("registered PHC device on %s\n", netdev->name);
908
909 /* set default timestamp mode to disabled here. We do this in
910 * create_clock instead of init, because we don't want to override the
911 * previous settings during a resume cycle.
912 */
913 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
914 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
915
916 return 0;
917 }
918
919 /**
920 * ixgbe_ptp_init
921 * @adapter: the ixgbe private adapter structure
922 *
923 * This function performs the required steps for enabling PTP
924 * support. If PTP support has already been loaded it simply calls the
925 * cyclecounter init routine and exits.
926 */
ixgbe_ptp_init(struct ixgbe_adapter * adapter)927 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
928 {
929 /* initialize the spin lock first since we can't control when a user
930 * will call the entry functions once we have initialized the clock
931 * device
932 */
933 spin_lock_init(&adapter->tmreg_lock);
934
935 /* obtain a PTP device, or re-use an existing device */
936 if (ixgbe_ptp_create_clock(adapter))
937 return;
938
939 /* we have a clock so we can initialize work now */
940 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
941
942 /* reset the PTP related hardware bits */
943 ixgbe_ptp_reset(adapter);
944
945 /* enter the IXGBE_PTP_RUNNING state */
946 set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
947
948 return;
949 }
950
951 /**
952 * ixgbe_ptp_suspend - stop PTP work items
953 * @ adapter: pointer to adapter struct
954 *
955 * this function suspends PTP activity, and prevents more PTP work from being
956 * generated, but does not destroy the PTP clock device.
957 */
ixgbe_ptp_suspend(struct ixgbe_adapter * adapter)958 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
959 {
960 /* Leave the IXGBE_PTP_RUNNING state. */
961 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
962 return;
963
964 /* since this might be called in suspend, we don't clear the state,
965 * but simply reset the auxiliary PPS signal control register
966 */
967 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TSAUXC, 0x0);
968
969 /* ensure that we cancel any pending PTP Tx work item in progress */
970 cancel_work_sync(&adapter->ptp_tx_work);
971 if (adapter->ptp_tx_skb) {
972 dev_kfree_skb_any(adapter->ptp_tx_skb);
973 adapter->ptp_tx_skb = NULL;
974 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
975 }
976 }
977
978 /**
979 * ixgbe_ptp_stop - close the PTP device
980 * @adapter: pointer to adapter struct
981 *
982 * completely destroy the PTP device, should only be called when the device is
983 * being fully closed.
984 */
ixgbe_ptp_stop(struct ixgbe_adapter * adapter)985 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
986 {
987 /* first, suspend PTP activity */
988 ixgbe_ptp_suspend(adapter);
989
990 /* disable the PTP clock device */
991 if (adapter->ptp_clock) {
992 ptp_clock_unregister(adapter->ptp_clock);
993 adapter->ptp_clock = NULL;
994 e_dev_info("removed PHC on %s\n",
995 adapter->netdev->name);
996 }
997 }
998