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1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
44 
45 #include "mlx5_core.h"
46 
47 enum {
48 	CMD_IF_REV = 5,
49 };
50 
51 enum {
52 	CMD_MODE_POLLING,
53 	CMD_MODE_EVENTS
54 };
55 
56 enum {
57 	NUM_LONG_LISTS	  = 2,
58 	NUM_MED_LISTS	  = 64,
59 	LONG_LIST_SIZE	  = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
60 				MLX5_CMD_DATA_BLOCK_SIZE,
61 	MED_LIST_SIZE	  = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
62 };
63 
64 enum {
65 	MLX5_CMD_DELIVERY_STAT_OK			= 0x0,
66 	MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR		= 0x1,
67 	MLX5_CMD_DELIVERY_STAT_TOK_ERR			= 0x2,
68 	MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR		= 0x3,
69 	MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR	= 0x4,
70 	MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR		= 0x5,
71 	MLX5_CMD_DELIVERY_STAT_FW_ERR			= 0x6,
72 	MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR		= 0x7,
73 	MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR		= 0x8,
74 	MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR	= 0x9,
75 	MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR		= 0x10,
76 };
77 
alloc_cmd(struct mlx5_cmd * cmd,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t cbk,void * context,int page_queue)78 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
79 					   struct mlx5_cmd_msg *in,
80 					   struct mlx5_cmd_msg *out,
81 					   void *uout, int uout_size,
82 					   mlx5_cmd_cbk_t cbk,
83 					   void *context, int page_queue)
84 {
85 	gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
86 	struct mlx5_cmd_work_ent *ent;
87 
88 	ent = kzalloc(sizeof(*ent), alloc_flags);
89 	if (!ent)
90 		return ERR_PTR(-ENOMEM);
91 
92 	ent->in		= in;
93 	ent->out	= out;
94 	ent->uout	= uout;
95 	ent->uout_size	= uout_size;
96 	ent->callback	= cbk;
97 	ent->context	= context;
98 	ent->cmd	= cmd;
99 	ent->page_queue = page_queue;
100 
101 	return ent;
102 }
103 
alloc_token(struct mlx5_cmd * cmd)104 static u8 alloc_token(struct mlx5_cmd *cmd)
105 {
106 	u8 token;
107 
108 	spin_lock(&cmd->token_lock);
109 	cmd->token++;
110 	if (cmd->token == 0)
111 		cmd->token++;
112 	token = cmd->token;
113 	spin_unlock(&cmd->token_lock);
114 
115 	return token;
116 }
117 
alloc_ent(struct mlx5_cmd * cmd)118 static int alloc_ent(struct mlx5_cmd *cmd)
119 {
120 	unsigned long flags;
121 	int ret;
122 
123 	spin_lock_irqsave(&cmd->alloc_lock, flags);
124 	ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
125 	if (ret < cmd->max_reg_cmds)
126 		clear_bit(ret, &cmd->bitmask);
127 	spin_unlock_irqrestore(&cmd->alloc_lock, flags);
128 
129 	return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
130 }
131 
free_ent(struct mlx5_cmd * cmd,int idx)132 static void free_ent(struct mlx5_cmd *cmd, int idx)
133 {
134 	unsigned long flags;
135 
136 	spin_lock_irqsave(&cmd->alloc_lock, flags);
137 	set_bit(idx, &cmd->bitmask);
138 	spin_unlock_irqrestore(&cmd->alloc_lock, flags);
139 }
140 
get_inst(struct mlx5_cmd * cmd,int idx)141 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
142 {
143 	return cmd->cmd_buf + (idx << cmd->log_stride);
144 }
145 
xor8_buf(void * buf,size_t offset,int len)146 static u8 xor8_buf(void *buf, size_t offset, int len)
147 {
148 	u8 *ptr = buf;
149 	u8 sum = 0;
150 	int i;
151 	int end = len + offset;
152 
153 	for (i = offset; i < end; i++)
154 		sum ^= ptr[i];
155 
156 	return sum;
157 }
158 
verify_block_sig(struct mlx5_cmd_prot_block * block)159 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
160 {
161 	size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
162 	int xor_len = sizeof(*block) - sizeof(block->data) - 1;
163 
164 	if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
165 		return -EINVAL;
166 
167 	if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
168 		return -EINVAL;
169 
170 	return 0;
171 }
172 
calc_block_sig(struct mlx5_cmd_prot_block * block)173 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
174 {
175 	int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
176 	size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
177 
178 	block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
179 	block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
180 }
181 
calc_chain_sig(struct mlx5_cmd_msg * msg)182 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
183 {
184 	struct mlx5_cmd_mailbox *next = msg->next;
185 	int size = msg->len;
186 	int blen = size - min_t(int, sizeof(msg->first.data), size);
187 	int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
188 		/ MLX5_CMD_DATA_BLOCK_SIZE;
189 	int i = 0;
190 
191 	for (i = 0; i < n && next; i++)  {
192 		calc_block_sig(next->buf);
193 		next = next->next;
194 	}
195 }
196 
set_signature(struct mlx5_cmd_work_ent * ent,int csum)197 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
198 {
199 	ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
200 	if (csum) {
201 		calc_chain_sig(ent->in);
202 		calc_chain_sig(ent->out);
203 	}
204 }
205 
poll_timeout(struct mlx5_cmd_work_ent * ent)206 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
207 {
208 	unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
209 	u8 own;
210 
211 	do {
212 		own = ent->lay->status_own;
213 		if (!(own & CMD_OWNER_HW)) {
214 			ent->ret = 0;
215 			return;
216 		}
217 		usleep_range(5000, 10000);
218 	} while (time_before(jiffies, poll_end));
219 
220 	ent->ret = -ETIMEDOUT;
221 }
222 
free_cmd(struct mlx5_cmd_work_ent * ent)223 static void free_cmd(struct mlx5_cmd_work_ent *ent)
224 {
225 	kfree(ent);
226 }
227 
228 
verify_signature(struct mlx5_cmd_work_ent * ent)229 static int verify_signature(struct mlx5_cmd_work_ent *ent)
230 {
231 	struct mlx5_cmd_mailbox *next = ent->out->next;
232 	int err;
233 	u8 sig;
234 	int size = ent->out->len;
235 	int blen = size - min_t(int, sizeof(ent->out->first.data), size);
236 	int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
237 		/ MLX5_CMD_DATA_BLOCK_SIZE;
238 	int i = 0;
239 
240 	sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
241 	if (sig != 0xff)
242 		return -EINVAL;
243 
244 	for (i = 0; i < n && next; i++) {
245 		err = verify_block_sig(next->buf);
246 		if (err)
247 			return err;
248 
249 		next = next->next;
250 	}
251 
252 	return 0;
253 }
254 
dump_buf(void * buf,int size,int data_only,int offset)255 static void dump_buf(void *buf, int size, int data_only, int offset)
256 {
257 	__be32 *p = buf;
258 	int i;
259 
260 	for (i = 0; i < size; i += 16) {
261 		pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
262 			 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
263 			 be32_to_cpu(p[3]));
264 		p += 4;
265 		offset += 16;
266 	}
267 	if (!data_only)
268 		pr_debug("\n");
269 }
270 
271 enum {
272 	MLX5_DRIVER_STATUS_ABORTED = 0xfe,
273 	MLX5_DRIVER_SYND = 0xbadd00de,
274 };
275 
mlx5_internal_err_ret_value(struct mlx5_core_dev * dev,u16 op,u32 * synd,u8 * status)276 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
277 				       u32 *synd, u8 *status)
278 {
279 	*synd = 0;
280 	*status = 0;
281 
282 	switch (op) {
283 	case MLX5_CMD_OP_TEARDOWN_HCA:
284 	case MLX5_CMD_OP_DISABLE_HCA:
285 	case MLX5_CMD_OP_MANAGE_PAGES:
286 	case MLX5_CMD_OP_DESTROY_MKEY:
287 	case MLX5_CMD_OP_DESTROY_EQ:
288 	case MLX5_CMD_OP_DESTROY_CQ:
289 	case MLX5_CMD_OP_DESTROY_QP:
290 	case MLX5_CMD_OP_DESTROY_PSV:
291 	case MLX5_CMD_OP_DESTROY_SRQ:
292 	case MLX5_CMD_OP_DESTROY_XRC_SRQ:
293 	case MLX5_CMD_OP_DESTROY_DCT:
294 	case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
295 	case MLX5_CMD_OP_DEALLOC_PD:
296 	case MLX5_CMD_OP_DEALLOC_UAR:
297 	case MLX5_CMD_OP_DETTACH_FROM_MCG:
298 	case MLX5_CMD_OP_DEALLOC_XRCD:
299 	case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
300 	case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
301 	case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
302 	case MLX5_CMD_OP_DESTROY_TIR:
303 	case MLX5_CMD_OP_DESTROY_SQ:
304 	case MLX5_CMD_OP_DESTROY_RQ:
305 	case MLX5_CMD_OP_DESTROY_RMP:
306 	case MLX5_CMD_OP_DESTROY_TIS:
307 	case MLX5_CMD_OP_DESTROY_RQT:
308 	case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
309 	case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
310 	case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
311 		return MLX5_CMD_STAT_OK;
312 
313 	case MLX5_CMD_OP_QUERY_HCA_CAP:
314 	case MLX5_CMD_OP_QUERY_ADAPTER:
315 	case MLX5_CMD_OP_INIT_HCA:
316 	case MLX5_CMD_OP_ENABLE_HCA:
317 	case MLX5_CMD_OP_QUERY_PAGES:
318 	case MLX5_CMD_OP_SET_HCA_CAP:
319 	case MLX5_CMD_OP_QUERY_ISSI:
320 	case MLX5_CMD_OP_SET_ISSI:
321 	case MLX5_CMD_OP_CREATE_MKEY:
322 	case MLX5_CMD_OP_QUERY_MKEY:
323 	case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
324 	case MLX5_CMD_OP_PAGE_FAULT_RESUME:
325 	case MLX5_CMD_OP_CREATE_EQ:
326 	case MLX5_CMD_OP_QUERY_EQ:
327 	case MLX5_CMD_OP_GEN_EQE:
328 	case MLX5_CMD_OP_CREATE_CQ:
329 	case MLX5_CMD_OP_QUERY_CQ:
330 	case MLX5_CMD_OP_MODIFY_CQ:
331 	case MLX5_CMD_OP_CREATE_QP:
332 	case MLX5_CMD_OP_RST2INIT_QP:
333 	case MLX5_CMD_OP_INIT2RTR_QP:
334 	case MLX5_CMD_OP_RTR2RTS_QP:
335 	case MLX5_CMD_OP_RTS2RTS_QP:
336 	case MLX5_CMD_OP_SQERR2RTS_QP:
337 	case MLX5_CMD_OP_2ERR_QP:
338 	case MLX5_CMD_OP_2RST_QP:
339 	case MLX5_CMD_OP_QUERY_QP:
340 	case MLX5_CMD_OP_SQD_RTS_QP:
341 	case MLX5_CMD_OP_INIT2INIT_QP:
342 	case MLX5_CMD_OP_CREATE_PSV:
343 	case MLX5_CMD_OP_CREATE_SRQ:
344 	case MLX5_CMD_OP_QUERY_SRQ:
345 	case MLX5_CMD_OP_ARM_RQ:
346 	case MLX5_CMD_OP_CREATE_XRC_SRQ:
347 	case MLX5_CMD_OP_QUERY_XRC_SRQ:
348 	case MLX5_CMD_OP_ARM_XRC_SRQ:
349 	case MLX5_CMD_OP_CREATE_DCT:
350 	case MLX5_CMD_OP_DRAIN_DCT:
351 	case MLX5_CMD_OP_QUERY_DCT:
352 	case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
353 	case MLX5_CMD_OP_QUERY_VPORT_STATE:
354 	case MLX5_CMD_OP_MODIFY_VPORT_STATE:
355 	case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
356 	case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
357 	case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
358 	case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
359 	case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
360 	case MLX5_CMD_OP_SET_ROCE_ADDRESS:
361 	case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
362 	case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
363 	case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
364 	case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
365 	case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
366 	case MLX5_CMD_OP_ALLOC_Q_COUNTER:
367 	case MLX5_CMD_OP_QUERY_Q_COUNTER:
368 	case MLX5_CMD_OP_ALLOC_PD:
369 	case MLX5_CMD_OP_ALLOC_UAR:
370 	case MLX5_CMD_OP_CONFIG_INT_MODERATION:
371 	case MLX5_CMD_OP_ACCESS_REG:
372 	case MLX5_CMD_OP_ATTACH_TO_MCG:
373 	case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
374 	case MLX5_CMD_OP_MAD_IFC:
375 	case MLX5_CMD_OP_QUERY_MAD_DEMUX:
376 	case MLX5_CMD_OP_SET_MAD_DEMUX:
377 	case MLX5_CMD_OP_NOP:
378 	case MLX5_CMD_OP_ALLOC_XRCD:
379 	case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
380 	case MLX5_CMD_OP_QUERY_CONG_STATUS:
381 	case MLX5_CMD_OP_MODIFY_CONG_STATUS:
382 	case MLX5_CMD_OP_QUERY_CONG_PARAMS:
383 	case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
384 	case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
385 	case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
386 	case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
387 	case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
388 	case MLX5_CMD_OP_CREATE_TIR:
389 	case MLX5_CMD_OP_MODIFY_TIR:
390 	case MLX5_CMD_OP_QUERY_TIR:
391 	case MLX5_CMD_OP_CREATE_SQ:
392 	case MLX5_CMD_OP_MODIFY_SQ:
393 	case MLX5_CMD_OP_QUERY_SQ:
394 	case MLX5_CMD_OP_CREATE_RQ:
395 	case MLX5_CMD_OP_MODIFY_RQ:
396 	case MLX5_CMD_OP_QUERY_RQ:
397 	case MLX5_CMD_OP_CREATE_RMP:
398 	case MLX5_CMD_OP_MODIFY_RMP:
399 	case MLX5_CMD_OP_QUERY_RMP:
400 	case MLX5_CMD_OP_CREATE_TIS:
401 	case MLX5_CMD_OP_MODIFY_TIS:
402 	case MLX5_CMD_OP_QUERY_TIS:
403 	case MLX5_CMD_OP_CREATE_RQT:
404 	case MLX5_CMD_OP_MODIFY_RQT:
405 	case MLX5_CMD_OP_QUERY_RQT:
406 	case MLX5_CMD_OP_CREATE_FLOW_TABLE:
407 	case MLX5_CMD_OP_QUERY_FLOW_TABLE:
408 	case MLX5_CMD_OP_CREATE_FLOW_GROUP:
409 	case MLX5_CMD_OP_QUERY_FLOW_GROUP:
410 	case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
411 	case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
412 		*status = MLX5_DRIVER_STATUS_ABORTED;
413 		*synd = MLX5_DRIVER_SYND;
414 		return -EIO;
415 	default:
416 		mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
417 		return -EINVAL;
418 	}
419 }
420 
mlx5_command_str(int command)421 const char *mlx5_command_str(int command)
422 {
423 	switch (command) {
424 	case MLX5_CMD_OP_QUERY_HCA_CAP:
425 		return "QUERY_HCA_CAP";
426 
427 	case MLX5_CMD_OP_SET_HCA_CAP:
428 		return "SET_HCA_CAP";
429 
430 	case MLX5_CMD_OP_QUERY_ADAPTER:
431 		return "QUERY_ADAPTER";
432 
433 	case MLX5_CMD_OP_INIT_HCA:
434 		return "INIT_HCA";
435 
436 	case MLX5_CMD_OP_TEARDOWN_HCA:
437 		return "TEARDOWN_HCA";
438 
439 	case MLX5_CMD_OP_ENABLE_HCA:
440 		return "MLX5_CMD_OP_ENABLE_HCA";
441 
442 	case MLX5_CMD_OP_DISABLE_HCA:
443 		return "MLX5_CMD_OP_DISABLE_HCA";
444 
445 	case MLX5_CMD_OP_QUERY_PAGES:
446 		return "QUERY_PAGES";
447 
448 	case MLX5_CMD_OP_MANAGE_PAGES:
449 		return "MANAGE_PAGES";
450 
451 	case MLX5_CMD_OP_CREATE_MKEY:
452 		return "CREATE_MKEY";
453 
454 	case MLX5_CMD_OP_QUERY_MKEY:
455 		return "QUERY_MKEY";
456 
457 	case MLX5_CMD_OP_DESTROY_MKEY:
458 		return "DESTROY_MKEY";
459 
460 	case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
461 		return "QUERY_SPECIAL_CONTEXTS";
462 
463 	case MLX5_CMD_OP_CREATE_EQ:
464 		return "CREATE_EQ";
465 
466 	case MLX5_CMD_OP_DESTROY_EQ:
467 		return "DESTROY_EQ";
468 
469 	case MLX5_CMD_OP_QUERY_EQ:
470 		return "QUERY_EQ";
471 
472 	case MLX5_CMD_OP_CREATE_CQ:
473 		return "CREATE_CQ";
474 
475 	case MLX5_CMD_OP_DESTROY_CQ:
476 		return "DESTROY_CQ";
477 
478 	case MLX5_CMD_OP_QUERY_CQ:
479 		return "QUERY_CQ";
480 
481 	case MLX5_CMD_OP_MODIFY_CQ:
482 		return "MODIFY_CQ";
483 
484 	case MLX5_CMD_OP_CREATE_QP:
485 		return "CREATE_QP";
486 
487 	case MLX5_CMD_OP_DESTROY_QP:
488 		return "DESTROY_QP";
489 
490 	case MLX5_CMD_OP_RST2INIT_QP:
491 		return "RST2INIT_QP";
492 
493 	case MLX5_CMD_OP_INIT2RTR_QP:
494 		return "INIT2RTR_QP";
495 
496 	case MLX5_CMD_OP_RTR2RTS_QP:
497 		return "RTR2RTS_QP";
498 
499 	case MLX5_CMD_OP_RTS2RTS_QP:
500 		return "RTS2RTS_QP";
501 
502 	case MLX5_CMD_OP_SQERR2RTS_QP:
503 		return "SQERR2RTS_QP";
504 
505 	case MLX5_CMD_OP_2ERR_QP:
506 		return "2ERR_QP";
507 
508 	case MLX5_CMD_OP_2RST_QP:
509 		return "2RST_QP";
510 
511 	case MLX5_CMD_OP_QUERY_QP:
512 		return "QUERY_QP";
513 
514 	case MLX5_CMD_OP_MAD_IFC:
515 		return "MAD_IFC";
516 
517 	case MLX5_CMD_OP_INIT2INIT_QP:
518 		return "INIT2INIT_QP";
519 
520 	case MLX5_CMD_OP_CREATE_PSV:
521 		return "CREATE_PSV";
522 
523 	case MLX5_CMD_OP_DESTROY_PSV:
524 		return "DESTROY_PSV";
525 
526 	case MLX5_CMD_OP_CREATE_SRQ:
527 		return "CREATE_SRQ";
528 
529 	case MLX5_CMD_OP_DESTROY_SRQ:
530 		return "DESTROY_SRQ";
531 
532 	case MLX5_CMD_OP_QUERY_SRQ:
533 		return "QUERY_SRQ";
534 
535 	case MLX5_CMD_OP_ARM_RQ:
536 		return "ARM_RQ";
537 
538 	case MLX5_CMD_OP_CREATE_XRC_SRQ:
539 		return "CREATE_XRC_SRQ";
540 
541 	case MLX5_CMD_OP_DESTROY_XRC_SRQ:
542 		return "DESTROY_XRC_SRQ";
543 
544 	case MLX5_CMD_OP_QUERY_XRC_SRQ:
545 		return "QUERY_XRC_SRQ";
546 
547 	case MLX5_CMD_OP_ARM_XRC_SRQ:
548 		return "ARM_XRC_SRQ";
549 
550 	case MLX5_CMD_OP_ALLOC_PD:
551 		return "ALLOC_PD";
552 
553 	case MLX5_CMD_OP_DEALLOC_PD:
554 		return "DEALLOC_PD";
555 
556 	case MLX5_CMD_OP_ALLOC_UAR:
557 		return "ALLOC_UAR";
558 
559 	case MLX5_CMD_OP_DEALLOC_UAR:
560 		return "DEALLOC_UAR";
561 
562 	case MLX5_CMD_OP_ATTACH_TO_MCG:
563 		return "ATTACH_TO_MCG";
564 
565 	case MLX5_CMD_OP_DETTACH_FROM_MCG:
566 		return "DETTACH_FROM_MCG";
567 
568 	case MLX5_CMD_OP_ALLOC_XRCD:
569 		return "ALLOC_XRCD";
570 
571 	case MLX5_CMD_OP_DEALLOC_XRCD:
572 		return "DEALLOC_XRCD";
573 
574 	case MLX5_CMD_OP_ACCESS_REG:
575 		return "MLX5_CMD_OP_ACCESS_REG";
576 
577 	default: return "unknown command opcode";
578 	}
579 }
580 
dump_command(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent,int input)581 static void dump_command(struct mlx5_core_dev *dev,
582 			 struct mlx5_cmd_work_ent *ent, int input)
583 {
584 	u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
585 	struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
586 	struct mlx5_cmd_mailbox *next = msg->next;
587 	int data_only;
588 	u32 offset = 0;
589 	int dump_len;
590 
591 	data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
592 
593 	if (data_only)
594 		mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
595 				   "dump command data %s(0x%x) %s\n",
596 				   mlx5_command_str(op), op,
597 				   input ? "INPUT" : "OUTPUT");
598 	else
599 		mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
600 			      mlx5_command_str(op), op,
601 			      input ? "INPUT" : "OUTPUT");
602 
603 	if (data_only) {
604 		if (input) {
605 			dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
606 			offset += sizeof(ent->lay->in);
607 		} else {
608 			dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
609 			offset += sizeof(ent->lay->out);
610 		}
611 	} else {
612 		dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
613 		offset += sizeof(*ent->lay);
614 	}
615 
616 	while (next && offset < msg->len) {
617 		if (data_only) {
618 			dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
619 			dump_buf(next->buf, dump_len, 1, offset);
620 			offset += MLX5_CMD_DATA_BLOCK_SIZE;
621 		} else {
622 			mlx5_core_dbg(dev, "command block:\n");
623 			dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
624 			offset += sizeof(struct mlx5_cmd_prot_block);
625 		}
626 		next = next->next;
627 	}
628 
629 	if (data_only)
630 		pr_debug("\n");
631 }
632 
633 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
634 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
635 			      struct mlx5_cmd_msg *msg);
636 
msg_to_opcode(struct mlx5_cmd_msg * in)637 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
638 {
639 	struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
640 
641 	return be16_to_cpu(hdr->opcode);
642 }
643 
cb_timeout_handler(struct work_struct * work)644 static void cb_timeout_handler(struct work_struct *work)
645 {
646 	struct delayed_work *dwork = container_of(work, struct delayed_work,
647 						  work);
648 	struct mlx5_cmd_work_ent *ent = container_of(dwork,
649 						     struct mlx5_cmd_work_ent,
650 						     cb_timeout_work);
651 	struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
652 						 cmd);
653 
654 	ent->ret = -ETIMEDOUT;
655 	mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
656 		       mlx5_command_str(msg_to_opcode(ent->in)),
657 		       msg_to_opcode(ent->in));
658 	mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
659 }
660 
cmd_work_handler(struct work_struct * work)661 static void cmd_work_handler(struct work_struct *work)
662 {
663 	struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
664 	struct mlx5_cmd *cmd = ent->cmd;
665 	struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
666 	unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
667 	struct mlx5_cmd_layout *lay;
668 	struct semaphore *sem;
669 	unsigned long flags;
670 	int alloc_ret;
671 	int cmd_mode;
672 
673 	complete(&ent->handling);
674 	sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
675 	down(sem);
676 	if (!ent->page_queue) {
677 		alloc_ret = alloc_ent(cmd);
678 		if (alloc_ret < 0) {
679 			if (ent->callback) {
680 				ent->callback(-EAGAIN, ent->context);
681 				mlx5_free_cmd_msg(dev, ent->out);
682 				free_msg(dev, ent->in);
683 				free_cmd(ent);
684 			} else {
685 				ent->ret = -EAGAIN;
686 				complete(&ent->done);
687 			}
688 			mlx5_core_err(dev, "failed to allocate command entry\n");
689 			up(sem);
690 			return;
691 		}
692 		ent->idx = alloc_ret;
693 	} else {
694 		ent->idx = cmd->max_reg_cmds;
695 		spin_lock_irqsave(&cmd->alloc_lock, flags);
696 		clear_bit(ent->idx, &cmd->bitmask);
697 		spin_unlock_irqrestore(&cmd->alloc_lock, flags);
698 	}
699 
700 	cmd->ent_arr[ent->idx] = ent;
701 	lay = get_inst(cmd, ent->idx);
702 	ent->lay = lay;
703 	memset(lay, 0, sizeof(*lay));
704 	memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
705 	ent->op = be32_to_cpu(lay->in[0]) >> 16;
706 	if (ent->in->next)
707 		lay->in_ptr = cpu_to_be64(ent->in->next->dma);
708 	lay->inlen = cpu_to_be32(ent->in->len);
709 	if (ent->out->next)
710 		lay->out_ptr = cpu_to_be64(ent->out->next->dma);
711 	lay->outlen = cpu_to_be32(ent->out->len);
712 	lay->type = MLX5_PCI_CMD_XPORT;
713 	lay->token = ent->token;
714 	lay->status_own = CMD_OWNER_HW;
715 	set_signature(ent, !cmd->checksum_disabled);
716 	dump_command(dev, ent, 1);
717 	ent->ts1 = ktime_get_ns();
718 	cmd_mode = cmd->mode;
719 
720 	if (ent->callback)
721 		schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
722 
723 	/* ring doorbell after the descriptor is valid */
724 	mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
725 	wmb();
726 	iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
727 	mmiowb();
728 	/* if not in polling don't use ent after this point */
729 	if (cmd_mode == CMD_MODE_POLLING) {
730 		poll_timeout(ent);
731 		/* make sure we read the descriptor after ownership is SW */
732 		rmb();
733 		mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
734 	}
735 }
736 
deliv_status_to_str(u8 status)737 static const char *deliv_status_to_str(u8 status)
738 {
739 	switch (status) {
740 	case MLX5_CMD_DELIVERY_STAT_OK:
741 		return "no errors";
742 	case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
743 		return "signature error";
744 	case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
745 		return "token error";
746 	case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
747 		return "bad block number";
748 	case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
749 		return "output pointer not aligned to block size";
750 	case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
751 		return "input pointer not aligned to block size";
752 	case MLX5_CMD_DELIVERY_STAT_FW_ERR:
753 		return "firmware internal error";
754 	case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
755 		return "command input length error";
756 	case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
757 		return "command ouput length error";
758 	case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
759 		return "reserved fields not cleared";
760 	case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
761 		return "bad command descriptor type";
762 	default:
763 		return "unknown status code";
764 	}
765 }
766 
wait_func(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)767 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
768 {
769 	unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
770 	struct mlx5_cmd *cmd = &dev->cmd;
771 	int err;
772 
773 	if (!wait_for_completion_timeout(&ent->handling, timeout) &&
774 	    cancel_work_sync(&ent->work)) {
775 		ent->ret = -ECANCELED;
776 		goto out_err;
777 	}
778 
779 	if (cmd->mode == CMD_MODE_POLLING) {
780 		wait_for_completion(&ent->done);
781 	} else if (!wait_for_completion_timeout(&ent->done, timeout)) {
782 		ent->ret = -ETIMEDOUT;
783 		mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
784 	}
785 
786 out_err:
787 	err = ent->ret;
788 
789 	if (err == -ETIMEDOUT) {
790 		mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
791 			       mlx5_command_str(msg_to_opcode(ent->in)),
792 			       msg_to_opcode(ent->in));
793 	} else if (err == -ECANCELED) {
794 		mlx5_core_warn(dev, "%s(0x%x) canceled on out of queue timeout.\n",
795 			       mlx5_command_str(msg_to_opcode(ent->in)),
796 			       msg_to_opcode(ent->in));
797 	}
798 	mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
799 		      err, deliv_status_to_str(ent->status), ent->status);
800 
801 	return err;
802 }
803 
get_synd_ptr(struct mlx5_outbox_hdr * out)804 static __be32 *get_synd_ptr(struct mlx5_outbox_hdr *out)
805 {
806 	return &out->syndrome;
807 }
808 
get_status_ptr(struct mlx5_outbox_hdr * out)809 static u8 *get_status_ptr(struct mlx5_outbox_hdr *out)
810 {
811 	return &out->status;
812 }
813 
814 /*  Notes:
815  *    1. Callback functions may not sleep
816  *    2. page queue commands do not support asynchrous completion
817  */
mlx5_cmd_invoke(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t callback,void * context,int page_queue,u8 * status,u8 token)818 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
819 			   struct mlx5_cmd_msg *out, void *uout, int uout_size,
820 			   mlx5_cmd_cbk_t callback,
821 			   void *context, int page_queue, u8 *status,
822 			   u8 token)
823 {
824 	struct mlx5_cmd *cmd = &dev->cmd;
825 	struct mlx5_cmd_work_ent *ent;
826 	struct mlx5_cmd_stats *stats;
827 	int err = 0;
828 	s64 ds;
829 	u16 op;
830 
831 	if (callback && page_queue)
832 		return -EINVAL;
833 
834 	ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
835 			page_queue);
836 	if (IS_ERR(ent))
837 		return PTR_ERR(ent);
838 
839 	ent->token = token;
840 
841 	init_completion(&ent->handling);
842 	if (!callback)
843 		init_completion(&ent->done);
844 
845 	INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
846 	INIT_WORK(&ent->work, cmd_work_handler);
847 	if (page_queue) {
848 		cmd_work_handler(&ent->work);
849 	} else if (!queue_work(cmd->wq, &ent->work)) {
850 		mlx5_core_warn(dev, "failed to queue work\n");
851 		err = -ENOMEM;
852 		goto out_free;
853 	}
854 
855 	if (callback)
856 		goto out;
857 	if (err == -ECANCELED)
858 		goto out_free;
859 
860 	err = wait_func(dev, ent);
861 	if (err == -ETIMEDOUT)
862 		goto out_free;
863 
864 	ds = ent->ts2 - ent->ts1;
865 	op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
866 	if (op < ARRAY_SIZE(cmd->stats)) {
867 		stats = &cmd->stats[op];
868 		spin_lock_irq(&stats->lock);
869 		stats->sum += ds;
870 		++stats->n;
871 		spin_unlock_irq(&stats->lock);
872 	}
873 	mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
874 			   "fw exec time for %s is %lld nsec\n",
875 			   mlx5_command_str(op), ds);
876 	*status = ent->status;
877 
878 out_free:
879 	free_cmd(ent);
880 out:
881 	return err;
882 }
883 
dbg_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)884 static ssize_t dbg_write(struct file *filp, const char __user *buf,
885 			 size_t count, loff_t *pos)
886 {
887 	struct mlx5_core_dev *dev = filp->private_data;
888 	struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
889 	char lbuf[3];
890 	int err;
891 
892 	if (!dbg->in_msg || !dbg->out_msg)
893 		return -ENOMEM;
894 
895 	if (copy_from_user(lbuf, buf, sizeof(lbuf)))
896 		return -EFAULT;
897 
898 	lbuf[sizeof(lbuf) - 1] = 0;
899 
900 	if (strcmp(lbuf, "go"))
901 		return -EINVAL;
902 
903 	err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
904 
905 	return err ? err : count;
906 }
907 
908 
909 static const struct file_operations fops = {
910 	.owner	= THIS_MODULE,
911 	.open	= simple_open,
912 	.write	= dbg_write,
913 };
914 
mlx5_copy_to_msg(struct mlx5_cmd_msg * to,void * from,int size,u8 token)915 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
916 			    u8 token)
917 {
918 	struct mlx5_cmd_prot_block *block;
919 	struct mlx5_cmd_mailbox *next;
920 	int copy;
921 
922 	if (!to || !from)
923 		return -ENOMEM;
924 
925 	copy = min_t(int, size, sizeof(to->first.data));
926 	memcpy(to->first.data, from, copy);
927 	size -= copy;
928 	from += copy;
929 
930 	next = to->next;
931 	while (size) {
932 		if (!next) {
933 			/* this is a BUG */
934 			return -ENOMEM;
935 		}
936 
937 		copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
938 		block = next->buf;
939 		memcpy(block->data, from, copy);
940 		from += copy;
941 		size -= copy;
942 		block->token = token;
943 		next = next->next;
944 	}
945 
946 	return 0;
947 }
948 
mlx5_copy_from_msg(void * to,struct mlx5_cmd_msg * from,int size)949 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
950 {
951 	struct mlx5_cmd_prot_block *block;
952 	struct mlx5_cmd_mailbox *next;
953 	int copy;
954 
955 	if (!to || !from)
956 		return -ENOMEM;
957 
958 	copy = min_t(int, size, sizeof(from->first.data));
959 	memcpy(to, from->first.data, copy);
960 	size -= copy;
961 	to += copy;
962 
963 	next = from->next;
964 	while (size) {
965 		if (!next) {
966 			/* this is a BUG */
967 			return -ENOMEM;
968 		}
969 
970 		copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
971 		block = next->buf;
972 
973 		memcpy(to, block->data, copy);
974 		to += copy;
975 		size -= copy;
976 		next = next->next;
977 	}
978 
979 	return 0;
980 }
981 
alloc_cmd_box(struct mlx5_core_dev * dev,gfp_t flags)982 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
983 					      gfp_t flags)
984 {
985 	struct mlx5_cmd_mailbox *mailbox;
986 
987 	mailbox = kmalloc(sizeof(*mailbox), flags);
988 	if (!mailbox)
989 		return ERR_PTR(-ENOMEM);
990 
991 	mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
992 				      &mailbox->dma);
993 	if (!mailbox->buf) {
994 		mlx5_core_dbg(dev, "failed allocation\n");
995 		kfree(mailbox);
996 		return ERR_PTR(-ENOMEM);
997 	}
998 	memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
999 	mailbox->next = NULL;
1000 
1001 	return mailbox;
1002 }
1003 
free_cmd_box(struct mlx5_core_dev * dev,struct mlx5_cmd_mailbox * mailbox)1004 static void free_cmd_box(struct mlx5_core_dev *dev,
1005 			 struct mlx5_cmd_mailbox *mailbox)
1006 {
1007 	pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1008 	kfree(mailbox);
1009 }
1010 
mlx5_alloc_cmd_msg(struct mlx5_core_dev * dev,gfp_t flags,int size,u8 token)1011 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1012 					       gfp_t flags, int size,
1013 					       u8 token)
1014 {
1015 	struct mlx5_cmd_mailbox *tmp, *head = NULL;
1016 	struct mlx5_cmd_prot_block *block;
1017 	struct mlx5_cmd_msg *msg;
1018 	int blen;
1019 	int err;
1020 	int n;
1021 	int i;
1022 
1023 	msg = kzalloc(sizeof(*msg), flags);
1024 	if (!msg)
1025 		return ERR_PTR(-ENOMEM);
1026 
1027 	blen = size - min_t(int, sizeof(msg->first.data), size);
1028 	n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
1029 
1030 	for (i = 0; i < n; i++) {
1031 		tmp = alloc_cmd_box(dev, flags);
1032 		if (IS_ERR(tmp)) {
1033 			mlx5_core_warn(dev, "failed allocating block\n");
1034 			err = PTR_ERR(tmp);
1035 			goto err_alloc;
1036 		}
1037 
1038 		block = tmp->buf;
1039 		tmp->next = head;
1040 		block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1041 		block->block_num = cpu_to_be32(n - i - 1);
1042 		block->token = token;
1043 		head = tmp;
1044 	}
1045 	msg->next = head;
1046 	msg->len = size;
1047 	return msg;
1048 
1049 err_alloc:
1050 	while (head) {
1051 		tmp = head->next;
1052 		free_cmd_box(dev, head);
1053 		head = tmp;
1054 	}
1055 	kfree(msg);
1056 
1057 	return ERR_PTR(err);
1058 }
1059 
mlx5_free_cmd_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1060 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1061 				  struct mlx5_cmd_msg *msg)
1062 {
1063 	struct mlx5_cmd_mailbox *head = msg->next;
1064 	struct mlx5_cmd_mailbox *next;
1065 
1066 	while (head) {
1067 		next = head->next;
1068 		free_cmd_box(dev, head);
1069 		head = next;
1070 	}
1071 	kfree(msg);
1072 }
1073 
data_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1074 static ssize_t data_write(struct file *filp, const char __user *buf,
1075 			  size_t count, loff_t *pos)
1076 {
1077 	struct mlx5_core_dev *dev = filp->private_data;
1078 	struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1079 	void *ptr;
1080 	int err;
1081 
1082 	if (*pos != 0)
1083 		return -EINVAL;
1084 
1085 	kfree(dbg->in_msg);
1086 	dbg->in_msg = NULL;
1087 	dbg->inlen = 0;
1088 
1089 	ptr = kzalloc(count, GFP_KERNEL);
1090 	if (!ptr)
1091 		return -ENOMEM;
1092 
1093 	if (copy_from_user(ptr, buf, count)) {
1094 		err = -EFAULT;
1095 		goto out;
1096 	}
1097 	dbg->in_msg = ptr;
1098 	dbg->inlen = count;
1099 
1100 	*pos = count;
1101 
1102 	return count;
1103 
1104 out:
1105 	kfree(ptr);
1106 	return err;
1107 }
1108 
data_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1109 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1110 			 loff_t *pos)
1111 {
1112 	struct mlx5_core_dev *dev = filp->private_data;
1113 	struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1114 	int copy;
1115 
1116 	if (*pos)
1117 		return 0;
1118 
1119 	if (!dbg->out_msg)
1120 		return -ENOMEM;
1121 
1122 	copy = min_t(int, count, dbg->outlen);
1123 	if (copy_to_user(buf, dbg->out_msg, copy))
1124 		return -EFAULT;
1125 
1126 	*pos += copy;
1127 
1128 	return copy;
1129 }
1130 
1131 static const struct file_operations dfops = {
1132 	.owner	= THIS_MODULE,
1133 	.open	= simple_open,
1134 	.write	= data_write,
1135 	.read	= data_read,
1136 };
1137 
outlen_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1138 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1139 			   loff_t *pos)
1140 {
1141 	struct mlx5_core_dev *dev = filp->private_data;
1142 	struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1143 	char outlen[8];
1144 	int err;
1145 
1146 	if (*pos)
1147 		return 0;
1148 
1149 	err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1150 	if (err < 0)
1151 		return err;
1152 
1153 	if (copy_to_user(buf, &outlen, err))
1154 		return -EFAULT;
1155 
1156 	*pos += err;
1157 
1158 	return err;
1159 }
1160 
outlen_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1161 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1162 			    size_t count, loff_t *pos)
1163 {
1164 	struct mlx5_core_dev *dev = filp->private_data;
1165 	struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1166 	char outlen_str[8] = {0};
1167 	int outlen;
1168 	void *ptr;
1169 	int err;
1170 
1171 	if (*pos != 0 || count > 6)
1172 		return -EINVAL;
1173 
1174 	kfree(dbg->out_msg);
1175 	dbg->out_msg = NULL;
1176 	dbg->outlen = 0;
1177 
1178 	if (copy_from_user(outlen_str, buf, count))
1179 		return -EFAULT;
1180 
1181 	err = sscanf(outlen_str, "%d", &outlen);
1182 	if (err < 0)
1183 		return err;
1184 
1185 	ptr = kzalloc(outlen, GFP_KERNEL);
1186 	if (!ptr)
1187 		return -ENOMEM;
1188 
1189 	dbg->out_msg = ptr;
1190 	dbg->outlen = outlen;
1191 
1192 	*pos = count;
1193 
1194 	return count;
1195 }
1196 
1197 static const struct file_operations olfops = {
1198 	.owner	= THIS_MODULE,
1199 	.open	= simple_open,
1200 	.write	= outlen_write,
1201 	.read	= outlen_read,
1202 };
1203 
set_wqname(struct mlx5_core_dev * dev)1204 static void set_wqname(struct mlx5_core_dev *dev)
1205 {
1206 	struct mlx5_cmd *cmd = &dev->cmd;
1207 
1208 	snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1209 		 dev_name(&dev->pdev->dev));
1210 }
1211 
clean_debug_files(struct mlx5_core_dev * dev)1212 static void clean_debug_files(struct mlx5_core_dev *dev)
1213 {
1214 	struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1215 
1216 	if (!mlx5_debugfs_root)
1217 		return;
1218 
1219 	mlx5_cmdif_debugfs_cleanup(dev);
1220 	debugfs_remove_recursive(dbg->dbg_root);
1221 }
1222 
create_debugfs_files(struct mlx5_core_dev * dev)1223 static int create_debugfs_files(struct mlx5_core_dev *dev)
1224 {
1225 	struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1226 	int err = -ENOMEM;
1227 
1228 	if (!mlx5_debugfs_root)
1229 		return 0;
1230 
1231 	dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1232 	if (!dbg->dbg_root)
1233 		return err;
1234 
1235 	dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1236 					  dev, &dfops);
1237 	if (!dbg->dbg_in)
1238 		goto err_dbg;
1239 
1240 	dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1241 					   dev, &dfops);
1242 	if (!dbg->dbg_out)
1243 		goto err_dbg;
1244 
1245 	dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1246 					      dev, &olfops);
1247 	if (!dbg->dbg_outlen)
1248 		goto err_dbg;
1249 
1250 	dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1251 					    &dbg->status);
1252 	if (!dbg->dbg_status)
1253 		goto err_dbg;
1254 
1255 	dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1256 	if (!dbg->dbg_run)
1257 		goto err_dbg;
1258 
1259 	mlx5_cmdif_debugfs_init(dev);
1260 
1261 	return 0;
1262 
1263 err_dbg:
1264 	clean_debug_files(dev);
1265 	return err;
1266 }
1267 
mlx5_cmd_change_mod(struct mlx5_core_dev * dev,int mode)1268 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1269 {
1270 	struct mlx5_cmd *cmd = &dev->cmd;
1271 	int i;
1272 
1273 	for (i = 0; i < cmd->max_reg_cmds; i++)
1274 		down(&cmd->sem);
1275 	down(&cmd->pages_sem);
1276 
1277 	cmd->mode = mode;
1278 
1279 	up(&cmd->pages_sem);
1280 	for (i = 0; i < cmd->max_reg_cmds; i++)
1281 		up(&cmd->sem);
1282 }
1283 
mlx5_cmd_use_events(struct mlx5_core_dev * dev)1284 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1285 {
1286 	mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1287 }
1288 
mlx5_cmd_use_polling(struct mlx5_core_dev * dev)1289 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1290 {
1291 	mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1292 }
1293 
free_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1294 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1295 {
1296 	unsigned long flags;
1297 
1298 	if (msg->cache) {
1299 		spin_lock_irqsave(&msg->cache->lock, flags);
1300 		list_add_tail(&msg->list, &msg->cache->head);
1301 		spin_unlock_irqrestore(&msg->cache->lock, flags);
1302 	} else {
1303 		mlx5_free_cmd_msg(dev, msg);
1304 	}
1305 }
1306 
mlx5_cmd_comp_handler(struct mlx5_core_dev * dev,u64 vec)1307 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
1308 {
1309 	struct mlx5_cmd *cmd = &dev->cmd;
1310 	struct mlx5_cmd_work_ent *ent;
1311 	mlx5_cmd_cbk_t callback;
1312 	void *context;
1313 	int err;
1314 	int i;
1315 	s64 ds;
1316 	struct mlx5_cmd_stats *stats;
1317 	unsigned long flags;
1318 	unsigned long vector;
1319 
1320 	/* there can be at most 32 command queues */
1321 	vector = vec & 0xffffffff;
1322 	for (i = 0; i < (1 << cmd->log_sz); i++) {
1323 		if (test_bit(i, &vector)) {
1324 			struct semaphore *sem;
1325 
1326 			ent = cmd->ent_arr[i];
1327 			if (ent->callback)
1328 				cancel_delayed_work(&ent->cb_timeout_work);
1329 			if (ent->page_queue)
1330 				sem = &cmd->pages_sem;
1331 			else
1332 				sem = &cmd->sem;
1333 			ent->ts2 = ktime_get_ns();
1334 			memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1335 			dump_command(dev, ent, 0);
1336 			if (!ent->ret) {
1337 				if (!cmd->checksum_disabled)
1338 					ent->ret = verify_signature(ent);
1339 				else
1340 					ent->ret = 0;
1341 				if (vec & MLX5_TRIGGERED_CMD_COMP)
1342 					ent->status = MLX5_DRIVER_STATUS_ABORTED;
1343 				else
1344 					ent->status = ent->lay->status_own >> 1;
1345 
1346 				mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1347 					      ent->ret, deliv_status_to_str(ent->status), ent->status);
1348 			}
1349 			free_ent(cmd, ent->idx);
1350 
1351 			if (ent->callback) {
1352 				ds = ent->ts2 - ent->ts1;
1353 				if (ent->op < ARRAY_SIZE(cmd->stats)) {
1354 					stats = &cmd->stats[ent->op];
1355 					spin_lock_irqsave(&stats->lock, flags);
1356 					stats->sum += ds;
1357 					++stats->n;
1358 					spin_unlock_irqrestore(&stats->lock, flags);
1359 				}
1360 
1361 				callback = ent->callback;
1362 				context = ent->context;
1363 				err = ent->ret;
1364 				if (!err)
1365 					err = mlx5_copy_from_msg(ent->uout,
1366 								 ent->out,
1367 								 ent->uout_size);
1368 
1369 				mlx5_free_cmd_msg(dev, ent->out);
1370 				free_msg(dev, ent->in);
1371 
1372 				err = err ? err : ent->status;
1373 				free_cmd(ent);
1374 				callback(err, context);
1375 			} else {
1376 				complete(&ent->done);
1377 			}
1378 			up(sem);
1379 		}
1380 	}
1381 }
1382 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1383 
status_to_err(u8 status)1384 static int status_to_err(u8 status)
1385 {
1386 	return status ? -1 : 0; /* TBD more meaningful codes */
1387 }
1388 
alloc_msg(struct mlx5_core_dev * dev,int in_size,gfp_t gfp)1389 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1390 				      gfp_t gfp)
1391 {
1392 	struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1393 	struct mlx5_cmd *cmd = &dev->cmd;
1394 	struct cache_ent *ent = NULL;
1395 
1396 	if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1397 		ent = &cmd->cache.large;
1398 	else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1399 		ent = &cmd->cache.med;
1400 
1401 	if (ent) {
1402 		spin_lock_irq(&ent->lock);
1403 		if (!list_empty(&ent->head)) {
1404 			msg = list_entry(ent->head.next, typeof(*msg), list);
1405 			/* For cached lists, we must explicitly state what is
1406 			 * the real size
1407 			 */
1408 			msg->len = in_size;
1409 			list_del(&msg->list);
1410 		}
1411 		spin_unlock_irq(&ent->lock);
1412 	}
1413 
1414 	if (IS_ERR(msg))
1415 		msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1416 
1417 	return msg;
1418 }
1419 
opcode_from_in(struct mlx5_inbox_hdr * in)1420 static u16 opcode_from_in(struct mlx5_inbox_hdr *in)
1421 {
1422 	return be16_to_cpu(in->opcode);
1423 }
1424 
is_manage_pages(struct mlx5_inbox_hdr * in)1425 static int is_manage_pages(struct mlx5_inbox_hdr *in)
1426 {
1427 	return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1428 }
1429 
cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size,mlx5_cmd_cbk_t callback,void * context)1430 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1431 		    int out_size, mlx5_cmd_cbk_t callback, void *context)
1432 {
1433 	struct mlx5_cmd_msg *inb;
1434 	struct mlx5_cmd_msg *outb;
1435 	int pages_queue;
1436 	gfp_t gfp;
1437 	int err;
1438 	u8 status = 0;
1439 	u32 drv_synd;
1440 	u8 token;
1441 
1442 	if (pci_channel_offline(dev->pdev) ||
1443 	    dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1444 		err = mlx5_internal_err_ret_value(dev, opcode_from_in(in), &drv_synd, &status);
1445 		*get_synd_ptr(out) = cpu_to_be32(drv_synd);
1446 		*get_status_ptr(out) = status;
1447 		return err;
1448 	}
1449 
1450 	pages_queue = is_manage_pages(in);
1451 	gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1452 
1453 	inb = alloc_msg(dev, in_size, gfp);
1454 	if (IS_ERR(inb)) {
1455 		err = PTR_ERR(inb);
1456 		return err;
1457 	}
1458 
1459 	token = alloc_token(&dev->cmd);
1460 
1461 	err = mlx5_copy_to_msg(inb, in, in_size, token);
1462 	if (err) {
1463 		mlx5_core_warn(dev, "err %d\n", err);
1464 		goto out_in;
1465 	}
1466 
1467 	outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1468 	if (IS_ERR(outb)) {
1469 		err = PTR_ERR(outb);
1470 		goto out_in;
1471 	}
1472 
1473 	err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1474 			      pages_queue, &status, token);
1475 	if (err)
1476 		goto out_out;
1477 
1478 	mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1479 	if (status) {
1480 		err = status_to_err(status);
1481 		goto out_out;
1482 	}
1483 
1484 	if (!callback)
1485 		err = mlx5_copy_from_msg(out, outb, out_size);
1486 
1487 out_out:
1488 	if (!callback)
1489 		mlx5_free_cmd_msg(dev, outb);
1490 
1491 out_in:
1492 	if (!callback)
1493 		free_msg(dev, inb);
1494 	return err;
1495 }
1496 
mlx5_cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)1497 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1498 		  int out_size)
1499 {
1500 	return cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1501 }
1502 EXPORT_SYMBOL(mlx5_cmd_exec);
1503 
mlx5_cmd_exec_cb(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size,mlx5_cmd_cbk_t callback,void * context)1504 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1505 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
1506 		     void *context)
1507 {
1508 	return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1509 }
1510 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1511 
destroy_msg_cache(struct mlx5_core_dev * dev)1512 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1513 {
1514 	struct mlx5_cmd *cmd = &dev->cmd;
1515 	struct mlx5_cmd_msg *msg;
1516 	struct mlx5_cmd_msg *n;
1517 
1518 	list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1519 		list_del(&msg->list);
1520 		mlx5_free_cmd_msg(dev, msg);
1521 	}
1522 
1523 	list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1524 		list_del(&msg->list);
1525 		mlx5_free_cmd_msg(dev, msg);
1526 	}
1527 }
1528 
create_msg_cache(struct mlx5_core_dev * dev)1529 static int create_msg_cache(struct mlx5_core_dev *dev)
1530 {
1531 	struct mlx5_cmd *cmd = &dev->cmd;
1532 	struct mlx5_cmd_msg *msg;
1533 	int err;
1534 	int i;
1535 
1536 	spin_lock_init(&cmd->cache.large.lock);
1537 	INIT_LIST_HEAD(&cmd->cache.large.head);
1538 	spin_lock_init(&cmd->cache.med.lock);
1539 	INIT_LIST_HEAD(&cmd->cache.med.head);
1540 
1541 	for (i = 0; i < NUM_LONG_LISTS; i++) {
1542 		msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE, 0);
1543 		if (IS_ERR(msg)) {
1544 			err = PTR_ERR(msg);
1545 			goto ex_err;
1546 		}
1547 		msg->cache = &cmd->cache.large;
1548 		list_add_tail(&msg->list, &cmd->cache.large.head);
1549 	}
1550 
1551 	for (i = 0; i < NUM_MED_LISTS; i++) {
1552 		msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE, 0);
1553 		if (IS_ERR(msg)) {
1554 			err = PTR_ERR(msg);
1555 			goto ex_err;
1556 		}
1557 		msg->cache = &cmd->cache.med;
1558 		list_add_tail(&msg->list, &cmd->cache.med.head);
1559 	}
1560 
1561 	return 0;
1562 
1563 ex_err:
1564 	destroy_msg_cache(dev);
1565 	return err;
1566 }
1567 
alloc_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)1568 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1569 {
1570 	struct device *ddev = &dev->pdev->dev;
1571 
1572 	cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1573 						 &cmd->alloc_dma, GFP_KERNEL);
1574 	if (!cmd->cmd_alloc_buf)
1575 		return -ENOMEM;
1576 
1577 	/* make sure it is aligned to 4K */
1578 	if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1579 		cmd->cmd_buf = cmd->cmd_alloc_buf;
1580 		cmd->dma = cmd->alloc_dma;
1581 		cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1582 		return 0;
1583 	}
1584 
1585 	dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1586 			  cmd->alloc_dma);
1587 	cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1588 						 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1589 						 &cmd->alloc_dma, GFP_KERNEL);
1590 	if (!cmd->cmd_alloc_buf)
1591 		return -ENOMEM;
1592 
1593 	cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1594 	cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1595 	cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1596 	return 0;
1597 }
1598 
free_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)1599 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1600 {
1601 	struct device *ddev = &dev->pdev->dev;
1602 
1603 	dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1604 			  cmd->alloc_dma);
1605 }
1606 
mlx5_cmd_init(struct mlx5_core_dev * dev)1607 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1608 {
1609 	int size = sizeof(struct mlx5_cmd_prot_block);
1610 	int align = roundup_pow_of_two(size);
1611 	struct mlx5_cmd *cmd = &dev->cmd;
1612 	u32 cmd_h, cmd_l;
1613 	u16 cmd_if_rev;
1614 	int err;
1615 	int i;
1616 
1617 	memset(cmd, 0, sizeof(*cmd));
1618 	cmd_if_rev = cmdif_rev(dev);
1619 	if (cmd_if_rev != CMD_IF_REV) {
1620 		dev_err(&dev->pdev->dev,
1621 			"Driver cmdif rev(%d) differs from firmware's(%d)\n",
1622 			CMD_IF_REV, cmd_if_rev);
1623 		return -EINVAL;
1624 	}
1625 
1626 	cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1627 	if (!cmd->pool)
1628 		return -ENOMEM;
1629 
1630 	err = alloc_cmd_page(dev, cmd);
1631 	if (err)
1632 		goto err_free_pool;
1633 
1634 	cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1635 	cmd->log_sz = cmd_l >> 4 & 0xf;
1636 	cmd->log_stride = cmd_l & 0xf;
1637 	if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1638 		dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1639 			1 << cmd->log_sz);
1640 		err = -EINVAL;
1641 		goto err_free_page;
1642 	}
1643 
1644 	if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1645 		dev_err(&dev->pdev->dev, "command queue size overflow\n");
1646 		err = -EINVAL;
1647 		goto err_free_page;
1648 	}
1649 
1650 	cmd->checksum_disabled = 1;
1651 	cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1652 	cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1653 
1654 	cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1655 	if (cmd->cmdif_rev > CMD_IF_REV) {
1656 		dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1657 			CMD_IF_REV, cmd->cmdif_rev);
1658 		err = -ENOTSUPP;
1659 		goto err_free_page;
1660 	}
1661 
1662 	spin_lock_init(&cmd->alloc_lock);
1663 	spin_lock_init(&cmd->token_lock);
1664 	for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1665 		spin_lock_init(&cmd->stats[i].lock);
1666 
1667 	sema_init(&cmd->sem, cmd->max_reg_cmds);
1668 	sema_init(&cmd->pages_sem, 1);
1669 
1670 	cmd_h = (u32)((u64)(cmd->dma) >> 32);
1671 	cmd_l = (u32)(cmd->dma);
1672 	if (cmd_l & 0xfff) {
1673 		dev_err(&dev->pdev->dev, "invalid command queue address\n");
1674 		err = -ENOMEM;
1675 		goto err_free_page;
1676 	}
1677 
1678 	iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1679 	iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1680 
1681 	/* Make sure firmware sees the complete address before we proceed */
1682 	wmb();
1683 
1684 	mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1685 
1686 	cmd->mode = CMD_MODE_POLLING;
1687 
1688 	err = create_msg_cache(dev);
1689 	if (err) {
1690 		dev_err(&dev->pdev->dev, "failed to create command cache\n");
1691 		goto err_free_page;
1692 	}
1693 
1694 	set_wqname(dev);
1695 	cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1696 	if (!cmd->wq) {
1697 		dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1698 		err = -ENOMEM;
1699 		goto err_cache;
1700 	}
1701 
1702 	err = create_debugfs_files(dev);
1703 	if (err) {
1704 		err = -ENOMEM;
1705 		goto err_wq;
1706 	}
1707 
1708 	return 0;
1709 
1710 err_wq:
1711 	destroy_workqueue(cmd->wq);
1712 
1713 err_cache:
1714 	destroy_msg_cache(dev);
1715 
1716 err_free_page:
1717 	free_cmd_page(dev, cmd);
1718 
1719 err_free_pool:
1720 	pci_pool_destroy(cmd->pool);
1721 
1722 	return err;
1723 }
1724 EXPORT_SYMBOL(mlx5_cmd_init);
1725 
mlx5_cmd_cleanup(struct mlx5_core_dev * dev)1726 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1727 {
1728 	struct mlx5_cmd *cmd = &dev->cmd;
1729 
1730 	clean_debug_files(dev);
1731 	destroy_workqueue(cmd->wq);
1732 	destroy_msg_cache(dev);
1733 	free_cmd_page(dev, cmd);
1734 	pci_pool_destroy(cmd->pool);
1735 }
1736 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1737 
cmd_status_str(u8 status)1738 static const char *cmd_status_str(u8 status)
1739 {
1740 	switch (status) {
1741 	case MLX5_CMD_STAT_OK:
1742 		return "OK";
1743 	case MLX5_CMD_STAT_INT_ERR:
1744 		return "internal error";
1745 	case MLX5_CMD_STAT_BAD_OP_ERR:
1746 		return "bad operation";
1747 	case MLX5_CMD_STAT_BAD_PARAM_ERR:
1748 		return "bad parameter";
1749 	case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1750 		return "bad system state";
1751 	case MLX5_CMD_STAT_BAD_RES_ERR:
1752 		return "bad resource";
1753 	case MLX5_CMD_STAT_RES_BUSY:
1754 		return "resource busy";
1755 	case MLX5_CMD_STAT_LIM_ERR:
1756 		return "limits exceeded";
1757 	case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1758 		return "bad resource state";
1759 	case MLX5_CMD_STAT_IX_ERR:
1760 		return "bad index";
1761 	case MLX5_CMD_STAT_NO_RES_ERR:
1762 		return "no resources";
1763 	case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1764 		return "bad input length";
1765 	case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1766 		return "bad output length";
1767 	case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1768 		return "bad QP state";
1769 	case MLX5_CMD_STAT_BAD_PKT_ERR:
1770 		return "bad packet (discarded)";
1771 	case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1772 		return "bad size too many outstanding CQEs";
1773 	default:
1774 		return "unknown status";
1775 	}
1776 }
1777 
cmd_status_to_err(u8 status)1778 static int cmd_status_to_err(u8 status)
1779 {
1780 	switch (status) {
1781 	case MLX5_CMD_STAT_OK:				return 0;
1782 	case MLX5_CMD_STAT_INT_ERR:			return -EIO;
1783 	case MLX5_CMD_STAT_BAD_OP_ERR:			return -EINVAL;
1784 	case MLX5_CMD_STAT_BAD_PARAM_ERR:		return -EINVAL;
1785 	case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:		return -EIO;
1786 	case MLX5_CMD_STAT_BAD_RES_ERR:			return -EINVAL;
1787 	case MLX5_CMD_STAT_RES_BUSY:			return -EBUSY;
1788 	case MLX5_CMD_STAT_LIM_ERR:			return -ENOMEM;
1789 	case MLX5_CMD_STAT_BAD_RES_STATE_ERR:		return -EINVAL;
1790 	case MLX5_CMD_STAT_IX_ERR:			return -EINVAL;
1791 	case MLX5_CMD_STAT_NO_RES_ERR:			return -EAGAIN;
1792 	case MLX5_CMD_STAT_BAD_INP_LEN_ERR:		return -EIO;
1793 	case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:		return -EIO;
1794 	case MLX5_CMD_STAT_BAD_QP_STATE_ERR:		return -EINVAL;
1795 	case MLX5_CMD_STAT_BAD_PKT_ERR:			return -EINVAL;
1796 	case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:	return -EINVAL;
1797 	default:					return -EIO;
1798 	}
1799 }
1800 
1801 /* this will be available till all the commands use set/get macros */
mlx5_cmd_status_to_err(struct mlx5_outbox_hdr * hdr)1802 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1803 {
1804 	if (!hdr->status)
1805 		return 0;
1806 
1807 	pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1808 		cmd_status_str(hdr->status), hdr->status,
1809 		be32_to_cpu(hdr->syndrome));
1810 
1811 	return cmd_status_to_err(hdr->status);
1812 }
1813 
mlx5_cmd_status_to_err_v2(void * ptr)1814 int mlx5_cmd_status_to_err_v2(void *ptr)
1815 {
1816 	u32	syndrome;
1817 	u8	status;
1818 
1819 	status = be32_to_cpu(*(__be32 *)ptr) >> 24;
1820 	if (!status)
1821 		return 0;
1822 
1823 	syndrome = be32_to_cpu(*(__be32 *)(ptr + 4));
1824 
1825 	pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1826 		cmd_status_str(status), status, syndrome);
1827 
1828 	return cmd_status_to_err(status);
1829 }
1830