1 /* Texas Instruments Ethernet Switch Driver
2 *
3 * Copyright (C) 2013 Texas Instruments
4 *
5 * Module Author: Mugunthan V N <mugunthanvnm@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/platform_device.h>
18 #include <linux/init.h>
19 #include <linux/netdevice.h>
20 #include <linux/phy.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23
24 #include "cpsw.h"
25
26 /* AM33xx SoC specific definitions for the CONTROL port */
27 #define AM33XX_GMII_SEL_MODE_MII 0
28 #define AM33XX_GMII_SEL_MODE_RMII 1
29 #define AM33XX_GMII_SEL_MODE_RGMII 2
30
31 #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
32 #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
33
34 #define GMII_SEL_MODE_MASK 0x3
35
36 struct cpsw_phy_sel_priv {
37 struct device *dev;
38 u32 __iomem *gmii_sel;
39 bool rmii_clock_external;
40 void (*cpsw_phy_sel)(struct cpsw_phy_sel_priv *priv,
41 phy_interface_t phy_mode, int slave);
42 };
43
44
cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv * priv,phy_interface_t phy_mode,int slave)45 static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv,
46 phy_interface_t phy_mode, int slave)
47 {
48 u32 reg;
49 u32 mask;
50 u32 mode = 0;
51
52 reg = readl(priv->gmii_sel);
53
54 switch (phy_mode) {
55 case PHY_INTERFACE_MODE_RMII:
56 mode = AM33XX_GMII_SEL_MODE_RMII;
57 break;
58
59 case PHY_INTERFACE_MODE_RGMII:
60 case PHY_INTERFACE_MODE_RGMII_ID:
61 case PHY_INTERFACE_MODE_RGMII_RXID:
62 case PHY_INTERFACE_MODE_RGMII_TXID:
63 mode = AM33XX_GMII_SEL_MODE_RGMII;
64 break;
65
66 case PHY_INTERFACE_MODE_MII:
67 default:
68 mode = AM33XX_GMII_SEL_MODE_MII;
69 break;
70 };
71
72 mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
73 mode <<= slave * 2;
74
75 if (priv->rmii_clock_external) {
76 if (slave == 0)
77 mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
78 else
79 mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
80 }
81
82 reg &= ~mask;
83 reg |= mode;
84
85 writel(reg, priv->gmii_sel);
86 }
87
cpsw_gmii_sel_dra7xx(struct cpsw_phy_sel_priv * priv,phy_interface_t phy_mode,int slave)88 static void cpsw_gmii_sel_dra7xx(struct cpsw_phy_sel_priv *priv,
89 phy_interface_t phy_mode, int slave)
90 {
91 u32 reg;
92 u32 mask;
93 u32 mode = 0;
94
95 reg = readl(priv->gmii_sel);
96
97 switch (phy_mode) {
98 case PHY_INTERFACE_MODE_RMII:
99 mode = AM33XX_GMII_SEL_MODE_RMII;
100 break;
101
102 case PHY_INTERFACE_MODE_RGMII:
103 case PHY_INTERFACE_MODE_RGMII_ID:
104 case PHY_INTERFACE_MODE_RGMII_RXID:
105 case PHY_INTERFACE_MODE_RGMII_TXID:
106 mode = AM33XX_GMII_SEL_MODE_RGMII;
107 break;
108
109 case PHY_INTERFACE_MODE_MII:
110 default:
111 mode = AM33XX_GMII_SEL_MODE_MII;
112 break;
113 };
114
115 switch (slave) {
116 case 0:
117 mask = GMII_SEL_MODE_MASK;
118 break;
119 case 1:
120 mask = GMII_SEL_MODE_MASK << 4;
121 mode <<= 4;
122 break;
123 default:
124 dev_err(priv->dev, "invalid slave number...\n");
125 return;
126 }
127
128 if (priv->rmii_clock_external)
129 dev_err(priv->dev, "RMII External clock is not supported\n");
130
131 reg &= ~mask;
132 reg |= mode;
133
134 writel(reg, priv->gmii_sel);
135 }
136
137 static struct platform_driver cpsw_phy_sel_driver;
match(struct device * dev,void * data)138 static int match(struct device *dev, void *data)
139 {
140 struct device_node *node = (struct device_node *)data;
141 return dev->of_node == node &&
142 dev->driver == &cpsw_phy_sel_driver.driver;
143 }
144
cpsw_phy_sel(struct device * dev,phy_interface_t phy_mode,int slave)145 void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave)
146 {
147 struct device_node *node;
148 struct cpsw_phy_sel_priv *priv;
149
150 node = of_get_child_by_name(dev->of_node, "cpsw-phy-sel");
151 if (!node) {
152 dev_err(dev, "Phy mode driver DT not found\n");
153 return;
154 }
155
156 dev = bus_find_device(&platform_bus_type, NULL, node, match);
157 of_node_put(node);
158 priv = dev_get_drvdata(dev);
159
160 priv->cpsw_phy_sel(priv, phy_mode, slave);
161
162 put_device(dev);
163 }
164 EXPORT_SYMBOL_GPL(cpsw_phy_sel);
165
166 static const struct of_device_id cpsw_phy_sel_id_table[] = {
167 {
168 .compatible = "ti,am3352-cpsw-phy-sel",
169 .data = &cpsw_gmii_sel_am3352,
170 },
171 {
172 .compatible = "ti,dra7xx-cpsw-phy-sel",
173 .data = &cpsw_gmii_sel_dra7xx,
174 },
175 {
176 .compatible = "ti,am43xx-cpsw-phy-sel",
177 .data = &cpsw_gmii_sel_am3352,
178 },
179 {}
180 };
181
cpsw_phy_sel_probe(struct platform_device * pdev)182 static int cpsw_phy_sel_probe(struct platform_device *pdev)
183 {
184 struct resource *res;
185 const struct of_device_id *of_id;
186 struct cpsw_phy_sel_priv *priv;
187
188 of_id = of_match_node(cpsw_phy_sel_id_table, pdev->dev.of_node);
189 if (!of_id)
190 return -EINVAL;
191
192 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
193 if (!priv) {
194 dev_err(&pdev->dev, "unable to alloc memory for cpsw phy sel\n");
195 return -ENOMEM;
196 }
197
198 priv->dev = &pdev->dev;
199 priv->cpsw_phy_sel = of_id->data;
200
201 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gmii-sel");
202 priv->gmii_sel = devm_ioremap_resource(&pdev->dev, res);
203 if (IS_ERR(priv->gmii_sel))
204 return PTR_ERR(priv->gmii_sel);
205
206 if (of_find_property(pdev->dev.of_node, "rmii-clock-ext", NULL))
207 priv->rmii_clock_external = true;
208
209 dev_set_drvdata(&pdev->dev, priv);
210
211 return 0;
212 }
213
214 static struct platform_driver cpsw_phy_sel_driver = {
215 .probe = cpsw_phy_sel_probe,
216 .driver = {
217 .name = "cpsw-phy-sel",
218 .of_match_table = cpsw_phy_sel_id_table,
219 },
220 };
221 builtin_platform_driver(cpsw_phy_sel_driver);
222