1 /*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #ifndef _PCI_H_
19 #define _PCI_H_
20
21 #include <linux/interrupt.h>
22
23 #include "hw.h"
24 #include "ce.h"
25
26 /*
27 * maximum number of bytes that can be handled atomically by DiagRead/DiagWrite
28 */
29 #define DIAG_TRANSFER_LIMIT 2048
30
31 /*
32 * maximum number of bytes that can be
33 * handled atomically by DiagRead/DiagWrite
34 */
35 #define DIAG_TRANSFER_LIMIT 2048
36
37 struct bmi_xfer {
38 bool tx_done;
39 bool rx_done;
40 bool wait_for_resp;
41 u32 resp_len;
42 };
43
44 /*
45 * PCI-specific Target state
46 *
47 * NOTE: Structure is shared between Host software and Target firmware!
48 *
49 * Much of this may be of interest to the Host so
50 * HOST_INTEREST->hi_interconnect_state points here
51 * (and all members are 32-bit quantities in order to
52 * facilitate Host access). In particular, Host software is
53 * required to initialize pipe_cfg_addr and svc_to_pipe_map.
54 */
55 struct pcie_state {
56 /* Pipe configuration Target address */
57 /* NB: ce_pipe_config[CE_COUNT] */
58 u32 pipe_cfg_addr;
59
60 /* Service to pipe map Target address */
61 /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
62 u32 svc_to_pipe_map;
63
64 /* number of MSI interrupts requested */
65 u32 msi_requested;
66
67 /* number of MSI interrupts granted */
68 u32 msi_granted;
69
70 /* Message Signalled Interrupt address */
71 u32 msi_addr;
72
73 /* Base data */
74 u32 msi_data;
75
76 /*
77 * Data for firmware interrupt;
78 * MSI data for other interrupts are
79 * in various SoC registers
80 */
81 u32 msi_fw_intr_data;
82
83 /* PCIE_PWR_METHOD_* */
84 u32 power_mgmt_method;
85
86 /* PCIE_CONFIG_FLAG_* */
87 u32 config_flags;
88 };
89
90 /* PCIE_CONFIG_FLAG definitions */
91 #define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
92
93 /* Host software's Copy Engine configuration. */
94 #define CE_ATTR_FLAGS 0
95
96 /*
97 * Configuration information for a Copy Engine pipe.
98 * Passed from Host to Target during startup (one per CE).
99 *
100 * NOTE: Structure is shared between Host software and Target firmware!
101 */
102 struct ce_pipe_config {
103 __le32 pipenum;
104 __le32 pipedir;
105 __le32 nentries;
106 __le32 nbytes_max;
107 __le32 flags;
108 __le32 reserved;
109 };
110
111 /*
112 * Directions for interconnect pipe configuration.
113 * These definitions may be used during configuration and are shared
114 * between Host and Target.
115 *
116 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
117 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
118 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
119 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
120 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
121 * over the interconnect.
122 */
123 #define PIPEDIR_NONE 0
124 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
125 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
126 #define PIPEDIR_INOUT 3 /* bidirectional */
127
128 /* Establish a mapping between a service/direction and a pipe. */
129 struct service_to_pipe {
130 __le32 service_id;
131 __le32 pipedir;
132 __le32 pipenum;
133 };
134
135 /* Per-pipe state. */
136 struct ath10k_pci_pipe {
137 /* Handle of underlying Copy Engine */
138 struct ath10k_ce_pipe *ce_hdl;
139
140 /* Our pipe number; facilitiates use of pipe_info ptrs. */
141 u8 pipe_num;
142
143 /* Convenience back pointer to hif_ce_state. */
144 struct ath10k *hif_ce_state;
145
146 size_t buf_sz;
147
148 /* protects compl_free and num_send_allowed */
149 spinlock_t pipe_lock;
150
151 struct ath10k_pci *ar_pci;
152 struct tasklet_struct intr;
153 };
154
155 struct ath10k_pci_supp_chip {
156 u32 dev_id;
157 u32 rev_id;
158 };
159
160 struct ath10k_pci {
161 struct pci_dev *pdev;
162 struct device *dev;
163 struct ath10k *ar;
164 void __iomem *mem;
165 size_t mem_len;
166
167 /*
168 * Number of MSI interrupts granted, 0 --> using legacy PCI line
169 * interrupts.
170 */
171 int num_msi_intrs;
172
173 struct tasklet_struct intr_tq;
174 struct tasklet_struct msi_fw_err;
175
176 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
177
178 /* Copy Engine used for Diagnostic Accesses */
179 struct ath10k_ce_pipe *ce_diag;
180
181 /* FIXME: document what this really protects */
182 spinlock_t ce_lock;
183
184 /* Map CE id to ce_state */
185 struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
186 struct timer_list rx_post_retry;
187
188 /* Due to HW quirks it is recommended to disable ASPM during device
189 * bootup. To do that the original PCI-E Link Control is stored before
190 * device bootup is executed and re-programmed later.
191 */
192 u16 link_ctl;
193
194 /* Protects ps_awake and ps_wake_refcount */
195 spinlock_t ps_lock;
196
197 /* The device has a special powersave-oriented register. When device is
198 * considered asleep it drains less power and driver is forbidden from
199 * accessing most MMIO registers. If host were to access them without
200 * waking up the device might scribble over host memory or return
201 * 0xdeadbeef readouts.
202 */
203 unsigned long ps_wake_refcount;
204
205 /* Waking up takes some time (up to 2ms in some cases) so it can be bad
206 * for latency. To mitigate this the device isn't immediately allowed
207 * to sleep after all references are undone - instead there's a grace
208 * period after which the powersave register is updated unless some
209 * activity to/from device happened in the meantime.
210 *
211 * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
212 */
213 struct timer_list ps_timer;
214
215 /* MMIO registers are used to communicate with the device. With
216 * intensive traffic accessing powersave register would be a bit
217 * wasteful overhead and would needlessly stall CPU. It is far more
218 * efficient to rely on a variable in RAM and update it only upon
219 * powersave register state changes.
220 */
221 bool ps_awake;
222
223 /* pci power save, disable for QCA988X and QCA99X0.
224 * Writing 'false' to this variable avoids frequent locking
225 * on MMIO read/write.
226 */
227 bool pci_ps;
228 };
229
ath10k_pci_priv(struct ath10k * ar)230 static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
231 {
232 return (struct ath10k_pci *)ar->drv_priv;
233 }
234
235 #define ATH10K_PCI_RX_POST_RETRY_MS 50
236 #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
237 #define PCIE_WAKE_TIMEOUT 30000 /* 30ms */
238 #define PCIE_WAKE_LATE_US 10000 /* 10ms */
239
240 #define BAR_NUM 0
241
242 #define CDC_WAR_MAGIC_STR 0xceef0000
243 #define CDC_WAR_DATA_CE 4
244
245 /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
246 #define DIAG_ACCESS_CE_TIMEOUT_MS 10
247
248 void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
249 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
250 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
251
252 u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
253 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
254 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
255
256 /* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
257 * frequently. To avoid this put SoC to sleep after a very conservative grace
258 * period. Adjust with great care.
259 */
260 #define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
261
262 #endif /* _PCI_H_ */
263