1 /*
2 * PCIe host controller driver for Texas Instruments Keystone SoCs
3 *
4 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
5 * http://www.ti.com
6 *
7 * Author: Murali Karicheri <m-karicheri2@ti.com>
8 * Implementation based on pci-exynos.c and pcie-designware.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/irqdomain.h>
19 #include <linux/module.h>
20 #include <linux/msi.h>
21 #include <linux/of_irq.h>
22 #include <linux/of.h>
23 #include <linux/of_pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/phy/phy.h>
26 #include <linux/resource.h>
27 #include <linux/signal.h>
28
29 #include "pcie-designware.h"
30 #include "pci-keystone.h"
31
32 #define DRIVER_NAME "keystone-pcie"
33
34 /* driver specific constants */
35 #define MAX_MSI_HOST_IRQS 8
36 #define MAX_LEGACY_HOST_IRQS 4
37
38 /* DEV_STAT_CTRL */
39 #define PCIE_CAP_BASE 0x70
40
41 /* PCIE controller device IDs */
42 #define PCIE_RC_K2HK 0xb008
43 #define PCIE_RC_K2E 0xb009
44 #define PCIE_RC_K2L 0xb00a
45 #define PCIE_RC_K2G 0xb00b
46
47 #define to_keystone_pcie(x) container_of(x, struct keystone_pcie, pp)
48
quirk_limit_mrrs(struct pci_dev * dev)49 static void quirk_limit_mrrs(struct pci_dev *dev)
50 {
51 struct pci_bus *bus = dev->bus;
52 struct pci_dev *bridge = bus->self;
53 static const struct pci_device_id rc_pci_devids[] = {
54 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
55 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
56 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
57 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
58 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
59 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
60 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G),
61 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
62 { 0, },
63 };
64
65 if (pci_is_root_bus(bus))
66 return;
67
68 /* look for the host bridge */
69 while (!pci_is_root_bus(bus)) {
70 bridge = bus->self;
71 bus = bus->parent;
72 }
73
74 if (bridge) {
75 /*
76 * Keystone PCI controller has a h/w limitation of
77 * 256 bytes maximum read request size. It can't handle
78 * anything higher than this. So force this limit on
79 * all downstream devices.
80 */
81 if (pci_match_id(rc_pci_devids, bridge)) {
82 if (pcie_get_readrq(dev) > 256) {
83 dev_info(&dev->dev, "limiting MRRS to 256\n");
84 pcie_set_readrq(dev, 256);
85 }
86 }
87 }
88 }
89 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
90
ks_pcie_establish_link(struct keystone_pcie * ks_pcie)91 static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
92 {
93 struct pcie_port *pp = &ks_pcie->pp;
94 unsigned int retries;
95
96 dw_pcie_setup_rc(pp);
97
98 if (dw_pcie_link_up(pp)) {
99 dev_err(pp->dev, "Link already up\n");
100 return 0;
101 }
102
103 ks_dw_pcie_initiate_link_train(ks_pcie);
104 /* check if the link is up or not */
105 for (retries = 0; retries < 200; retries++) {
106 if (dw_pcie_link_up(pp))
107 return 0;
108 usleep_range(100, 1000);
109 ks_dw_pcie_initiate_link_train(ks_pcie);
110 }
111
112 dev_err(pp->dev, "phy link never came up\n");
113 return -EINVAL;
114 }
115
ks_pcie_msi_irq_handler(struct irq_desc * desc)116 static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
117 {
118 unsigned int irq = irq_desc_get_irq(desc);
119 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
120 u32 offset = irq - ks_pcie->msi_host_irqs[0];
121 struct pcie_port *pp = &ks_pcie->pp;
122 struct irq_chip *chip = irq_desc_get_chip(desc);
123
124 dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq);
125
126 /*
127 * The chained irq handler installation would have replaced normal
128 * interrupt driver handler so we need to take care of mask/unmask and
129 * ack operation.
130 */
131 chained_irq_enter(chip, desc);
132 ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
133 chained_irq_exit(chip, desc);
134 }
135
136 /**
137 * ks_pcie_legacy_irq_handler() - Handle legacy interrupt
138 * @irq: IRQ line for legacy interrupts
139 * @desc: Pointer to irq descriptor
140 *
141 * Traverse through pending legacy interrupts and invoke handler for each. Also
142 * takes care of interrupt controller level mask/ack operation.
143 */
ks_pcie_legacy_irq_handler(struct irq_desc * desc)144 static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
145 {
146 unsigned int irq = irq_desc_get_irq(desc);
147 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
148 struct pcie_port *pp = &ks_pcie->pp;
149 u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
150 struct irq_chip *chip = irq_desc_get_chip(desc);
151
152 dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq);
153
154 /*
155 * The chained irq handler installation would have replaced normal
156 * interrupt driver handler so we need to take care of mask/unmask and
157 * ack operation.
158 */
159 chained_irq_enter(chip, desc);
160 ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
161 chained_irq_exit(chip, desc);
162 }
163
ks_pcie_get_irq_controller_info(struct keystone_pcie * ks_pcie,char * controller,int * num_irqs)164 static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
165 char *controller, int *num_irqs)
166 {
167 int temp, max_host_irqs, legacy = 1, *host_irqs, ret = -EINVAL;
168 struct device *dev = ks_pcie->pp.dev;
169 struct device_node *np_pcie = dev->of_node, **np_temp;
170
171 if (!strcmp(controller, "msi-interrupt-controller"))
172 legacy = 0;
173
174 if (legacy) {
175 np_temp = &ks_pcie->legacy_intc_np;
176 max_host_irqs = MAX_LEGACY_HOST_IRQS;
177 host_irqs = &ks_pcie->legacy_host_irqs[0];
178 } else {
179 np_temp = &ks_pcie->msi_intc_np;
180 max_host_irqs = MAX_MSI_HOST_IRQS;
181 host_irqs = &ks_pcie->msi_host_irqs[0];
182 }
183
184 /* interrupt controller is in a child node */
185 *np_temp = of_get_child_by_name(np_pcie, controller);
186 if (!(*np_temp)) {
187 dev_err(dev, "Node for %s is absent\n", controller);
188 goto out;
189 }
190 temp = of_irq_count(*np_temp);
191 if (!temp) {
192 of_node_put(*np_temp);
193 goto out;
194 }
195 if (temp > max_host_irqs)
196 dev_warn(dev, "Too many %s interrupts defined %u\n",
197 (legacy ? "legacy" : "MSI"), temp);
198
199 /*
200 * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to
201 * 7 (MSI)
202 */
203 for (temp = 0; temp < max_host_irqs; temp++) {
204 host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp);
205 if (!host_irqs[temp])
206 break;
207 }
208
209 of_node_put(*np_temp);
210
211 if (temp) {
212 *num_irqs = temp;
213 ret = 0;
214 }
215 out:
216 return ret;
217 }
218
ks_pcie_setup_interrupts(struct keystone_pcie * ks_pcie)219 static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
220 {
221 int i;
222
223 /* Legacy IRQ */
224 for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
225 irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
226 ks_pcie_legacy_irq_handler,
227 ks_pcie);
228 }
229 ks_dw_pcie_enable_legacy_irqs(ks_pcie);
230
231 /* MSI IRQ */
232 if (IS_ENABLED(CONFIG_PCI_MSI)) {
233 for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
234 irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
235 ks_pcie_msi_irq_handler,
236 ks_pcie);
237 }
238 }
239 }
240
241 /*
242 * When a PCI device does not exist during config cycles, keystone host gets a
243 * bus error instead of returning 0xffffffff. This handler always returns 0
244 * for this kind of faults.
245 */
keystone_pcie_fault(unsigned long addr,unsigned int fsr,struct pt_regs * regs)246 static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
247 struct pt_regs *regs)
248 {
249 unsigned long instr = *(unsigned long *) instruction_pointer(regs);
250
251 if ((instr & 0x0e100090) == 0x00100090) {
252 int reg = (instr >> 12) & 15;
253
254 regs->uregs[reg] = -1;
255 regs->ARM_pc += 4;
256 }
257
258 return 0;
259 }
260
ks_pcie_host_init(struct pcie_port * pp)261 static void __init ks_pcie_host_init(struct pcie_port *pp)
262 {
263 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
264 u32 val;
265
266 ks_pcie_establish_link(ks_pcie);
267 ks_dw_pcie_setup_rc_app_regs(ks_pcie);
268 ks_pcie_setup_interrupts(ks_pcie);
269 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
270 pp->dbi_base + PCI_IO_BASE);
271
272 /* update the Vendor ID */
273 writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);
274
275 /* update the DEV_STAT_CTRL to publish right mrrs */
276 val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
277 val &= ~PCI_EXP_DEVCTL_READRQ;
278 /* set the mrrs to 256 bytes */
279 val |= BIT(12);
280 writel(val, pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
281
282 /*
283 * PCIe access errors that result into OCP errors are caught by ARM as
284 * "External aborts"
285 */
286 hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
287 "Asynchronous external abort");
288 }
289
290 static struct pcie_host_ops keystone_pcie_host_ops = {
291 .rd_other_conf = ks_dw_pcie_rd_other_conf,
292 .wr_other_conf = ks_dw_pcie_wr_other_conf,
293 .link_up = ks_dw_pcie_link_up,
294 .host_init = ks_pcie_host_init,
295 .msi_set_irq = ks_dw_pcie_msi_set_irq,
296 .msi_clear_irq = ks_dw_pcie_msi_clear_irq,
297 .get_msi_addr = ks_dw_pcie_get_msi_addr,
298 .msi_host_init = ks_dw_pcie_msi_host_init,
299 .scan_bus = ks_dw_pcie_v3_65_scan_bus,
300 };
301
ks_add_pcie_port(struct keystone_pcie * ks_pcie,struct platform_device * pdev)302 static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
303 struct platform_device *pdev)
304 {
305 struct pcie_port *pp = &ks_pcie->pp;
306 int ret;
307
308 ret = ks_pcie_get_irq_controller_info(ks_pcie,
309 "legacy-interrupt-controller",
310 &ks_pcie->num_legacy_host_irqs);
311 if (ret)
312 return ret;
313
314 if (IS_ENABLED(CONFIG_PCI_MSI)) {
315 ret = ks_pcie_get_irq_controller_info(ks_pcie,
316 "msi-interrupt-controller",
317 &ks_pcie->num_msi_host_irqs);
318 if (ret)
319 return ret;
320 }
321
322 pp->root_bus_nr = -1;
323 pp->ops = &keystone_pcie_host_ops;
324 ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
325 if (ret) {
326 dev_err(&pdev->dev, "failed to initialize host\n");
327 return ret;
328 }
329
330 return ret;
331 }
332
333 static const struct of_device_id ks_pcie_of_match[] = {
334 {
335 .type = "pci",
336 .compatible = "ti,keystone-pcie",
337 },
338 { },
339 };
340 MODULE_DEVICE_TABLE(of, ks_pcie_of_match);
341
ks_pcie_remove(struct platform_device * pdev)342 static int __exit ks_pcie_remove(struct platform_device *pdev)
343 {
344 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
345
346 clk_disable_unprepare(ks_pcie->clk);
347
348 return 0;
349 }
350
ks_pcie_probe(struct platform_device * pdev)351 static int __init ks_pcie_probe(struct platform_device *pdev)
352 {
353 struct device *dev = &pdev->dev;
354 struct keystone_pcie *ks_pcie;
355 struct pcie_port *pp;
356 struct resource *res;
357 void __iomem *reg_p;
358 struct phy *phy;
359 int ret = 0;
360
361 ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
362 GFP_KERNEL);
363 if (!ks_pcie)
364 return -ENOMEM;
365
366 pp = &ks_pcie->pp;
367
368 /* initialize SerDes Phy if present */
369 phy = devm_phy_get(dev, "pcie-phy");
370 if (!IS_ERR_OR_NULL(phy)) {
371 ret = phy_init(phy);
372 if (ret < 0)
373 return ret;
374 }
375
376 /* index 2 is to read PCI DEVICE_ID */
377 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
378 reg_p = devm_ioremap_resource(dev, res);
379 if (IS_ERR(reg_p))
380 return PTR_ERR(reg_p);
381 ks_pcie->device_id = readl(reg_p) >> 16;
382 devm_iounmap(dev, reg_p);
383 devm_release_mem_region(dev, res->start, resource_size(res));
384
385 pp->dev = dev;
386 platform_set_drvdata(pdev, ks_pcie);
387 ks_pcie->clk = devm_clk_get(dev, "pcie");
388 if (IS_ERR(ks_pcie->clk)) {
389 dev_err(dev, "Failed to get pcie rc clock\n");
390 return PTR_ERR(ks_pcie->clk);
391 }
392 ret = clk_prepare_enable(ks_pcie->clk);
393 if (ret)
394 return ret;
395
396 ret = ks_add_pcie_port(ks_pcie, pdev);
397 if (ret < 0)
398 goto fail_clk;
399
400 return 0;
401 fail_clk:
402 clk_disable_unprepare(ks_pcie->clk);
403
404 return ret;
405 }
406
407 static struct platform_driver ks_pcie_driver __refdata = {
408 .probe = ks_pcie_probe,
409 .remove = __exit_p(ks_pcie_remove),
410 .driver = {
411 .name = "keystone-pcie",
412 .of_match_table = of_match_ptr(ks_pcie_of_match),
413 },
414 };
415
416 module_platform_driver(ks_pcie_driver);
417
418 MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
419 MODULE_DESCRIPTION("Keystone PCIe host controller driver");
420 MODULE_LICENSE("GPL v2");
421