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1 /*
2  * APM X-Gene MSI Driver
3  *
4  * Copyright (c) 2014, Applied Micro Circuits Corporation
5  * Author: Tanmay Inamdar <tinamdar@apm.com>
6  *	   Duc Dang <dhdang@apm.com>
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18 #include <linux/cpu.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/msi.h>
22 #include <linux/of_irq.h>
23 #include <linux/irqchip/chained_irq.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_pci.h>
27 
28 #define MSI_IR0			0x000000
29 #define MSI_INT0		0x800000
30 #define IDX_PER_GROUP		8
31 #define IRQS_PER_IDX		16
32 #define NR_HW_IRQS		16
33 #define NR_MSI_VEC		(IDX_PER_GROUP * IRQS_PER_IDX * NR_HW_IRQS)
34 
35 struct xgene_msi_group {
36 	struct xgene_msi	*msi;
37 	int			gic_irq;
38 	u32			msi_grp;
39 };
40 
41 struct xgene_msi {
42 	struct device_node	*node;
43 	struct irq_domain	*inner_domain;
44 	struct irq_domain	*msi_domain;
45 	u64			msi_addr;
46 	void __iomem		*msi_regs;
47 	unsigned long		*bitmap;
48 	struct mutex		bitmap_lock;
49 	struct xgene_msi_group	*msi_groups;
50 	int			num_cpus;
51 };
52 
53 /* Global data */
54 static struct xgene_msi xgene_msi_ctrl;
55 
56 static struct irq_chip xgene_msi_top_irq_chip = {
57 	.name		= "X-Gene1 MSI",
58 	.irq_enable	= pci_msi_unmask_irq,
59 	.irq_disable	= pci_msi_mask_irq,
60 	.irq_mask	= pci_msi_mask_irq,
61 	.irq_unmask	= pci_msi_unmask_irq,
62 };
63 
64 static struct  msi_domain_info xgene_msi_domain_info = {
65 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
66 		  MSI_FLAG_PCI_MSIX),
67 	.chip	= &xgene_msi_top_irq_chip,
68 };
69 
70 /*
71  * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where
72  * n is group number (0..F), x is index of registers in each group (0..7)
73  * The register layout is as follows:
74  * MSI0IR0			base_addr
75  * MSI0IR1			base_addr +  0x10000
76  * ...				...
77  * MSI0IR6			base_addr +  0x60000
78  * MSI0IR7			base_addr +  0x70000
79  * MSI1IR0			base_addr +  0x80000
80  * MSI1IR1			base_addr +  0x90000
81  * ...				...
82  * MSI1IR7			base_addr +  0xF0000
83  * MSI2IR0			base_addr + 0x100000
84  * ...				...
85  * MSIFIR0			base_addr + 0x780000
86  * MSIFIR1			base_addr + 0x790000
87  * ...				...
88  * MSIFIR7			base_addr + 0x7F0000
89  * MSIINT0			base_addr + 0x800000
90  * MSIINT1			base_addr + 0x810000
91  * ...				...
92  * MSIINTF			base_addr + 0x8F0000
93  *
94  * Each index register supports 16 MSI vectors (0..15) to generate interrupt.
95  * There are total 16 GIC IRQs assigned for these 16 groups of MSI termination
96  * registers.
97  *
98  * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate
99  * the MSI pending status caused by 1 of its 8 index registers.
100  */
101 
102 /* MSInIRx read helper */
xgene_msi_ir_read(struct xgene_msi * msi,u32 msi_grp,u32 msir_idx)103 static u32 xgene_msi_ir_read(struct xgene_msi *msi,
104 				    u32 msi_grp, u32 msir_idx)
105 {
106 	return readl_relaxed(msi->msi_regs + MSI_IR0 +
107 			      (msi_grp << 19) + (msir_idx << 16));
108 }
109 
110 /* MSIINTn read helper */
xgene_msi_int_read(struct xgene_msi * msi,u32 msi_grp)111 static u32 xgene_msi_int_read(struct xgene_msi *msi, u32 msi_grp)
112 {
113 	return readl_relaxed(msi->msi_regs + MSI_INT0 + (msi_grp << 16));
114 }
115 
116 /*
117  * With 2048 MSI vectors supported, the MSI message can be constructed using
118  * following scheme:
119  * - Divide into 8 256-vector groups
120  *		Group 0: 0-255
121  *		Group 1: 256-511
122  *		Group 2: 512-767
123  *		...
124  *		Group 7: 1792-2047
125  * - Each 256-vector group is divided into 16 16-vector groups
126  *	As an example: 16 16-vector groups for 256-vector group 0-255 is
127  *		Group 0: 0-15
128  *		Group 1: 16-32
129  *		...
130  *		Group 15: 240-255
131  * - The termination address of MSI vector in 256-vector group n and 16-vector
132  *   group x is the address of MSIxIRn
133  * - The data for MSI vector in 16-vector group x is x
134  */
hwirq_to_reg_set(unsigned long hwirq)135 static u32 hwirq_to_reg_set(unsigned long hwirq)
136 {
137 	return (hwirq / (NR_HW_IRQS * IRQS_PER_IDX));
138 }
139 
hwirq_to_group(unsigned long hwirq)140 static u32 hwirq_to_group(unsigned long hwirq)
141 {
142 	return (hwirq % NR_HW_IRQS);
143 }
144 
hwirq_to_msi_data(unsigned long hwirq)145 static u32 hwirq_to_msi_data(unsigned long hwirq)
146 {
147 	return ((hwirq / NR_HW_IRQS) % IRQS_PER_IDX);
148 }
149 
xgene_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)150 static void xgene_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
151 {
152 	struct xgene_msi *msi = irq_data_get_irq_chip_data(data);
153 	u32 reg_set = hwirq_to_reg_set(data->hwirq);
154 	u32 group = hwirq_to_group(data->hwirq);
155 	u64 target_addr = msi->msi_addr + (((8 * group) + reg_set) << 16);
156 
157 	msg->address_hi = upper_32_bits(target_addr);
158 	msg->address_lo = lower_32_bits(target_addr);
159 	msg->data = hwirq_to_msi_data(data->hwirq);
160 }
161 
162 /*
163  * X-Gene v1 only has 16 MSI GIC IRQs for 2048 MSI vectors.  To maintain
164  * the expected behaviour of .set_affinity for each MSI interrupt, the 16
165  * MSI GIC IRQs are statically allocated to 8 X-Gene v1 cores (2 GIC IRQs
166  * for each core).  The MSI vector is moved fom 1 MSI GIC IRQ to another
167  * MSI GIC IRQ to steer its MSI interrupt to correct X-Gene v1 core.  As a
168  * consequence, the total MSI vectors that X-Gene v1 supports will be
169  * reduced to 256 (2048/8) vectors.
170  */
hwirq_to_cpu(unsigned long hwirq)171 static int hwirq_to_cpu(unsigned long hwirq)
172 {
173 	return (hwirq % xgene_msi_ctrl.num_cpus);
174 }
175 
hwirq_to_canonical_hwirq(unsigned long hwirq)176 static unsigned long hwirq_to_canonical_hwirq(unsigned long hwirq)
177 {
178 	return (hwirq - hwirq_to_cpu(hwirq));
179 }
180 
xgene_msi_set_affinity(struct irq_data * irqdata,const struct cpumask * mask,bool force)181 static int xgene_msi_set_affinity(struct irq_data *irqdata,
182 				  const struct cpumask *mask, bool force)
183 {
184 	int target_cpu = cpumask_first(mask);
185 	int curr_cpu;
186 
187 	curr_cpu = hwirq_to_cpu(irqdata->hwirq);
188 	if (curr_cpu == target_cpu)
189 		return IRQ_SET_MASK_OK_DONE;
190 
191 	/* Update MSI number to target the new CPU */
192 	irqdata->hwirq = hwirq_to_canonical_hwirq(irqdata->hwirq) + target_cpu;
193 
194 	return IRQ_SET_MASK_OK;
195 }
196 
197 static struct irq_chip xgene_msi_bottom_irq_chip = {
198 	.name			= "MSI",
199 	.irq_set_affinity       = xgene_msi_set_affinity,
200 	.irq_compose_msi_msg	= xgene_compose_msi_msg,
201 };
202 
xgene_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)203 static int xgene_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
204 				  unsigned int nr_irqs, void *args)
205 {
206 	struct xgene_msi *msi = domain->host_data;
207 	int msi_irq;
208 
209 	mutex_lock(&msi->bitmap_lock);
210 
211 	msi_irq = bitmap_find_next_zero_area(msi->bitmap, NR_MSI_VEC, 0,
212 					     msi->num_cpus, 0);
213 	if (msi_irq < NR_MSI_VEC)
214 		bitmap_set(msi->bitmap, msi_irq, msi->num_cpus);
215 	else
216 		msi_irq = -ENOSPC;
217 
218 	mutex_unlock(&msi->bitmap_lock);
219 
220 	if (msi_irq < 0)
221 		return msi_irq;
222 
223 	irq_domain_set_info(domain, virq, msi_irq,
224 			    &xgene_msi_bottom_irq_chip, domain->host_data,
225 			    handle_simple_irq, NULL, NULL);
226 
227 	return 0;
228 }
229 
xgene_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)230 static void xgene_irq_domain_free(struct irq_domain *domain,
231 				  unsigned int virq, unsigned int nr_irqs)
232 {
233 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
234 	struct xgene_msi *msi = irq_data_get_irq_chip_data(d);
235 	u32 hwirq;
236 
237 	mutex_lock(&msi->bitmap_lock);
238 
239 	hwirq = hwirq_to_canonical_hwirq(d->hwirq);
240 	bitmap_clear(msi->bitmap, hwirq, msi->num_cpus);
241 
242 	mutex_unlock(&msi->bitmap_lock);
243 
244 	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
245 }
246 
247 static const struct irq_domain_ops msi_domain_ops = {
248 	.alloc  = xgene_irq_domain_alloc,
249 	.free   = xgene_irq_domain_free,
250 };
251 
xgene_allocate_domains(struct xgene_msi * msi)252 static int xgene_allocate_domains(struct xgene_msi *msi)
253 {
254 	msi->inner_domain = irq_domain_add_linear(NULL, NR_MSI_VEC,
255 						  &msi_domain_ops, msi);
256 	if (!msi->inner_domain)
257 		return -ENOMEM;
258 
259 	msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(msi->node),
260 						    &xgene_msi_domain_info,
261 						    msi->inner_domain);
262 
263 	if (!msi->msi_domain) {
264 		irq_domain_remove(msi->inner_domain);
265 		return -ENOMEM;
266 	}
267 
268 	return 0;
269 }
270 
xgene_free_domains(struct xgene_msi * msi)271 static void xgene_free_domains(struct xgene_msi *msi)
272 {
273 	if (msi->msi_domain)
274 		irq_domain_remove(msi->msi_domain);
275 	if (msi->inner_domain)
276 		irq_domain_remove(msi->inner_domain);
277 }
278 
xgene_msi_init_allocator(struct xgene_msi * xgene_msi)279 static int xgene_msi_init_allocator(struct xgene_msi *xgene_msi)
280 {
281 	int size = BITS_TO_LONGS(NR_MSI_VEC) * sizeof(long);
282 
283 	xgene_msi->bitmap = kzalloc(size, GFP_KERNEL);
284 	if (!xgene_msi->bitmap)
285 		return -ENOMEM;
286 
287 	mutex_init(&xgene_msi->bitmap_lock);
288 
289 	xgene_msi->msi_groups = kcalloc(NR_HW_IRQS,
290 					sizeof(struct xgene_msi_group),
291 					GFP_KERNEL);
292 	if (!xgene_msi->msi_groups)
293 		return -ENOMEM;
294 
295 	return 0;
296 }
297 
xgene_msi_isr(struct irq_desc * desc)298 static void xgene_msi_isr(struct irq_desc *desc)
299 {
300 	struct irq_chip *chip = irq_desc_get_chip(desc);
301 	struct xgene_msi_group *msi_groups;
302 	struct xgene_msi *xgene_msi;
303 	unsigned int virq;
304 	int msir_index, msir_val, hw_irq;
305 	u32 intr_index, grp_select, msi_grp;
306 
307 	chained_irq_enter(chip, desc);
308 
309 	msi_groups = irq_desc_get_handler_data(desc);
310 	xgene_msi = msi_groups->msi;
311 	msi_grp = msi_groups->msi_grp;
312 
313 	/*
314 	 * MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt
315 	 * If bit x of this register is set (x is 0..7), one or more interupts
316 	 * corresponding to MSInIRx is set.
317 	 */
318 	grp_select = xgene_msi_int_read(xgene_msi, msi_grp);
319 	while (grp_select) {
320 		msir_index = ffs(grp_select) - 1;
321 		/*
322 		 * Calculate MSInIRx address to read to check for interrupts
323 		 * (refer to termination address and data assignment
324 		 * described in xgene_compose_msi_msg() )
325 		 */
326 		msir_val = xgene_msi_ir_read(xgene_msi, msi_grp, msir_index);
327 		while (msir_val) {
328 			intr_index = ffs(msir_val) - 1;
329 			/*
330 			 * Calculate MSI vector number (refer to the termination
331 			 * address and data assignment described in
332 			 * xgene_compose_msi_msg function)
333 			 */
334 			hw_irq = (((msir_index * IRQS_PER_IDX) + intr_index) *
335 				 NR_HW_IRQS) + msi_grp;
336 			/*
337 			 * As we have multiple hw_irq that maps to single MSI,
338 			 * always look up the virq using the hw_irq as seen from
339 			 * CPU0
340 			 */
341 			hw_irq = hwirq_to_canonical_hwirq(hw_irq);
342 			virq = irq_find_mapping(xgene_msi->inner_domain, hw_irq);
343 			WARN_ON(!virq);
344 			if (virq != 0)
345 				generic_handle_irq(virq);
346 			msir_val &= ~(1 << intr_index);
347 		}
348 		grp_select &= ~(1 << msir_index);
349 
350 		if (!grp_select) {
351 			/*
352 			 * We handled all interrupts happened in this group,
353 			 * resample this group MSI_INTx register in case
354 			 * something else has been made pending in the meantime
355 			 */
356 			grp_select = xgene_msi_int_read(xgene_msi, msi_grp);
357 		}
358 	}
359 
360 	chained_irq_exit(chip, desc);
361 }
362 
xgene_msi_remove(struct platform_device * pdev)363 static int xgene_msi_remove(struct platform_device *pdev)
364 {
365 	int virq, i;
366 	struct xgene_msi *msi = platform_get_drvdata(pdev);
367 
368 	for (i = 0; i < NR_HW_IRQS; i++) {
369 		virq = msi->msi_groups[i].gic_irq;
370 		if (virq != 0)
371 			irq_set_chained_handler_and_data(virq, NULL, NULL);
372 	}
373 	kfree(msi->msi_groups);
374 
375 	kfree(msi->bitmap);
376 	msi->bitmap = NULL;
377 
378 	xgene_free_domains(msi);
379 
380 	return 0;
381 }
382 
xgene_msi_hwirq_alloc(unsigned int cpu)383 static int xgene_msi_hwirq_alloc(unsigned int cpu)
384 {
385 	struct xgene_msi *msi = &xgene_msi_ctrl;
386 	struct xgene_msi_group *msi_group;
387 	cpumask_var_t mask;
388 	int i;
389 	int err;
390 
391 	for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) {
392 		msi_group = &msi->msi_groups[i];
393 		if (!msi_group->gic_irq)
394 			continue;
395 
396 		irq_set_chained_handler_and_data(msi_group->gic_irq,
397 			xgene_msi_isr, msi_group);
398 
399 		/*
400 		 * Statically allocate MSI GIC IRQs to each CPU core.
401 		 * With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated
402 		 * to each core.
403 		 */
404 		if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
405 			cpumask_clear(mask);
406 			cpumask_set_cpu(cpu, mask);
407 			err = irq_set_affinity(msi_group->gic_irq, mask);
408 			if (err)
409 				pr_err("failed to set affinity for GIC IRQ");
410 			free_cpumask_var(mask);
411 		} else {
412 			pr_err("failed to alloc CPU mask for affinity\n");
413 			err = -EINVAL;
414 		}
415 
416 		if (err) {
417 			irq_set_chained_handler_and_data(msi_group->gic_irq,
418 							 NULL, NULL);
419 			return err;
420 		}
421 	}
422 
423 	return 0;
424 }
425 
xgene_msi_hwirq_free(unsigned int cpu)426 static void xgene_msi_hwirq_free(unsigned int cpu)
427 {
428 	struct xgene_msi *msi = &xgene_msi_ctrl;
429 	struct xgene_msi_group *msi_group;
430 	int i;
431 
432 	for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) {
433 		msi_group = &msi->msi_groups[i];
434 		if (!msi_group->gic_irq)
435 			continue;
436 
437 		irq_set_chained_handler_and_data(msi_group->gic_irq, NULL,
438 						 NULL);
439 	}
440 }
441 
xgene_msi_cpu_callback(struct notifier_block * nfb,unsigned long action,void * hcpu)442 static int xgene_msi_cpu_callback(struct notifier_block *nfb,
443 				  unsigned long action, void *hcpu)
444 {
445 	unsigned cpu = (unsigned long)hcpu;
446 
447 	switch (action) {
448 	case CPU_ONLINE:
449 	case CPU_ONLINE_FROZEN:
450 		xgene_msi_hwirq_alloc(cpu);
451 		break;
452 	case CPU_DEAD:
453 	case CPU_DEAD_FROZEN:
454 		xgene_msi_hwirq_free(cpu);
455 		break;
456 	default:
457 		break;
458 	}
459 
460 	return NOTIFY_OK;
461 }
462 
463 static struct notifier_block xgene_msi_cpu_notifier = {
464 	.notifier_call = xgene_msi_cpu_callback,
465 };
466 
467 static const struct of_device_id xgene_msi_match_table[] = {
468 	{.compatible = "apm,xgene1-msi"},
469 	{},
470 };
471 
xgene_msi_probe(struct platform_device * pdev)472 static int xgene_msi_probe(struct platform_device *pdev)
473 {
474 	struct resource *res;
475 	int rc, irq_index;
476 	struct xgene_msi *xgene_msi;
477 	unsigned int cpu;
478 	int virt_msir;
479 	u32 msi_val, msi_idx;
480 
481 	xgene_msi = &xgene_msi_ctrl;
482 
483 	platform_set_drvdata(pdev, xgene_msi);
484 
485 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
486 	xgene_msi->msi_regs = devm_ioremap_resource(&pdev->dev, res);
487 	if (IS_ERR(xgene_msi->msi_regs)) {
488 		dev_err(&pdev->dev, "no reg space\n");
489 		rc = -EINVAL;
490 		goto error;
491 	}
492 	xgene_msi->msi_addr = res->start;
493 	xgene_msi->node = pdev->dev.of_node;
494 	xgene_msi->num_cpus = num_possible_cpus();
495 
496 	rc = xgene_msi_init_allocator(xgene_msi);
497 	if (rc) {
498 		dev_err(&pdev->dev, "Error allocating MSI bitmap\n");
499 		goto error;
500 	}
501 
502 	rc = xgene_allocate_domains(xgene_msi);
503 	if (rc) {
504 		dev_err(&pdev->dev, "Failed to allocate MSI domain\n");
505 		goto error;
506 	}
507 
508 	for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) {
509 		virt_msir = platform_get_irq(pdev, irq_index);
510 		if (virt_msir < 0) {
511 			dev_err(&pdev->dev, "Cannot translate IRQ index %d\n",
512 				irq_index);
513 			rc = -EINVAL;
514 			goto error;
515 		}
516 		xgene_msi->msi_groups[irq_index].gic_irq = virt_msir;
517 		xgene_msi->msi_groups[irq_index].msi_grp = irq_index;
518 		xgene_msi->msi_groups[irq_index].msi = xgene_msi;
519 	}
520 
521 	/*
522 	 * MSInIRx registers are read-to-clear; before registering
523 	 * interrupt handlers, read all of them to clear spurious
524 	 * interrupts that may occur before the driver is probed.
525 	 */
526 	for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) {
527 		for (msi_idx = 0; msi_idx < IDX_PER_GROUP; msi_idx++)
528 			msi_val = xgene_msi_ir_read(xgene_msi, irq_index,
529 						    msi_idx);
530 		/* Read MSIINTn to confirm */
531 		msi_val = xgene_msi_int_read(xgene_msi, irq_index);
532 		if (msi_val) {
533 			dev_err(&pdev->dev, "Failed to clear spurious IRQ\n");
534 			rc = -EINVAL;
535 			goto error;
536 		}
537 	}
538 
539 	cpu_notifier_register_begin();
540 
541 	for_each_online_cpu(cpu)
542 		if (xgene_msi_hwirq_alloc(cpu)) {
543 			dev_err(&pdev->dev, "failed to register MSI handlers\n");
544 			cpu_notifier_register_done();
545 			goto error;
546 		}
547 
548 	rc = __register_hotcpu_notifier(&xgene_msi_cpu_notifier);
549 	if (rc) {
550 		dev_err(&pdev->dev, "failed to add CPU MSI notifier\n");
551 		cpu_notifier_register_done();
552 		goto error;
553 	}
554 
555 	cpu_notifier_register_done();
556 
557 	dev_info(&pdev->dev, "APM X-Gene PCIe MSI driver loaded\n");
558 
559 	return 0;
560 
561 error:
562 	xgene_msi_remove(pdev);
563 	return rc;
564 }
565 
566 static struct platform_driver xgene_msi_driver = {
567 	.driver = {
568 		.name = "xgene-msi",
569 		.of_match_table = xgene_msi_match_table,
570 	},
571 	.probe = xgene_msi_probe,
572 	.remove = xgene_msi_remove,
573 };
574 
xgene_pcie_msi_init(void)575 static int __init xgene_pcie_msi_init(void)
576 {
577 	return platform_driver_register(&xgene_msi_driver);
578 }
579 subsys_initcall(xgene_pcie_msi_init);
580