1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <asm-generic/pci-bridge.h>
19 #include "pci.h"
20
21 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
22 #define CARDBUS_RESERVE_BUSNR 3
23
24 static struct resource busn_resource = {
25 .name = "PCI busn",
26 .start = 0,
27 .end = 255,
28 .flags = IORESOURCE_BUS,
29 };
30
31 /* Ugh. Need to stop exporting this to modules. */
32 LIST_HEAD(pci_root_buses);
33 EXPORT_SYMBOL(pci_root_buses);
34
35 static LIST_HEAD(pci_domain_busn_res_list);
36
37 struct pci_domain_busn_res {
38 struct list_head list;
39 struct resource res;
40 int domain_nr;
41 };
42
get_pci_domain_busn_res(int domain_nr)43 static struct resource *get_pci_domain_busn_res(int domain_nr)
44 {
45 struct pci_domain_busn_res *r;
46
47 list_for_each_entry(r, &pci_domain_busn_res_list, list)
48 if (r->domain_nr == domain_nr)
49 return &r->res;
50
51 r = kzalloc(sizeof(*r), GFP_KERNEL);
52 if (!r)
53 return NULL;
54
55 r->domain_nr = domain_nr;
56 r->res.start = 0;
57 r->res.end = 0xff;
58 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
59
60 list_add_tail(&r->list, &pci_domain_busn_res_list);
61
62 return &r->res;
63 }
64
find_anything(struct device * dev,void * data)65 static int find_anything(struct device *dev, void *data)
66 {
67 return 1;
68 }
69
70 /*
71 * Some device drivers need know if pci is initiated.
72 * Basically, we think pci is not initiated when there
73 * is no device to be found on the pci_bus_type.
74 */
no_pci_devices(void)75 int no_pci_devices(void)
76 {
77 struct device *dev;
78 int no_devices;
79
80 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
81 no_devices = (dev == NULL);
82 put_device(dev);
83 return no_devices;
84 }
85 EXPORT_SYMBOL(no_pci_devices);
86
87 /*
88 * PCI Bus Class
89 */
release_pcibus_dev(struct device * dev)90 static void release_pcibus_dev(struct device *dev)
91 {
92 struct pci_bus *pci_bus = to_pci_bus(dev);
93
94 put_device(pci_bus->bridge);
95 pci_bus_remove_resources(pci_bus);
96 pci_release_bus_of_node(pci_bus);
97 kfree(pci_bus);
98 }
99
100 static struct class pcibus_class = {
101 .name = "pci_bus",
102 .dev_release = &release_pcibus_dev,
103 .dev_groups = pcibus_groups,
104 };
105
pcibus_class_init(void)106 static int __init pcibus_class_init(void)
107 {
108 return class_register(&pcibus_class);
109 }
110 postcore_initcall(pcibus_class_init);
111
pci_size(u64 base,u64 maxbase,u64 mask)112 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
113 {
114 u64 size = mask & maxbase; /* Find the significant bits */
115 if (!size)
116 return 0;
117
118 /* Get the lowest of them to find the decode size, and
119 from that the extent. */
120 size = (size & ~(size-1)) - 1;
121
122 /* base == maxbase can be valid only if the BAR has
123 already been programmed with all 1s. */
124 if (base == maxbase && ((base | size) & mask) != mask)
125 return 0;
126
127 return size;
128 }
129
decode_bar(struct pci_dev * dev,u32 bar)130 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
131 {
132 u32 mem_type;
133 unsigned long flags;
134
135 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
136 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
137 flags |= IORESOURCE_IO;
138 return flags;
139 }
140
141 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
142 flags |= IORESOURCE_MEM;
143 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
144 flags |= IORESOURCE_PREFETCH;
145
146 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
147 switch (mem_type) {
148 case PCI_BASE_ADDRESS_MEM_TYPE_32:
149 break;
150 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
151 /* 1M mem BAR treated as 32-bit BAR */
152 break;
153 case PCI_BASE_ADDRESS_MEM_TYPE_64:
154 flags |= IORESOURCE_MEM_64;
155 break;
156 default:
157 /* mem unknown type treated as 32-bit BAR */
158 break;
159 }
160 return flags;
161 }
162
163 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
164
165 /**
166 * pci_read_base - read a PCI BAR
167 * @dev: the PCI device
168 * @type: type of the BAR
169 * @res: resource buffer to be filled in
170 * @pos: BAR position in the config space
171 *
172 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
173 */
__pci_read_base(struct pci_dev * dev,enum pci_bar_type type,struct resource * res,unsigned int pos)174 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
175 struct resource *res, unsigned int pos)
176 {
177 u32 l, sz, mask;
178 u64 l64, sz64, mask64;
179 u16 orig_cmd;
180 struct pci_bus_region region, inverted_region;
181
182 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
183
184 /* No printks while decoding is disabled! */
185 if (!dev->mmio_always_on) {
186 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
187 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
188 pci_write_config_word(dev, PCI_COMMAND,
189 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
190 }
191 }
192
193 res->name = pci_name(dev);
194
195 pci_read_config_dword(dev, pos, &l);
196 pci_write_config_dword(dev, pos, l | mask);
197 pci_read_config_dword(dev, pos, &sz);
198 pci_write_config_dword(dev, pos, l);
199
200 /*
201 * All bits set in sz means the device isn't working properly.
202 * If the BAR isn't implemented, all bits must be 0. If it's a
203 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
204 * 1 must be clear.
205 */
206 if (sz == 0xffffffff)
207 sz = 0;
208
209 /*
210 * I don't know how l can have all bits set. Copied from old code.
211 * Maybe it fixes a bug on some ancient platform.
212 */
213 if (l == 0xffffffff)
214 l = 0;
215
216 if (type == pci_bar_unknown) {
217 res->flags = decode_bar(dev, l);
218 res->flags |= IORESOURCE_SIZEALIGN;
219 if (res->flags & IORESOURCE_IO) {
220 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
221 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
222 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
223 } else {
224 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
225 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
226 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
227 }
228 } else {
229 if (l & PCI_ROM_ADDRESS_ENABLE)
230 res->flags |= IORESOURCE_ROM_ENABLE;
231 l64 = l & PCI_ROM_ADDRESS_MASK;
232 sz64 = sz & PCI_ROM_ADDRESS_MASK;
233 mask64 = PCI_ROM_ADDRESS_MASK;
234 }
235
236 if (res->flags & IORESOURCE_MEM_64) {
237 pci_read_config_dword(dev, pos + 4, &l);
238 pci_write_config_dword(dev, pos + 4, ~0);
239 pci_read_config_dword(dev, pos + 4, &sz);
240 pci_write_config_dword(dev, pos + 4, l);
241
242 l64 |= ((u64)l << 32);
243 sz64 |= ((u64)sz << 32);
244 mask64 |= ((u64)~0 << 32);
245 }
246
247 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
248 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
249
250 if (!sz64)
251 goto fail;
252
253 sz64 = pci_size(l64, sz64, mask64);
254 if (!sz64) {
255 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
256 pos);
257 goto fail;
258 }
259
260 if (res->flags & IORESOURCE_MEM_64) {
261 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
262 && sz64 > 0x100000000ULL) {
263 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
264 res->start = 0;
265 res->end = 0;
266 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
267 pos, (unsigned long long)sz64);
268 goto out;
269 }
270
271 if ((sizeof(pci_bus_addr_t) < 8) && l) {
272 /* Above 32-bit boundary; try to reallocate */
273 res->flags |= IORESOURCE_UNSET;
274 res->start = 0;
275 res->end = sz64;
276 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
277 pos, (unsigned long long)l64);
278 goto out;
279 }
280 }
281
282 region.start = l64;
283 region.end = l64 + sz64;
284
285 pcibios_bus_to_resource(dev->bus, res, ®ion);
286 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
287
288 /*
289 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
290 * the corresponding resource address (the physical address used by
291 * the CPU. Converting that resource address back to a bus address
292 * should yield the original BAR value:
293 *
294 * resource_to_bus(bus_to_resource(A)) == A
295 *
296 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
297 * be claimed by the device.
298 */
299 if (inverted_region.start != region.start) {
300 res->flags |= IORESOURCE_UNSET;
301 res->start = 0;
302 res->end = region.end - region.start;
303 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
304 pos, (unsigned long long)region.start);
305 }
306
307 goto out;
308
309
310 fail:
311 res->flags = 0;
312 out:
313 if (res->flags)
314 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
315
316 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
317 }
318
pci_read_bases(struct pci_dev * dev,unsigned int howmany,int rom)319 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
320 {
321 unsigned int pos, reg;
322
323 if (dev->non_compliant_bars)
324 return;
325
326 for (pos = 0; pos < howmany; pos++) {
327 struct resource *res = &dev->resource[pos];
328 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
329 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
330 }
331
332 if (rom) {
333 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
334 dev->rom_base_reg = rom;
335 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
336 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
337 __pci_read_base(dev, pci_bar_mem32, res, rom);
338 }
339 }
340
pci_read_bridge_io(struct pci_bus * child)341 static void pci_read_bridge_io(struct pci_bus *child)
342 {
343 struct pci_dev *dev = child->self;
344 u8 io_base_lo, io_limit_lo;
345 unsigned long io_mask, io_granularity, base, limit;
346 struct pci_bus_region region;
347 struct resource *res;
348
349 io_mask = PCI_IO_RANGE_MASK;
350 io_granularity = 0x1000;
351 if (dev->io_window_1k) {
352 /* Support 1K I/O space granularity */
353 io_mask = PCI_IO_1K_RANGE_MASK;
354 io_granularity = 0x400;
355 }
356
357 res = child->resource[0];
358 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
359 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
360 base = (io_base_lo & io_mask) << 8;
361 limit = (io_limit_lo & io_mask) << 8;
362
363 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
364 u16 io_base_hi, io_limit_hi;
365
366 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
367 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
368 base |= ((unsigned long) io_base_hi << 16);
369 limit |= ((unsigned long) io_limit_hi << 16);
370 }
371
372 if (base <= limit) {
373 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
374 region.start = base;
375 region.end = limit + io_granularity - 1;
376 pcibios_bus_to_resource(dev->bus, res, ®ion);
377 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
378 }
379 }
380
pci_read_bridge_mmio(struct pci_bus * child)381 static void pci_read_bridge_mmio(struct pci_bus *child)
382 {
383 struct pci_dev *dev = child->self;
384 u16 mem_base_lo, mem_limit_lo;
385 unsigned long base, limit;
386 struct pci_bus_region region;
387 struct resource *res;
388
389 res = child->resource[1];
390 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
391 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
392 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
393 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
394 if (base <= limit) {
395 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
396 region.start = base;
397 region.end = limit + 0xfffff;
398 pcibios_bus_to_resource(dev->bus, res, ®ion);
399 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
400 }
401 }
402
pci_read_bridge_mmio_pref(struct pci_bus * child)403 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
404 {
405 struct pci_dev *dev = child->self;
406 u16 mem_base_lo, mem_limit_lo;
407 u64 base64, limit64;
408 pci_bus_addr_t base, limit;
409 struct pci_bus_region region;
410 struct resource *res;
411
412 res = child->resource[2];
413 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
414 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
415 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
416 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
417
418 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
419 u32 mem_base_hi, mem_limit_hi;
420
421 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
422 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
423
424 /*
425 * Some bridges set the base > limit by default, and some
426 * (broken) BIOSes do not initialize them. If we find
427 * this, just assume they are not being used.
428 */
429 if (mem_base_hi <= mem_limit_hi) {
430 base64 |= (u64) mem_base_hi << 32;
431 limit64 |= (u64) mem_limit_hi << 32;
432 }
433 }
434
435 base = (pci_bus_addr_t) base64;
436 limit = (pci_bus_addr_t) limit64;
437
438 if (base != base64) {
439 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
440 (unsigned long long) base64);
441 return;
442 }
443
444 if (base <= limit) {
445 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
446 IORESOURCE_MEM | IORESOURCE_PREFETCH;
447 if (res->flags & PCI_PREF_RANGE_TYPE_64)
448 res->flags |= IORESOURCE_MEM_64;
449 region.start = base;
450 region.end = limit + 0xfffff;
451 pcibios_bus_to_resource(dev->bus, res, ®ion);
452 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
453 }
454 }
455
pci_read_bridge_bases(struct pci_bus * child)456 void pci_read_bridge_bases(struct pci_bus *child)
457 {
458 struct pci_dev *dev = child->self;
459 struct resource *res;
460 int i;
461
462 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
463 return;
464
465 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
466 &child->busn_res,
467 dev->transparent ? " (subtractive decode)" : "");
468
469 pci_bus_remove_resources(child);
470 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
471 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
472
473 pci_read_bridge_io(child);
474 pci_read_bridge_mmio(child);
475 pci_read_bridge_mmio_pref(child);
476
477 if (dev->transparent) {
478 pci_bus_for_each_resource(child->parent, res, i) {
479 if (res && res->flags) {
480 pci_bus_add_resource(child, res,
481 PCI_SUBTRACTIVE_DECODE);
482 dev_printk(KERN_DEBUG, &dev->dev,
483 " bridge window %pR (subtractive decode)\n",
484 res);
485 }
486 }
487 }
488 }
489
pci_alloc_bus(struct pci_bus * parent)490 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
491 {
492 struct pci_bus *b;
493
494 b = kzalloc(sizeof(*b), GFP_KERNEL);
495 if (!b)
496 return NULL;
497
498 INIT_LIST_HEAD(&b->node);
499 INIT_LIST_HEAD(&b->children);
500 INIT_LIST_HEAD(&b->devices);
501 INIT_LIST_HEAD(&b->slots);
502 INIT_LIST_HEAD(&b->resources);
503 b->max_bus_speed = PCI_SPEED_UNKNOWN;
504 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
505 #ifdef CONFIG_PCI_DOMAINS_GENERIC
506 if (parent)
507 b->domain_nr = parent->domain_nr;
508 #endif
509 return b;
510 }
511
pci_release_host_bridge_dev(struct device * dev)512 static void pci_release_host_bridge_dev(struct device *dev)
513 {
514 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
515
516 if (bridge->release_fn)
517 bridge->release_fn(bridge);
518
519 pci_free_resource_list(&bridge->windows);
520
521 kfree(bridge);
522 }
523
pci_alloc_host_bridge(struct pci_bus * b)524 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
525 {
526 struct pci_host_bridge *bridge;
527
528 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
529 if (!bridge)
530 return NULL;
531
532 INIT_LIST_HEAD(&bridge->windows);
533 bridge->bus = b;
534 return bridge;
535 }
536
537 static const unsigned char pcix_bus_speed[] = {
538 PCI_SPEED_UNKNOWN, /* 0 */
539 PCI_SPEED_66MHz_PCIX, /* 1 */
540 PCI_SPEED_100MHz_PCIX, /* 2 */
541 PCI_SPEED_133MHz_PCIX, /* 3 */
542 PCI_SPEED_UNKNOWN, /* 4 */
543 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
544 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
545 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
546 PCI_SPEED_UNKNOWN, /* 8 */
547 PCI_SPEED_66MHz_PCIX_266, /* 9 */
548 PCI_SPEED_100MHz_PCIX_266, /* A */
549 PCI_SPEED_133MHz_PCIX_266, /* B */
550 PCI_SPEED_UNKNOWN, /* C */
551 PCI_SPEED_66MHz_PCIX_533, /* D */
552 PCI_SPEED_100MHz_PCIX_533, /* E */
553 PCI_SPEED_133MHz_PCIX_533 /* F */
554 };
555
556 const unsigned char pcie_link_speed[] = {
557 PCI_SPEED_UNKNOWN, /* 0 */
558 PCIE_SPEED_2_5GT, /* 1 */
559 PCIE_SPEED_5_0GT, /* 2 */
560 PCIE_SPEED_8_0GT, /* 3 */
561 PCI_SPEED_UNKNOWN, /* 4 */
562 PCI_SPEED_UNKNOWN, /* 5 */
563 PCI_SPEED_UNKNOWN, /* 6 */
564 PCI_SPEED_UNKNOWN, /* 7 */
565 PCI_SPEED_UNKNOWN, /* 8 */
566 PCI_SPEED_UNKNOWN, /* 9 */
567 PCI_SPEED_UNKNOWN, /* A */
568 PCI_SPEED_UNKNOWN, /* B */
569 PCI_SPEED_UNKNOWN, /* C */
570 PCI_SPEED_UNKNOWN, /* D */
571 PCI_SPEED_UNKNOWN, /* E */
572 PCI_SPEED_UNKNOWN /* F */
573 };
574
pcie_update_link_speed(struct pci_bus * bus,u16 linksta)575 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
576 {
577 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
578 }
579 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
580
581 static unsigned char agp_speeds[] = {
582 AGP_UNKNOWN,
583 AGP_1X,
584 AGP_2X,
585 AGP_4X,
586 AGP_8X
587 };
588
agp_speed(int agp3,int agpstat)589 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
590 {
591 int index = 0;
592
593 if (agpstat & 4)
594 index = 3;
595 else if (agpstat & 2)
596 index = 2;
597 else if (agpstat & 1)
598 index = 1;
599 else
600 goto out;
601
602 if (agp3) {
603 index += 2;
604 if (index == 5)
605 index = 0;
606 }
607
608 out:
609 return agp_speeds[index];
610 }
611
pci_set_bus_speed(struct pci_bus * bus)612 static void pci_set_bus_speed(struct pci_bus *bus)
613 {
614 struct pci_dev *bridge = bus->self;
615 int pos;
616
617 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
618 if (!pos)
619 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
620 if (pos) {
621 u32 agpstat, agpcmd;
622
623 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
624 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
625
626 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
627 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
628 }
629
630 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
631 if (pos) {
632 u16 status;
633 enum pci_bus_speed max;
634
635 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
636 &status);
637
638 if (status & PCI_X_SSTATUS_533MHZ) {
639 max = PCI_SPEED_133MHz_PCIX_533;
640 } else if (status & PCI_X_SSTATUS_266MHZ) {
641 max = PCI_SPEED_133MHz_PCIX_266;
642 } else if (status & PCI_X_SSTATUS_133MHZ) {
643 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
644 max = PCI_SPEED_133MHz_PCIX_ECC;
645 else
646 max = PCI_SPEED_133MHz_PCIX;
647 } else {
648 max = PCI_SPEED_66MHz_PCIX;
649 }
650
651 bus->max_bus_speed = max;
652 bus->cur_bus_speed = pcix_bus_speed[
653 (status & PCI_X_SSTATUS_FREQ) >> 6];
654
655 return;
656 }
657
658 if (pci_is_pcie(bridge)) {
659 u32 linkcap;
660 u16 linksta;
661
662 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
663 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
664
665 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
666 pcie_update_link_speed(bus, linksta);
667 }
668 }
669
pci_host_bridge_msi_domain(struct pci_bus * bus)670 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
671 {
672 struct irq_domain *d;
673
674 /*
675 * Any firmware interface that can resolve the msi_domain
676 * should be called from here.
677 */
678 d = pci_host_bridge_of_msi_domain(bus);
679
680 return d;
681 }
682
pci_set_bus_msi_domain(struct pci_bus * bus)683 static void pci_set_bus_msi_domain(struct pci_bus *bus)
684 {
685 struct irq_domain *d;
686 struct pci_bus *b;
687
688 /*
689 * The bus can be a root bus, a subordinate bus, or a virtual bus
690 * created by an SR-IOV device. Walk up to the first bridge device
691 * found or derive the domain from the host bridge.
692 */
693 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
694 if (b->self)
695 d = dev_get_msi_domain(&b->self->dev);
696 }
697
698 if (!d)
699 d = pci_host_bridge_msi_domain(b);
700
701 dev_set_msi_domain(&bus->dev, d);
702 }
703
pci_alloc_child_bus(struct pci_bus * parent,struct pci_dev * bridge,int busnr)704 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
705 struct pci_dev *bridge, int busnr)
706 {
707 struct pci_bus *child;
708 int i;
709 int ret;
710
711 /*
712 * Allocate a new bus, and inherit stuff from the parent..
713 */
714 child = pci_alloc_bus(parent);
715 if (!child)
716 return NULL;
717
718 child->parent = parent;
719 child->ops = parent->ops;
720 child->msi = parent->msi;
721 child->sysdata = parent->sysdata;
722 child->bus_flags = parent->bus_flags;
723
724 /* initialize some portions of the bus device, but don't register it
725 * now as the parent is not properly set up yet.
726 */
727 child->dev.class = &pcibus_class;
728 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
729
730 /*
731 * Set up the primary, secondary and subordinate
732 * bus numbers.
733 */
734 child->number = child->busn_res.start = busnr;
735 child->primary = parent->busn_res.start;
736 child->busn_res.end = 0xff;
737
738 if (!bridge) {
739 child->dev.parent = parent->bridge;
740 goto add_dev;
741 }
742
743 child->self = bridge;
744 child->bridge = get_device(&bridge->dev);
745 child->dev.parent = child->bridge;
746 pci_set_bus_of_node(child);
747 pci_set_bus_speed(child);
748
749 /* Set up default resource pointers and names.. */
750 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
751 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
752 child->resource[i]->name = child->name;
753 }
754 bridge->subordinate = child;
755
756 add_dev:
757 pci_set_bus_msi_domain(child);
758 ret = device_register(&child->dev);
759 WARN_ON(ret < 0);
760
761 pcibios_add_bus(child);
762
763 /* Create legacy_io and legacy_mem files for this bus */
764 pci_create_legacy_files(child);
765
766 return child;
767 }
768
pci_add_new_bus(struct pci_bus * parent,struct pci_dev * dev,int busnr)769 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
770 int busnr)
771 {
772 struct pci_bus *child;
773
774 child = pci_alloc_child_bus(parent, dev, busnr);
775 if (child) {
776 down_write(&pci_bus_sem);
777 list_add_tail(&child->node, &parent->children);
778 up_write(&pci_bus_sem);
779 }
780 return child;
781 }
782 EXPORT_SYMBOL(pci_add_new_bus);
783
pci_enable_crs(struct pci_dev * pdev)784 static void pci_enable_crs(struct pci_dev *pdev)
785 {
786 u16 root_cap = 0;
787
788 /* Enable CRS Software Visibility if supported */
789 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
790 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
791 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
792 PCI_EXP_RTCTL_CRSSVE);
793 }
794
795 /*
796 * If it's a bridge, configure it and scan the bus behind it.
797 * For CardBus bridges, we don't scan behind as the devices will
798 * be handled by the bridge driver itself.
799 *
800 * We need to process bridges in two passes -- first we scan those
801 * already configured by the BIOS and after we are done with all of
802 * them, we proceed to assigning numbers to the remaining buses in
803 * order to avoid overlaps between old and new bus numbers.
804 */
pci_scan_bridge(struct pci_bus * bus,struct pci_dev * dev,int max,int pass)805 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
806 {
807 struct pci_bus *child;
808 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
809 u32 buses, i, j = 0;
810 u16 bctl;
811 u8 primary, secondary, subordinate;
812 int broken = 0;
813
814 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
815 primary = buses & 0xFF;
816 secondary = (buses >> 8) & 0xFF;
817 subordinate = (buses >> 16) & 0xFF;
818
819 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
820 secondary, subordinate, pass);
821
822 if (!primary && (primary != bus->number) && secondary && subordinate) {
823 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
824 primary = bus->number;
825 }
826
827 /* Check if setup is sensible at all */
828 if (!pass &&
829 (primary != bus->number || secondary <= bus->number ||
830 secondary > subordinate)) {
831 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
832 secondary, subordinate);
833 broken = 1;
834 }
835
836 /* Disable MasterAbortMode during probing to avoid reporting
837 of bus errors (in some architectures) */
838 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
839 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
840 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
841
842 pci_enable_crs(dev);
843
844 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
845 !is_cardbus && !broken) {
846 unsigned int cmax;
847 /*
848 * Bus already configured by firmware, process it in the first
849 * pass and just note the configuration.
850 */
851 if (pass)
852 goto out;
853
854 /*
855 * The bus might already exist for two reasons: Either we are
856 * rescanning the bus or the bus is reachable through more than
857 * one bridge. The second case can happen with the i450NX
858 * chipset.
859 */
860 child = pci_find_bus(pci_domain_nr(bus), secondary);
861 if (!child) {
862 child = pci_add_new_bus(bus, dev, secondary);
863 if (!child)
864 goto out;
865 child->primary = primary;
866 pci_bus_insert_busn_res(child, secondary, subordinate);
867 child->bridge_ctl = bctl;
868 }
869
870 cmax = pci_scan_child_bus(child);
871 if (cmax > subordinate)
872 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
873 subordinate, cmax);
874 /* subordinate should equal child->busn_res.end */
875 if (subordinate > max)
876 max = subordinate;
877 } else {
878 /*
879 * We need to assign a number to this bus which we always
880 * do in the second pass.
881 */
882 if (!pass) {
883 if (pcibios_assign_all_busses() || broken || is_cardbus)
884 /* Temporarily disable forwarding of the
885 configuration cycles on all bridges in
886 this bus segment to avoid possible
887 conflicts in the second pass between two
888 bridges programmed with overlapping
889 bus ranges. */
890 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
891 buses & ~0xffffff);
892 goto out;
893 }
894
895 /* Clear errors */
896 pci_write_config_word(dev, PCI_STATUS, 0xffff);
897
898 /* Prevent assigning a bus number that already exists.
899 * This can happen when a bridge is hot-plugged, so in
900 * this case we only re-scan this bus. */
901 child = pci_find_bus(pci_domain_nr(bus), max+1);
902 if (!child) {
903 child = pci_add_new_bus(bus, dev, max+1);
904 if (!child)
905 goto out;
906 pci_bus_insert_busn_res(child, max+1, 0xff);
907 }
908 max++;
909 buses = (buses & 0xff000000)
910 | ((unsigned int)(child->primary) << 0)
911 | ((unsigned int)(child->busn_res.start) << 8)
912 | ((unsigned int)(child->busn_res.end) << 16);
913
914 /*
915 * yenta.c forces a secondary latency timer of 176.
916 * Copy that behaviour here.
917 */
918 if (is_cardbus) {
919 buses &= ~0xff000000;
920 buses |= CARDBUS_LATENCY_TIMER << 24;
921 }
922
923 /*
924 * We need to blast all three values with a single write.
925 */
926 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
927
928 if (!is_cardbus) {
929 child->bridge_ctl = bctl;
930 max = pci_scan_child_bus(child);
931 } else {
932 /*
933 * For CardBus bridges, we leave 4 bus numbers
934 * as cards with a PCI-to-PCI bridge can be
935 * inserted later.
936 */
937 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
938 struct pci_bus *parent = bus;
939 if (pci_find_bus(pci_domain_nr(bus),
940 max+i+1))
941 break;
942 while (parent->parent) {
943 if ((!pcibios_assign_all_busses()) &&
944 (parent->busn_res.end > max) &&
945 (parent->busn_res.end <= max+i)) {
946 j = 1;
947 }
948 parent = parent->parent;
949 }
950 if (j) {
951 /*
952 * Often, there are two cardbus bridges
953 * -- try to leave one valid bus number
954 * for each one.
955 */
956 i /= 2;
957 break;
958 }
959 }
960 max += i;
961 }
962 /*
963 * Set the subordinate bus number to its real value.
964 */
965 pci_bus_update_busn_res_end(child, max);
966 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
967 }
968
969 sprintf(child->name,
970 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
971 pci_domain_nr(bus), child->number);
972
973 /* Has only triggered on CardBus, fixup is in yenta_socket */
974 while (bus->parent) {
975 if ((child->busn_res.end > bus->busn_res.end) ||
976 (child->number > bus->busn_res.end) ||
977 (child->number < bus->number) ||
978 (child->busn_res.end < bus->number)) {
979 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
980 &child->busn_res,
981 (bus->number > child->busn_res.end &&
982 bus->busn_res.end < child->number) ?
983 "wholly" : "partially",
984 bus->self->transparent ? " transparent" : "",
985 dev_name(&bus->dev),
986 &bus->busn_res);
987 }
988 bus = bus->parent;
989 }
990
991 out:
992 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
993
994 return max;
995 }
996 EXPORT_SYMBOL(pci_scan_bridge);
997
998 /*
999 * Read interrupt line and base address registers.
1000 * The architecture-dependent code can tweak these, of course.
1001 */
pci_read_irq(struct pci_dev * dev)1002 static void pci_read_irq(struct pci_dev *dev)
1003 {
1004 unsigned char irq;
1005
1006 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1007 dev->pin = irq;
1008 if (irq)
1009 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1010 dev->irq = irq;
1011 }
1012
set_pcie_port_type(struct pci_dev * pdev)1013 void set_pcie_port_type(struct pci_dev *pdev)
1014 {
1015 int pos;
1016 u16 reg16;
1017 int type;
1018 struct pci_dev *parent;
1019
1020 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1021 if (!pos)
1022 return;
1023
1024 pdev->pcie_cap = pos;
1025 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1026 pdev->pcie_flags_reg = reg16;
1027 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1028 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1029
1030 /*
1031 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1032 * of a Link. No PCIe component has two Links. Two Links are
1033 * connected by a Switch that has a Port on each Link and internal
1034 * logic to connect the two Ports.
1035 */
1036 type = pci_pcie_type(pdev);
1037 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1038 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1039 pdev->has_secondary_link = 1;
1040 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1041 type == PCI_EXP_TYPE_DOWNSTREAM) {
1042 parent = pci_upstream_bridge(pdev);
1043
1044 /*
1045 * Usually there's an upstream device (Root Port or Switch
1046 * Downstream Port), but we can't assume one exists.
1047 */
1048 if (parent && !parent->has_secondary_link)
1049 pdev->has_secondary_link = 1;
1050 }
1051 }
1052
set_pcie_hotplug_bridge(struct pci_dev * pdev)1053 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1054 {
1055 u32 reg32;
1056
1057 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1058 if (reg32 & PCI_EXP_SLTCAP_HPC)
1059 pdev->is_hotplug_bridge = 1;
1060 }
1061
1062 /**
1063 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1064 * @dev: PCI device
1065 *
1066 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1067 * when forwarding a type1 configuration request the bridge must check that
1068 * the extended register address field is zero. The bridge is not permitted
1069 * to forward the transactions and must handle it as an Unsupported Request.
1070 * Some bridges do not follow this rule and simply drop the extended register
1071 * bits, resulting in the standard config space being aliased, every 256
1072 * bytes across the entire configuration space. Test for this condition by
1073 * comparing the first dword of each potential alias to the vendor/device ID.
1074 * Known offenders:
1075 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1076 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1077 */
pci_ext_cfg_is_aliased(struct pci_dev * dev)1078 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1079 {
1080 #ifdef CONFIG_PCI_QUIRKS
1081 int pos;
1082 u32 header, tmp;
1083
1084 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1085
1086 for (pos = PCI_CFG_SPACE_SIZE;
1087 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1088 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1089 || header != tmp)
1090 return false;
1091 }
1092
1093 return true;
1094 #else
1095 return false;
1096 #endif
1097 }
1098
1099 /**
1100 * pci_cfg_space_size - get the configuration space size of the PCI device.
1101 * @dev: PCI device
1102 *
1103 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1104 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1105 * access it. Maybe we don't have a way to generate extended config space
1106 * accesses, or the device is behind a reverse Express bridge. So we try
1107 * reading the dword at 0x100 which must either be 0 or a valid extended
1108 * capability header.
1109 */
pci_cfg_space_size_ext(struct pci_dev * dev)1110 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1111 {
1112 u32 status;
1113 int pos = PCI_CFG_SPACE_SIZE;
1114
1115 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1116 goto fail;
1117 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1118 goto fail;
1119
1120 return PCI_CFG_SPACE_EXP_SIZE;
1121
1122 fail:
1123 return PCI_CFG_SPACE_SIZE;
1124 }
1125
pci_cfg_space_size(struct pci_dev * dev)1126 int pci_cfg_space_size(struct pci_dev *dev)
1127 {
1128 int pos;
1129 u32 status;
1130 u16 class;
1131
1132 class = dev->class >> 8;
1133 if (class == PCI_CLASS_BRIDGE_HOST)
1134 return pci_cfg_space_size_ext(dev);
1135
1136 if (!pci_is_pcie(dev)) {
1137 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1138 if (!pos)
1139 goto fail;
1140
1141 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1142 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1143 goto fail;
1144 }
1145
1146 return pci_cfg_space_size_ext(dev);
1147
1148 fail:
1149 return PCI_CFG_SPACE_SIZE;
1150 }
1151
1152 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1153
pci_msi_setup_pci_dev(struct pci_dev * dev)1154 void pci_msi_setup_pci_dev(struct pci_dev *dev)
1155 {
1156 /*
1157 * Disable the MSI hardware to avoid screaming interrupts
1158 * during boot. This is the power on reset default so
1159 * usually this should be a noop.
1160 */
1161 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1162 if (dev->msi_cap)
1163 pci_msi_set_enable(dev, 0);
1164
1165 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1166 if (dev->msix_cap)
1167 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1168 }
1169
1170 /**
1171 * pci_setup_device - fill in class and map information of a device
1172 * @dev: the device structure to fill
1173 *
1174 * Initialize the device structure with information about the device's
1175 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1176 * Called at initialisation of the PCI subsystem and by CardBus services.
1177 * Returns 0 on success and negative if unknown type of device (not normal,
1178 * bridge or CardBus).
1179 */
pci_setup_device(struct pci_dev * dev)1180 int pci_setup_device(struct pci_dev *dev)
1181 {
1182 u32 class;
1183 u16 cmd;
1184 u8 hdr_type;
1185 int pos = 0;
1186 struct pci_bus_region region;
1187 struct resource *res;
1188
1189 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1190 return -EIO;
1191
1192 dev->sysdata = dev->bus->sysdata;
1193 dev->dev.parent = dev->bus->bridge;
1194 dev->dev.bus = &pci_bus_type;
1195 dev->hdr_type = hdr_type & 0x7f;
1196 dev->multifunction = !!(hdr_type & 0x80);
1197 dev->error_state = pci_channel_io_normal;
1198 set_pcie_port_type(dev);
1199
1200 pci_dev_assign_slot(dev);
1201 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1202 set this higher, assuming the system even supports it. */
1203 dev->dma_mask = 0xffffffff;
1204
1205 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1206 dev->bus->number, PCI_SLOT(dev->devfn),
1207 PCI_FUNC(dev->devfn));
1208
1209 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1210 dev->revision = class & 0xff;
1211 dev->class = class >> 8; /* upper 3 bytes */
1212
1213 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1214 dev->vendor, dev->device, dev->hdr_type, dev->class);
1215
1216 /* need to have dev->class ready */
1217 dev->cfg_size = pci_cfg_space_size(dev);
1218
1219 /* "Unknown power state" */
1220 dev->current_state = PCI_UNKNOWN;
1221
1222 pci_msi_setup_pci_dev(dev);
1223
1224 /* Early fixups, before probing the BARs */
1225 pci_fixup_device(pci_fixup_early, dev);
1226 /* device class may be changed after fixup */
1227 class = dev->class >> 8;
1228
1229 if (dev->non_compliant_bars && !dev->mmio_always_on) {
1230 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1231 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1232 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1233 cmd &= ~PCI_COMMAND_IO;
1234 cmd &= ~PCI_COMMAND_MEMORY;
1235 pci_write_config_word(dev, PCI_COMMAND, cmd);
1236 }
1237 }
1238
1239 switch (dev->hdr_type) { /* header type */
1240 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1241 if (class == PCI_CLASS_BRIDGE_PCI)
1242 goto bad;
1243 pci_read_irq(dev);
1244 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1245 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1246 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1247
1248 /*
1249 * Do the ugly legacy mode stuff here rather than broken chip
1250 * quirk code. Legacy mode ATA controllers have fixed
1251 * addresses. These are not always echoed in BAR0-3, and
1252 * BAR0-3 in a few cases contain junk!
1253 */
1254 if (class == PCI_CLASS_STORAGE_IDE) {
1255 u8 progif;
1256 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1257 if ((progif & 1) == 0) {
1258 region.start = 0x1F0;
1259 region.end = 0x1F7;
1260 res = &dev->resource[0];
1261 res->flags = LEGACY_IO_RESOURCE;
1262 pcibios_bus_to_resource(dev->bus, res, ®ion);
1263 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1264 res);
1265 region.start = 0x3F6;
1266 region.end = 0x3F6;
1267 res = &dev->resource[1];
1268 res->flags = LEGACY_IO_RESOURCE;
1269 pcibios_bus_to_resource(dev->bus, res, ®ion);
1270 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1271 res);
1272 }
1273 if ((progif & 4) == 0) {
1274 region.start = 0x170;
1275 region.end = 0x177;
1276 res = &dev->resource[2];
1277 res->flags = LEGACY_IO_RESOURCE;
1278 pcibios_bus_to_resource(dev->bus, res, ®ion);
1279 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1280 res);
1281 region.start = 0x376;
1282 region.end = 0x376;
1283 res = &dev->resource[3];
1284 res->flags = LEGACY_IO_RESOURCE;
1285 pcibios_bus_to_resource(dev->bus, res, ®ion);
1286 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1287 res);
1288 }
1289 }
1290 break;
1291
1292 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1293 if (class != PCI_CLASS_BRIDGE_PCI)
1294 goto bad;
1295 /* The PCI-to-PCI bridge spec requires that subtractive
1296 decoding (i.e. transparent) bridge must have programming
1297 interface code of 0x01. */
1298 pci_read_irq(dev);
1299 dev->transparent = ((dev->class & 0xff) == 1);
1300 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1301 set_pcie_hotplug_bridge(dev);
1302 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1303 if (pos) {
1304 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1305 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1306 }
1307 break;
1308
1309 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1310 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1311 goto bad;
1312 pci_read_irq(dev);
1313 pci_read_bases(dev, 1, 0);
1314 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1315 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1316 break;
1317
1318 default: /* unknown header */
1319 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1320 dev->hdr_type);
1321 return -EIO;
1322
1323 bad:
1324 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1325 dev->class, dev->hdr_type);
1326 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1327 }
1328
1329 /* We found a fine healthy device, go go go... */
1330 return 0;
1331 }
1332
pci_configure_mps(struct pci_dev * dev)1333 static void pci_configure_mps(struct pci_dev *dev)
1334 {
1335 struct pci_dev *bridge = pci_upstream_bridge(dev);
1336 int mps, p_mps, rc;
1337
1338 if (!pci_is_pcie(dev))
1339 return;
1340
1341 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1342 if (dev->is_virtfn)
1343 return;
1344
1345 /*
1346 * For Root Complex Integrated Endpoints, program the maximum
1347 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
1348 */
1349 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
1350 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1351 mps = 128;
1352 else
1353 mps = 128 << dev->pcie_mpss;
1354 rc = pcie_set_mps(dev, mps);
1355 if (rc) {
1356 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1357 mps);
1358 }
1359 return;
1360 }
1361
1362 if (!bridge || !pci_is_pcie(bridge))
1363 return;
1364
1365 mps = pcie_get_mps(dev);
1366 p_mps = pcie_get_mps(bridge);
1367
1368 if (mps == p_mps)
1369 return;
1370
1371 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1372 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1373 mps, pci_name(bridge), p_mps);
1374 return;
1375 }
1376
1377 /*
1378 * Fancier MPS configuration is done later by
1379 * pcie_bus_configure_settings()
1380 */
1381 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1382 return;
1383
1384 rc = pcie_set_mps(dev, p_mps);
1385 if (rc) {
1386 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1387 p_mps);
1388 return;
1389 }
1390
1391 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1392 p_mps, mps, 128 << dev->pcie_mpss);
1393 }
1394
1395 static struct hpp_type0 pci_default_type0 = {
1396 .revision = 1,
1397 .cache_line_size = 8,
1398 .latency_timer = 0x40,
1399 .enable_serr = 0,
1400 .enable_perr = 0,
1401 };
1402
program_hpp_type0(struct pci_dev * dev,struct hpp_type0 * hpp)1403 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1404 {
1405 u16 pci_cmd, pci_bctl;
1406
1407 if (!hpp)
1408 hpp = &pci_default_type0;
1409
1410 if (hpp->revision > 1) {
1411 dev_warn(&dev->dev,
1412 "PCI settings rev %d not supported; using defaults\n",
1413 hpp->revision);
1414 hpp = &pci_default_type0;
1415 }
1416
1417 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1418 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1419 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1420 if (hpp->enable_serr)
1421 pci_cmd |= PCI_COMMAND_SERR;
1422 if (hpp->enable_perr)
1423 pci_cmd |= PCI_COMMAND_PARITY;
1424 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1425
1426 /* Program bridge control value */
1427 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1428 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1429 hpp->latency_timer);
1430 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1431 if (hpp->enable_serr)
1432 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1433 if (hpp->enable_perr)
1434 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1435 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1436 }
1437 }
1438
program_hpp_type1(struct pci_dev * dev,struct hpp_type1 * hpp)1439 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1440 {
1441 int pos;
1442
1443 if (!hpp)
1444 return;
1445
1446 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1447 if (!pos)
1448 return;
1449
1450 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1451 }
1452
pcie_root_rcb_set(struct pci_dev * dev)1453 static bool pcie_root_rcb_set(struct pci_dev *dev)
1454 {
1455 struct pci_dev *rp = pcie_find_root_port(dev);
1456 u16 lnkctl;
1457
1458 if (!rp)
1459 return false;
1460
1461 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1462 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1463 return true;
1464
1465 return false;
1466 }
1467
program_hpp_type2(struct pci_dev * dev,struct hpp_type2 * hpp)1468 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1469 {
1470 int pos;
1471 u32 reg32;
1472
1473 if (!hpp)
1474 return;
1475
1476 if (!pci_is_pcie(dev))
1477 return;
1478
1479 if (hpp->revision > 1) {
1480 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1481 hpp->revision);
1482 return;
1483 }
1484
1485 /*
1486 * Don't allow _HPX to change MPS or MRRS settings. We manage
1487 * those to make sure they're consistent with the rest of the
1488 * platform.
1489 */
1490 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1491 PCI_EXP_DEVCTL_READRQ;
1492 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1493 PCI_EXP_DEVCTL_READRQ);
1494
1495 /* Initialize Device Control Register */
1496 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1497 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1498
1499 /* Initialize Link Control Register */
1500 if (pcie_cap_has_lnkctl(dev)) {
1501
1502 /*
1503 * If the Root Port supports Read Completion Boundary of
1504 * 128, set RCB to 128. Otherwise, clear it.
1505 */
1506 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1507 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1508 if (pcie_root_rcb_set(dev))
1509 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1510
1511 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1512 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1513 }
1514
1515 /* Find Advanced Error Reporting Enhanced Capability */
1516 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1517 if (!pos)
1518 return;
1519
1520 /* Initialize Uncorrectable Error Mask Register */
1521 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1522 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1523 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1524
1525 /* Initialize Uncorrectable Error Severity Register */
1526 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1527 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1528 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1529
1530 /* Initialize Correctable Error Mask Register */
1531 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1532 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1533 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1534
1535 /* Initialize Advanced Error Capabilities and Control Register */
1536 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1537 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1538 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1539
1540 /*
1541 * FIXME: The following two registers are not supported yet.
1542 *
1543 * o Secondary Uncorrectable Error Severity Register
1544 * o Secondary Uncorrectable Error Mask Register
1545 */
1546 }
1547
pci_configure_device(struct pci_dev * dev)1548 static void pci_configure_device(struct pci_dev *dev)
1549 {
1550 struct hotplug_params hpp;
1551 int ret;
1552
1553 pci_configure_mps(dev);
1554
1555 memset(&hpp, 0, sizeof(hpp));
1556 ret = pci_get_hp_params(dev, &hpp);
1557 if (ret)
1558 return;
1559
1560 program_hpp_type2(dev, hpp.t2);
1561 program_hpp_type1(dev, hpp.t1);
1562 program_hpp_type0(dev, hpp.t0);
1563 }
1564
pci_release_capabilities(struct pci_dev * dev)1565 static void pci_release_capabilities(struct pci_dev *dev)
1566 {
1567 pci_vpd_release(dev);
1568 pci_iov_release(dev);
1569 pci_free_cap_save_buffers(dev);
1570 }
1571
1572 /**
1573 * pci_release_dev - free a pci device structure when all users of it are finished.
1574 * @dev: device that's been disconnected
1575 *
1576 * Will be called only by the device core when all users of this pci device are
1577 * done.
1578 */
pci_release_dev(struct device * dev)1579 static void pci_release_dev(struct device *dev)
1580 {
1581 struct pci_dev *pci_dev;
1582
1583 pci_dev = to_pci_dev(dev);
1584 pci_release_capabilities(pci_dev);
1585 pci_release_of_node(pci_dev);
1586 pcibios_release_device(pci_dev);
1587 pci_bus_put(pci_dev->bus);
1588 kfree(pci_dev->driver_override);
1589 kfree(pci_dev);
1590 }
1591
pci_alloc_dev(struct pci_bus * bus)1592 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1593 {
1594 struct pci_dev *dev;
1595
1596 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1597 if (!dev)
1598 return NULL;
1599
1600 INIT_LIST_HEAD(&dev->bus_list);
1601 dev->dev.type = &pci_dev_type;
1602 dev->bus = pci_bus_get(bus);
1603
1604 return dev;
1605 }
1606 EXPORT_SYMBOL(pci_alloc_dev);
1607
pci_bus_read_dev_vendor_id(struct pci_bus * bus,int devfn,u32 * l,int crs_timeout)1608 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1609 int crs_timeout)
1610 {
1611 int delay = 1;
1612
1613 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1614 return false;
1615
1616 /* some broken boards return 0 or ~0 if a slot is empty: */
1617 if (*l == 0xffffffff || *l == 0x00000000 ||
1618 *l == 0x0000ffff || *l == 0xffff0000)
1619 return false;
1620
1621 /*
1622 * Configuration Request Retry Status. Some root ports return the
1623 * actual device ID instead of the synthetic ID (0xFFFF) required
1624 * by the PCIe spec. Ignore the device ID and only check for
1625 * (vendor id == 1).
1626 */
1627 while ((*l & 0xffff) == 0x0001) {
1628 if (!crs_timeout)
1629 return false;
1630
1631 msleep(delay);
1632 delay *= 2;
1633 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1634 return false;
1635 /* Card hasn't responded in 60 seconds? Must be stuck. */
1636 if (delay > crs_timeout) {
1637 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1638 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1639 PCI_FUNC(devfn));
1640 return false;
1641 }
1642 }
1643
1644 return true;
1645 }
1646 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1647
1648 /*
1649 * Read the config data for a PCI device, sanity-check it
1650 * and fill in the dev structure...
1651 */
pci_scan_device(struct pci_bus * bus,int devfn)1652 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1653 {
1654 struct pci_dev *dev;
1655 u32 l;
1656
1657 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1658 return NULL;
1659
1660 dev = pci_alloc_dev(bus);
1661 if (!dev)
1662 return NULL;
1663
1664 dev->devfn = devfn;
1665 dev->vendor = l & 0xffff;
1666 dev->device = (l >> 16) & 0xffff;
1667
1668 pci_set_of_node(dev);
1669
1670 if (pci_setup_device(dev)) {
1671 pci_release_of_node(dev);
1672 pci_bus_put(dev->bus);
1673 kfree(dev);
1674 return NULL;
1675 }
1676
1677 return dev;
1678 }
1679
pci_init_capabilities(struct pci_dev * dev)1680 static void pci_init_capabilities(struct pci_dev *dev)
1681 {
1682 /* Enhanced Allocation */
1683 pci_ea_init(dev);
1684
1685 /* MSI/MSI-X list */
1686 pci_msi_init_pci_dev(dev);
1687
1688 /* Buffers for saving PCIe and PCI-X capabilities */
1689 pci_allocate_cap_save_buffers(dev);
1690
1691 /* Power Management */
1692 pci_pm_init(dev);
1693
1694 /* Vital Product Data */
1695 pci_vpd_pci22_init(dev);
1696
1697 /* Alternative Routing-ID Forwarding */
1698 pci_configure_ari(dev);
1699
1700 /* Single Root I/O Virtualization */
1701 pci_iov_init(dev);
1702
1703 /* Address Translation Services */
1704 pci_ats_init(dev);
1705
1706 /* Enable ACS P2P upstream forwarding */
1707 pci_enable_acs(dev);
1708
1709 pci_cleanup_aer_error_status_regs(dev);
1710 }
1711
1712 /*
1713 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1714 * devices. Firmware interfaces that can select the MSI domain on a
1715 * per-device basis should be called from here.
1716 */
pci_dev_msi_domain(struct pci_dev * dev)1717 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1718 {
1719 struct irq_domain *d;
1720
1721 /*
1722 * If a domain has been set through the pcibios_add_device
1723 * callback, then this is the one (platform code knows best).
1724 */
1725 d = dev_get_msi_domain(&dev->dev);
1726 if (d)
1727 return d;
1728
1729 /*
1730 * Let's see if we have a firmware interface able to provide
1731 * the domain.
1732 */
1733 d = pci_msi_get_device_domain(dev);
1734 if (d)
1735 return d;
1736
1737 return NULL;
1738 }
1739
pci_set_msi_domain(struct pci_dev * dev)1740 static void pci_set_msi_domain(struct pci_dev *dev)
1741 {
1742 struct irq_domain *d;
1743
1744 /*
1745 * If the platform or firmware interfaces cannot supply a
1746 * device-specific MSI domain, then inherit the default domain
1747 * from the host bridge itself.
1748 */
1749 d = pci_dev_msi_domain(dev);
1750 if (!d)
1751 d = dev_get_msi_domain(&dev->bus->dev);
1752
1753 dev_set_msi_domain(&dev->dev, d);
1754 }
1755
1756 /**
1757 * pci_dma_configure - Setup DMA configuration
1758 * @dev: ptr to pci_dev struct of the PCI device
1759 *
1760 * Function to update PCI devices's DMA configuration using the same
1761 * info from the OF node or ACPI node of host bridge's parent (if any).
1762 */
pci_dma_configure(struct pci_dev * dev)1763 static void pci_dma_configure(struct pci_dev *dev)
1764 {
1765 struct device *bridge = pci_get_host_bridge_device(dev);
1766
1767 if (IS_ENABLED(CONFIG_OF) &&
1768 bridge->parent && bridge->parent->of_node) {
1769 of_dma_configure(&dev->dev, bridge->parent->of_node);
1770 } else if (has_acpi_companion(bridge)) {
1771 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1772 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1773
1774 if (attr == DEV_DMA_NOT_SUPPORTED)
1775 dev_warn(&dev->dev, "DMA not supported.\n");
1776 else
1777 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1778 attr == DEV_DMA_COHERENT);
1779 }
1780
1781 pci_put_host_bridge_device(bridge);
1782 }
1783
pci_device_add(struct pci_dev * dev,struct pci_bus * bus)1784 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1785 {
1786 int ret;
1787
1788 pci_configure_device(dev);
1789
1790 device_initialize(&dev->dev);
1791 dev->dev.release = pci_release_dev;
1792
1793 set_dev_node(&dev->dev, pcibus_to_node(bus));
1794 dev->dev.dma_mask = &dev->dma_mask;
1795 dev->dev.dma_parms = &dev->dma_parms;
1796 dev->dev.coherent_dma_mask = 0xffffffffull;
1797 pci_dma_configure(dev);
1798
1799 pci_set_dma_max_seg_size(dev, 65536);
1800 pci_set_dma_seg_boundary(dev, 0xffffffff);
1801
1802 /* Fix up broken headers */
1803 pci_fixup_device(pci_fixup_header, dev);
1804
1805 /* moved out from quirk header fixup code */
1806 pci_reassigndev_resource_alignment(dev);
1807
1808 /* Clear the state_saved flag. */
1809 dev->state_saved = false;
1810
1811 /* Initialize various capabilities */
1812 pci_init_capabilities(dev);
1813
1814 /*
1815 * Add the device to our list of discovered devices
1816 * and the bus list for fixup functions, etc.
1817 */
1818 down_write(&pci_bus_sem);
1819 list_add_tail(&dev->bus_list, &bus->devices);
1820 up_write(&pci_bus_sem);
1821
1822 ret = pcibios_add_device(dev);
1823 WARN_ON(ret < 0);
1824
1825 /* Setup MSI irq domain */
1826 pci_set_msi_domain(dev);
1827
1828 /* Notifier could use PCI capabilities */
1829 dev->match_driver = false;
1830 ret = device_add(&dev->dev);
1831 WARN_ON(ret < 0);
1832 }
1833
pci_scan_single_device(struct pci_bus * bus,int devfn)1834 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1835 {
1836 struct pci_dev *dev;
1837
1838 dev = pci_get_slot(bus, devfn);
1839 if (dev) {
1840 pci_dev_put(dev);
1841 return dev;
1842 }
1843
1844 dev = pci_scan_device(bus, devfn);
1845 if (!dev)
1846 return NULL;
1847
1848 pci_device_add(dev, bus);
1849
1850 return dev;
1851 }
1852 EXPORT_SYMBOL(pci_scan_single_device);
1853
next_fn(struct pci_bus * bus,struct pci_dev * dev,unsigned fn)1854 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1855 {
1856 int pos;
1857 u16 cap = 0;
1858 unsigned next_fn;
1859
1860 if (pci_ari_enabled(bus)) {
1861 if (!dev)
1862 return 0;
1863 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1864 if (!pos)
1865 return 0;
1866
1867 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1868 next_fn = PCI_ARI_CAP_NFN(cap);
1869 if (next_fn <= fn)
1870 return 0; /* protect against malformed list */
1871
1872 return next_fn;
1873 }
1874
1875 /* dev may be NULL for non-contiguous multifunction devices */
1876 if (!dev || dev->multifunction)
1877 return (fn + 1) % 8;
1878
1879 return 0;
1880 }
1881
only_one_child(struct pci_bus * bus)1882 static int only_one_child(struct pci_bus *bus)
1883 {
1884 struct pci_dev *parent = bus->self;
1885
1886 if (!parent || !pci_is_pcie(parent))
1887 return 0;
1888 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1889 return 1;
1890 if (parent->has_secondary_link &&
1891 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1892 return 1;
1893 return 0;
1894 }
1895
1896 /**
1897 * pci_scan_slot - scan a PCI slot on a bus for devices.
1898 * @bus: PCI bus to scan
1899 * @devfn: slot number to scan (must have zero function.)
1900 *
1901 * Scan a PCI slot on the specified PCI bus for devices, adding
1902 * discovered devices to the @bus->devices list. New devices
1903 * will not have is_added set.
1904 *
1905 * Returns the number of new devices found.
1906 */
pci_scan_slot(struct pci_bus * bus,int devfn)1907 int pci_scan_slot(struct pci_bus *bus, int devfn)
1908 {
1909 unsigned fn, nr = 0;
1910 struct pci_dev *dev;
1911
1912 if (only_one_child(bus) && (devfn > 0))
1913 return 0; /* Already scanned the entire slot */
1914
1915 dev = pci_scan_single_device(bus, devfn);
1916 if (!dev)
1917 return 0;
1918 if (!dev->is_added)
1919 nr++;
1920
1921 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1922 dev = pci_scan_single_device(bus, devfn + fn);
1923 if (dev) {
1924 if (!dev->is_added)
1925 nr++;
1926 dev->multifunction = 1;
1927 }
1928 }
1929
1930 /* only one slot has pcie device */
1931 if (bus->self && nr)
1932 pcie_aspm_init_link_state(bus->self);
1933
1934 return nr;
1935 }
1936 EXPORT_SYMBOL(pci_scan_slot);
1937
pcie_find_smpss(struct pci_dev * dev,void * data)1938 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1939 {
1940 u8 *smpss = data;
1941
1942 if (!pci_is_pcie(dev))
1943 return 0;
1944
1945 /*
1946 * We don't have a way to change MPS settings on devices that have
1947 * drivers attached. A hot-added device might support only the minimum
1948 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1949 * where devices may be hot-added, we limit the fabric MPS to 128 so
1950 * hot-added devices will work correctly.
1951 *
1952 * However, if we hot-add a device to a slot directly below a Root
1953 * Port, it's impossible for there to be other existing devices below
1954 * the port. We don't limit the MPS in this case because we can
1955 * reconfigure MPS on both the Root Port and the hot-added device,
1956 * and there are no other devices involved.
1957 *
1958 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1959 */
1960 if (dev->is_hotplug_bridge &&
1961 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1962 *smpss = 0;
1963
1964 if (*smpss > dev->pcie_mpss)
1965 *smpss = dev->pcie_mpss;
1966
1967 return 0;
1968 }
1969
pcie_write_mps(struct pci_dev * dev,int mps)1970 static void pcie_write_mps(struct pci_dev *dev, int mps)
1971 {
1972 int rc;
1973
1974 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1975 mps = 128 << dev->pcie_mpss;
1976
1977 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1978 dev->bus->self)
1979 /* For "Performance", the assumption is made that
1980 * downstream communication will never be larger than
1981 * the MRRS. So, the MPS only needs to be configured
1982 * for the upstream communication. This being the case,
1983 * walk from the top down and set the MPS of the child
1984 * to that of the parent bus.
1985 *
1986 * Configure the device MPS with the smaller of the
1987 * device MPSS or the bridge MPS (which is assumed to be
1988 * properly configured at this point to the largest
1989 * allowable MPS based on its parent bus).
1990 */
1991 mps = min(mps, pcie_get_mps(dev->bus->self));
1992 }
1993
1994 rc = pcie_set_mps(dev, mps);
1995 if (rc)
1996 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1997 }
1998
pcie_write_mrrs(struct pci_dev * dev)1999 static void pcie_write_mrrs(struct pci_dev *dev)
2000 {
2001 int rc, mrrs;
2002
2003 /* In the "safe" case, do not configure the MRRS. There appear to be
2004 * issues with setting MRRS to 0 on a number of devices.
2005 */
2006 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2007 return;
2008
2009 /* For Max performance, the MRRS must be set to the largest supported
2010 * value. However, it cannot be configured larger than the MPS the
2011 * device or the bus can support. This should already be properly
2012 * configured by a prior call to pcie_write_mps.
2013 */
2014 mrrs = pcie_get_mps(dev);
2015
2016 /* MRRS is a R/W register. Invalid values can be written, but a
2017 * subsequent read will verify if the value is acceptable or not.
2018 * If the MRRS value provided is not acceptable (e.g., too large),
2019 * shrink the value until it is acceptable to the HW.
2020 */
2021 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2022 rc = pcie_set_readrq(dev, mrrs);
2023 if (!rc)
2024 break;
2025
2026 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
2027 mrrs /= 2;
2028 }
2029
2030 if (mrrs < 128)
2031 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2032 }
2033
pcie_bus_configure_set(struct pci_dev * dev,void * data)2034 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2035 {
2036 int mps, orig_mps;
2037
2038 if (!pci_is_pcie(dev))
2039 return 0;
2040
2041 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2042 pcie_bus_config == PCIE_BUS_DEFAULT)
2043 return 0;
2044
2045 mps = 128 << *(u8 *)data;
2046 orig_mps = pcie_get_mps(dev);
2047
2048 pcie_write_mps(dev, mps);
2049 pcie_write_mrrs(dev);
2050
2051 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2052 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2053 orig_mps, pcie_get_readrq(dev));
2054
2055 return 0;
2056 }
2057
2058 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2059 * parents then children fashion. If this changes, then this code will not
2060 * work as designed.
2061 */
pcie_bus_configure_settings(struct pci_bus * bus)2062 void pcie_bus_configure_settings(struct pci_bus *bus)
2063 {
2064 u8 smpss = 0;
2065
2066 if (!bus->self)
2067 return;
2068
2069 if (!pci_is_pcie(bus->self))
2070 return;
2071
2072 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2073 * to be aware of the MPS of the destination. To work around this,
2074 * simply force the MPS of the entire system to the smallest possible.
2075 */
2076 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2077 smpss = 0;
2078
2079 if (pcie_bus_config == PCIE_BUS_SAFE) {
2080 smpss = bus->self->pcie_mpss;
2081
2082 pcie_find_smpss(bus->self, &smpss);
2083 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2084 }
2085
2086 pcie_bus_configure_set(bus->self, &smpss);
2087 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2088 }
2089 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2090
pci_scan_child_bus(struct pci_bus * bus)2091 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2092 {
2093 unsigned int devfn, pass, max = bus->busn_res.start;
2094 struct pci_dev *dev;
2095
2096 dev_dbg(&bus->dev, "scanning bus\n");
2097
2098 /* Go find them, Rover! */
2099 for (devfn = 0; devfn < 0x100; devfn += 8)
2100 pci_scan_slot(bus, devfn);
2101
2102 /* Reserve buses for SR-IOV capability. */
2103 max += pci_iov_bus_range(bus);
2104
2105 /*
2106 * After performing arch-dependent fixup of the bus, look behind
2107 * all PCI-to-PCI bridges on this bus.
2108 */
2109 if (!bus->is_added) {
2110 dev_dbg(&bus->dev, "fixups for bus\n");
2111 pcibios_fixup_bus(bus);
2112 bus->is_added = 1;
2113 }
2114
2115 for (pass = 0; pass < 2; pass++)
2116 list_for_each_entry(dev, &bus->devices, bus_list) {
2117 if (pci_is_bridge(dev))
2118 max = pci_scan_bridge(bus, dev, max, pass);
2119 }
2120
2121 /*
2122 * We've scanned the bus and so we know all about what's on
2123 * the other side of any bridges that may be on this bus plus
2124 * any devices.
2125 *
2126 * Return how far we've got finding sub-buses.
2127 */
2128 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2129 return max;
2130 }
2131 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2132
2133 /**
2134 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2135 * @bridge: Host bridge to set up.
2136 *
2137 * Default empty implementation. Replace with an architecture-specific setup
2138 * routine, if necessary.
2139 */
pcibios_root_bridge_prepare(struct pci_host_bridge * bridge)2140 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2141 {
2142 return 0;
2143 }
2144
pcibios_add_bus(struct pci_bus * bus)2145 void __weak pcibios_add_bus(struct pci_bus *bus)
2146 {
2147 }
2148
pcibios_remove_bus(struct pci_bus * bus)2149 void __weak pcibios_remove_bus(struct pci_bus *bus)
2150 {
2151 }
2152
pci_create_root_bus(struct device * parent,int bus,struct pci_ops * ops,void * sysdata,struct list_head * resources)2153 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2154 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2155 {
2156 int error;
2157 struct pci_host_bridge *bridge;
2158 struct pci_bus *b, *b2;
2159 struct resource_entry *window, *n;
2160 struct resource *res;
2161 resource_size_t offset;
2162 char bus_addr[64];
2163 char *fmt;
2164
2165 b = pci_alloc_bus(NULL);
2166 if (!b)
2167 return NULL;
2168
2169 b->sysdata = sysdata;
2170 b->ops = ops;
2171 b->number = b->busn_res.start = bus;
2172 pci_bus_assign_domain_nr(b, parent);
2173 b2 = pci_find_bus(pci_domain_nr(b), bus);
2174 if (b2) {
2175 /* If we already got to this bus through a different bridge, ignore it */
2176 dev_dbg(&b2->dev, "bus already known\n");
2177 goto err_out;
2178 }
2179
2180 bridge = pci_alloc_host_bridge(b);
2181 if (!bridge)
2182 goto err_out;
2183
2184 bridge->dev.parent = parent;
2185 bridge->dev.release = pci_release_host_bridge_dev;
2186 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2187 error = pcibios_root_bridge_prepare(bridge);
2188 if (error) {
2189 kfree(bridge);
2190 goto err_out;
2191 }
2192
2193 error = device_register(&bridge->dev);
2194 if (error) {
2195 put_device(&bridge->dev);
2196 goto err_out;
2197 }
2198 b->bridge = get_device(&bridge->dev);
2199 device_enable_async_suspend(b->bridge);
2200 pci_set_bus_of_node(b);
2201 pci_set_bus_msi_domain(b);
2202
2203 if (!parent)
2204 set_dev_node(b->bridge, pcibus_to_node(b));
2205
2206 b->dev.class = &pcibus_class;
2207 b->dev.parent = b->bridge;
2208 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2209 error = device_register(&b->dev);
2210 if (error)
2211 goto class_dev_reg_err;
2212
2213 pcibios_add_bus(b);
2214
2215 /* Create legacy_io and legacy_mem files for this bus */
2216 pci_create_legacy_files(b);
2217
2218 if (parent)
2219 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2220 else
2221 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2222
2223 /* Add initial resources to the bus */
2224 resource_list_for_each_entry_safe(window, n, resources) {
2225 list_move_tail(&window->node, &bridge->windows);
2226 res = window->res;
2227 offset = window->offset;
2228 if (res->flags & IORESOURCE_BUS)
2229 pci_bus_insert_busn_res(b, bus, res->end);
2230 else
2231 pci_bus_add_resource(b, res, 0);
2232 if (offset) {
2233 if (resource_type(res) == IORESOURCE_IO)
2234 fmt = " (bus address [%#06llx-%#06llx])";
2235 else
2236 fmt = " (bus address [%#010llx-%#010llx])";
2237 snprintf(bus_addr, sizeof(bus_addr), fmt,
2238 (unsigned long long) (res->start - offset),
2239 (unsigned long long) (res->end - offset));
2240 } else
2241 bus_addr[0] = '\0';
2242 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2243 }
2244
2245 down_write(&pci_bus_sem);
2246 list_add_tail(&b->node, &pci_root_buses);
2247 up_write(&pci_bus_sem);
2248
2249 return b;
2250
2251 class_dev_reg_err:
2252 put_device(&bridge->dev);
2253 device_unregister(&bridge->dev);
2254 err_out:
2255 kfree(b);
2256 return NULL;
2257 }
2258 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2259
pci_bus_insert_busn_res(struct pci_bus * b,int bus,int bus_max)2260 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2261 {
2262 struct resource *res = &b->busn_res;
2263 struct resource *parent_res, *conflict;
2264
2265 res->start = bus;
2266 res->end = bus_max;
2267 res->flags = IORESOURCE_BUS;
2268
2269 if (!pci_is_root_bus(b))
2270 parent_res = &b->parent->busn_res;
2271 else {
2272 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2273 res->flags |= IORESOURCE_PCI_FIXED;
2274 }
2275
2276 conflict = request_resource_conflict(parent_res, res);
2277
2278 if (conflict)
2279 dev_printk(KERN_DEBUG, &b->dev,
2280 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2281 res, pci_is_root_bus(b) ? "domain " : "",
2282 parent_res, conflict->name, conflict);
2283
2284 return conflict == NULL;
2285 }
2286
pci_bus_update_busn_res_end(struct pci_bus * b,int bus_max)2287 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2288 {
2289 struct resource *res = &b->busn_res;
2290 struct resource old_res = *res;
2291 resource_size_t size;
2292 int ret;
2293
2294 if (res->start > bus_max)
2295 return -EINVAL;
2296
2297 size = bus_max - res->start + 1;
2298 ret = adjust_resource(res, res->start, size);
2299 dev_printk(KERN_DEBUG, &b->dev,
2300 "busn_res: %pR end %s updated to %02x\n",
2301 &old_res, ret ? "can not be" : "is", bus_max);
2302
2303 if (!ret && !res->parent)
2304 pci_bus_insert_busn_res(b, res->start, res->end);
2305
2306 return ret;
2307 }
2308
pci_bus_release_busn_res(struct pci_bus * b)2309 void pci_bus_release_busn_res(struct pci_bus *b)
2310 {
2311 struct resource *res = &b->busn_res;
2312 int ret;
2313
2314 if (!res->flags || !res->parent)
2315 return;
2316
2317 ret = release_resource(res);
2318 dev_printk(KERN_DEBUG, &b->dev,
2319 "busn_res: %pR %s released\n",
2320 res, ret ? "can not be" : "is");
2321 }
2322
pci_scan_root_bus_msi(struct device * parent,int bus,struct pci_ops * ops,void * sysdata,struct list_head * resources,struct msi_controller * msi)2323 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2324 struct pci_ops *ops, void *sysdata,
2325 struct list_head *resources, struct msi_controller *msi)
2326 {
2327 struct resource_entry *window;
2328 bool found = false;
2329 struct pci_bus *b;
2330 int max;
2331
2332 resource_list_for_each_entry(window, resources)
2333 if (window->res->flags & IORESOURCE_BUS) {
2334 found = true;
2335 break;
2336 }
2337
2338 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2339 if (!b)
2340 return NULL;
2341
2342 b->msi = msi;
2343
2344 if (!found) {
2345 dev_info(&b->dev,
2346 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2347 bus);
2348 pci_bus_insert_busn_res(b, bus, 255);
2349 }
2350
2351 max = pci_scan_child_bus(b);
2352
2353 if (!found)
2354 pci_bus_update_busn_res_end(b, max);
2355
2356 return b;
2357 }
2358
pci_scan_root_bus(struct device * parent,int bus,struct pci_ops * ops,void * sysdata,struct list_head * resources)2359 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2360 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2361 {
2362 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2363 NULL);
2364 }
2365 EXPORT_SYMBOL(pci_scan_root_bus);
2366
pci_scan_bus(int bus,struct pci_ops * ops,void * sysdata)2367 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2368 void *sysdata)
2369 {
2370 LIST_HEAD(resources);
2371 struct pci_bus *b;
2372
2373 pci_add_resource(&resources, &ioport_resource);
2374 pci_add_resource(&resources, &iomem_resource);
2375 pci_add_resource(&resources, &busn_resource);
2376 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2377 if (b) {
2378 pci_scan_child_bus(b);
2379 } else {
2380 pci_free_resource_list(&resources);
2381 }
2382 return b;
2383 }
2384 EXPORT_SYMBOL(pci_scan_bus);
2385
2386 /**
2387 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2388 * @bridge: PCI bridge for the bus to scan
2389 *
2390 * Scan a PCI bus and child buses for new devices, add them,
2391 * and enable them, resizing bridge mmio/io resource if necessary
2392 * and possible. The caller must ensure the child devices are already
2393 * removed for resizing to occur.
2394 *
2395 * Returns the max number of subordinate bus discovered.
2396 */
pci_rescan_bus_bridge_resize(struct pci_dev * bridge)2397 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2398 {
2399 unsigned int max;
2400 struct pci_bus *bus = bridge->subordinate;
2401
2402 max = pci_scan_child_bus(bus);
2403
2404 pci_assign_unassigned_bridge_resources(bridge);
2405
2406 pci_bus_add_devices(bus);
2407
2408 return max;
2409 }
2410
2411 /**
2412 * pci_rescan_bus - scan a PCI bus for devices.
2413 * @bus: PCI bus to scan
2414 *
2415 * Scan a PCI bus and child buses for new devices, adds them,
2416 * and enables them.
2417 *
2418 * Returns the max number of subordinate bus discovered.
2419 */
pci_rescan_bus(struct pci_bus * bus)2420 unsigned int pci_rescan_bus(struct pci_bus *bus)
2421 {
2422 unsigned int max;
2423
2424 max = pci_scan_child_bus(bus);
2425 pci_assign_unassigned_bus_resources(bus);
2426 pci_bus_add_devices(bus);
2427
2428 return max;
2429 }
2430 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2431
2432 /*
2433 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2434 * routines should always be executed under this mutex.
2435 */
2436 static DEFINE_MUTEX(pci_rescan_remove_lock);
2437
pci_lock_rescan_remove(void)2438 void pci_lock_rescan_remove(void)
2439 {
2440 mutex_lock(&pci_rescan_remove_lock);
2441 }
2442 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2443
pci_unlock_rescan_remove(void)2444 void pci_unlock_rescan_remove(void)
2445 {
2446 mutex_unlock(&pci_rescan_remove_lock);
2447 }
2448 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2449
pci_sort_bf_cmp(const struct device * d_a,const struct device * d_b)2450 static int __init pci_sort_bf_cmp(const struct device *d_a,
2451 const struct device *d_b)
2452 {
2453 const struct pci_dev *a = to_pci_dev(d_a);
2454 const struct pci_dev *b = to_pci_dev(d_b);
2455
2456 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2457 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2458
2459 if (a->bus->number < b->bus->number) return -1;
2460 else if (a->bus->number > b->bus->number) return 1;
2461
2462 if (a->devfn < b->devfn) return -1;
2463 else if (a->devfn > b->devfn) return 1;
2464
2465 return 0;
2466 }
2467
pci_sort_breadthfirst(void)2468 void __init pci_sort_breadthfirst(void)
2469 {
2470 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2471 }
2472