1 /* 2 * Copyright (C) 2001 by Hiroyuki Kondo 3 */ 4 5 #if !defined(CONFIG_M32R_CFC_NUM) 6 #define M32R_MAX_PCC 2 7 #else 8 #define M32R_MAX_PCC CONFIG_M32R_CFC_NUM 9 #endif 10 11 /* 12 * M32R PC Card Controller 13 */ 14 #define M32R_PCC0_BASE 0x00ef7000 15 #define M32R_PCC1_BASE 0x00ef7020 16 17 /* 18 * Register offsets 19 */ 20 #define PCCR 0x00 21 #define PCADR 0x04 22 #define PCMOD 0x08 23 #define PCIRC 0x0c 24 #define PCCSIGCR 0x10 25 #define PCATCR 0x14 26 27 /* 28 * PCCR 29 */ 30 #define PCCR_PCEN (1UL<<(31-31)) 31 32 /* 33 * PCIRC 34 */ 35 #define PCIRC_BWERR (1UL<<(31-7)) 36 #define PCIRC_CDIN1 (1UL<<(31-14)) 37 #define PCIRC_CDIN2 (1UL<<(31-15)) 38 #define PCIRC_BEIEN (1UL<<(31-23)) 39 #define PCIRC_CIIEN (1UL<<(31-30)) 40 #define PCIRC_COIEN (1UL<<(31-31)) 41 42 /* 43 * PCCSIGCR 44 */ 45 #define PCCSIGCR_SEN (1UL<<(31-3)) 46 #define PCCSIGCR_VEN (1UL<<(31-7)) 47 #define PCCSIGCR_CRST (1UL<<(31-15)) 48 #define PCCSIGCR_COCR (1UL<<(31-31)) 49 50 /* 51 * 52 */ 53 #define PCMOD_AS_ATTRIB (1UL<<(31-19)) 54 #define PCMOD_AS_IO (1UL<<(31-18)) 55 56 #define PCMOD_CBSZ (1UL<<(31-23)) /* set for 8bit */ 57 58 #define PCMOD_DBEX (1UL<<(31-31)) /* set for excahnge */ 59 60 /* 61 * M32R PCC Map addr 62 */ 63 64 #define M32R_PCC0_MAPBASE 0x14000000 65 #define M32R_PCC1_MAPBASE 0x16000000 66 67 #define M32R_PCC_MAPMAX 0x02000000 68 69 #define M32R_PCC_MAPSIZE 0x00001000 /* XXX */ 70 #define M32R_PCC_MAPMASK (~(M32R_PCC_MAPMAX-1)) 71 72 #define CFC_IOPORT_BASE 0x1000 73 74 #if defined(CONFIG_PLAT_MAPPI3) 75 #define CFC_ATTR_MAPBASE 0x14014000 76 #define CFC_IO_MAPBASE_BYTE 0xb4012000 77 #define CFC_IO_MAPBASE_WORD 0xb4002000 78 #elif !defined(CONFIG_PLAT_USRV) 79 #define CFC_ATTR_MAPBASE 0x0c014000 80 #define CFC_IO_MAPBASE_BYTE 0xac012000 81 #define CFC_IO_MAPBASE_WORD 0xac002000 82 #else 83 #define CFC_ATTR_MAPBASE 0x04014000 84 #define CFC_IO_MAPBASE_BYTE 0xa4012000 85 #define CFC_IO_MAPBASE_WORD 0xa4002000 86 #endif /* CONFIG_PLAT_USRV */ 87 88