1 /*
2 * SuperH Pin Function Controller support.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12 #define DRV_NAME "sh-pfc"
13
14 #include <linux/bitops.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/io.h>
18 #include <linux/ioport.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26
27 #include "core.h"
28
sh_pfc_map_resources(struct sh_pfc * pfc,struct platform_device * pdev)29 static int sh_pfc_map_resources(struct sh_pfc *pfc,
30 struct platform_device *pdev)
31 {
32 unsigned int num_windows, num_irqs;
33 struct sh_pfc_window *windows;
34 unsigned int *irqs = NULL;
35 struct resource *res;
36 unsigned int i;
37 int irq;
38
39 /* Count the MEM and IRQ resources. */
40 for (num_windows = 0;; num_windows++) {
41 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
42 if (!res)
43 break;
44 }
45 for (num_irqs = 0;; num_irqs++) {
46 irq = platform_get_irq(pdev, num_irqs);
47 if (irq == -EPROBE_DEFER)
48 return irq;
49 if (irq < 0)
50 break;
51 }
52
53 if (num_windows == 0)
54 return -EINVAL;
55
56 /* Allocate memory windows and IRQs arrays. */
57 windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
58 GFP_KERNEL);
59 if (windows == NULL)
60 return -ENOMEM;
61
62 pfc->num_windows = num_windows;
63 pfc->windows = windows;
64
65 if (num_irqs) {
66 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
67 GFP_KERNEL);
68 if (irqs == NULL)
69 return -ENOMEM;
70
71 pfc->num_irqs = num_irqs;
72 pfc->irqs = irqs;
73 }
74
75 /* Fill them. */
76 for (i = 0; i < num_windows; i++) {
77 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
78 windows->phys = res->start;
79 windows->size = resource_size(res);
80 windows->virt = devm_ioremap_resource(pfc->dev, res);
81 if (IS_ERR(windows->virt))
82 return -ENOMEM;
83 windows++;
84 }
85 for (i = 0; i < num_irqs; i++)
86 *irqs++ = platform_get_irq(pdev, i);
87
88 return 0;
89 }
90
sh_pfc_phys_to_virt(struct sh_pfc * pfc,u32 reg)91 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
92 {
93 struct sh_pfc_window *window;
94 phys_addr_t address = reg;
95 unsigned int i;
96
97 /* scan through physical windows and convert address */
98 for (i = 0; i < pfc->num_windows; i++) {
99 window = pfc->windows + i;
100
101 if (address < window->phys)
102 continue;
103
104 if (address >= (window->phys + window->size))
105 continue;
106
107 return window->virt + (address - window->phys);
108 }
109
110 BUG();
111 return NULL;
112 }
113
sh_pfc_get_pin_index(struct sh_pfc * pfc,unsigned int pin)114 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
115 {
116 unsigned int offset;
117 unsigned int i;
118
119 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
120 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
121
122 if (pin <= range->end)
123 return pin >= range->start
124 ? offset + pin - range->start : -1;
125
126 offset += range->end - range->start + 1;
127 }
128
129 return -EINVAL;
130 }
131
sh_pfc_enum_in_range(u16 enum_id,const struct pinmux_range * r)132 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
133 {
134 if (enum_id < r->begin)
135 return 0;
136
137 if (enum_id > r->end)
138 return 0;
139
140 return 1;
141 }
142
sh_pfc_read_raw_reg(void __iomem * mapped_reg,unsigned int reg_width)143 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
144 {
145 switch (reg_width) {
146 case 8:
147 return ioread8(mapped_reg);
148 case 16:
149 return ioread16(mapped_reg);
150 case 32:
151 return ioread32(mapped_reg);
152 }
153
154 BUG();
155 return 0;
156 }
157
sh_pfc_write_raw_reg(void __iomem * mapped_reg,unsigned int reg_width,u32 data)158 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
159 u32 data)
160 {
161 switch (reg_width) {
162 case 8:
163 iowrite8(data, mapped_reg);
164 return;
165 case 16:
166 iowrite16(data, mapped_reg);
167 return;
168 case 32:
169 iowrite32(data, mapped_reg);
170 return;
171 }
172
173 BUG();
174 }
175
sh_pfc_config_reg_helper(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int in_pos,void __iomem ** mapped_regp,u32 * maskp,unsigned int * posp)176 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
177 const struct pinmux_cfg_reg *crp,
178 unsigned int in_pos,
179 void __iomem **mapped_regp, u32 *maskp,
180 unsigned int *posp)
181 {
182 unsigned int k;
183
184 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
185
186 if (crp->field_width) {
187 *maskp = (1 << crp->field_width) - 1;
188 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
189 } else {
190 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
191 *posp = crp->reg_width;
192 for (k = 0; k <= in_pos; k++)
193 *posp -= crp->var_field_width[k];
194 }
195 }
196
sh_pfc_write_config_reg(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int field,u32 value)197 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
198 const struct pinmux_cfg_reg *crp,
199 unsigned int field, u32 value)
200 {
201 void __iomem *mapped_reg;
202 unsigned int pos;
203 u32 mask, data;
204
205 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
206
207 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
208 "r_width = %u, f_width = %u\n",
209 crp->reg, value, field, crp->reg_width, crp->field_width);
210
211 mask = ~(mask << pos);
212 value = value << pos;
213
214 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
215 data &= mask;
216 data |= value;
217
218 if (pfc->info->unlock_reg)
219 sh_pfc_write_raw_reg(
220 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
221 ~data);
222
223 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
224 }
225
sh_pfc_get_config_reg(struct sh_pfc * pfc,u16 enum_id,const struct pinmux_cfg_reg ** crp,unsigned int * fieldp,u32 * valuep)226 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
227 const struct pinmux_cfg_reg **crp,
228 unsigned int *fieldp, u32 *valuep)
229 {
230 unsigned int k = 0;
231
232 while (1) {
233 const struct pinmux_cfg_reg *config_reg =
234 pfc->info->cfg_regs + k;
235 unsigned int r_width = config_reg->reg_width;
236 unsigned int f_width = config_reg->field_width;
237 unsigned int curr_width;
238 unsigned int bit_pos;
239 unsigned int pos = 0;
240 unsigned int m = 0;
241
242 if (!r_width)
243 break;
244
245 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
246 u32 ncomb;
247 u32 n;
248
249 if (f_width)
250 curr_width = f_width;
251 else
252 curr_width = config_reg->var_field_width[m];
253
254 ncomb = 1 << curr_width;
255 for (n = 0; n < ncomb; n++) {
256 if (config_reg->enum_ids[pos + n] == enum_id) {
257 *crp = config_reg;
258 *fieldp = m;
259 *valuep = n;
260 return 0;
261 }
262 }
263 pos += ncomb;
264 m++;
265 }
266 k++;
267 }
268
269 return -EINVAL;
270 }
271
sh_pfc_mark_to_enum(struct sh_pfc * pfc,u16 mark,int pos,u16 * enum_idp)272 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
273 u16 *enum_idp)
274 {
275 const u16 *data = pfc->info->pinmux_data;
276 unsigned int k;
277
278 if (pos) {
279 *enum_idp = data[pos + 1];
280 return pos + 1;
281 }
282
283 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
284 if (data[k] == mark) {
285 *enum_idp = data[k + 1];
286 return k + 1;
287 }
288 }
289
290 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
291 mark);
292 return -EINVAL;
293 }
294
sh_pfc_config_mux(struct sh_pfc * pfc,unsigned mark,int pinmux_type)295 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
296 {
297 const struct pinmux_range *range;
298 int pos = 0;
299
300 switch (pinmux_type) {
301 case PINMUX_TYPE_GPIO:
302 case PINMUX_TYPE_FUNCTION:
303 range = NULL;
304 break;
305
306 case PINMUX_TYPE_OUTPUT:
307 range = &pfc->info->output;
308 break;
309
310 case PINMUX_TYPE_INPUT:
311 range = &pfc->info->input;
312 break;
313
314 default:
315 return -EINVAL;
316 }
317
318 /* Iterate over all the configuration fields we need to update. */
319 while (1) {
320 const struct pinmux_cfg_reg *cr;
321 unsigned int field;
322 u16 enum_id;
323 u32 value;
324 int in_range;
325 int ret;
326
327 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
328 if (pos < 0)
329 return pos;
330
331 if (!enum_id)
332 break;
333
334 /* Check if the configuration field selects a function. If it
335 * doesn't, skip the field if it's not applicable to the
336 * requested pinmux type.
337 */
338 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
339 if (!in_range) {
340 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
341 /* Functions are allowed to modify all
342 * fields.
343 */
344 in_range = 1;
345 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
346 /* Input/output types can only modify fields
347 * that correspond to their respective ranges.
348 */
349 in_range = sh_pfc_enum_in_range(enum_id, range);
350
351 /*
352 * special case pass through for fixed
353 * input-only or output-only pins without
354 * function enum register association.
355 */
356 if (in_range && enum_id == range->force)
357 continue;
358 }
359 /* GPIOs are only allowed to modify function fields. */
360 }
361
362 if (!in_range)
363 continue;
364
365 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
366 if (ret < 0)
367 return ret;
368
369 sh_pfc_write_config_reg(pfc, cr, field, value);
370 }
371
372 return 0;
373 }
374
sh_pfc_init_ranges(struct sh_pfc * pfc)375 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
376 {
377 struct sh_pfc_pin_range *range;
378 unsigned int nr_ranges;
379 unsigned int i;
380
381 if (pfc->info->pins[0].pin == (u16)-1) {
382 /* Pin number -1 denotes that the SoC doesn't report pin numbers
383 * in its pin arrays yet. Consider the pin numbers range as
384 * continuous and allocate a single range.
385 */
386 pfc->nr_ranges = 1;
387 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
388 GFP_KERNEL);
389 if (pfc->ranges == NULL)
390 return -ENOMEM;
391
392 pfc->ranges->start = 0;
393 pfc->ranges->end = pfc->info->nr_pins - 1;
394 pfc->nr_gpio_pins = pfc->info->nr_pins;
395
396 return 0;
397 }
398
399 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
400 * be sorted by pin numbers, and pins without a GPIO port must come
401 * last.
402 */
403 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
404 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
405 nr_ranges++;
406 }
407
408 pfc->nr_ranges = nr_ranges;
409 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
410 GFP_KERNEL);
411 if (pfc->ranges == NULL)
412 return -ENOMEM;
413
414 range = pfc->ranges;
415 range->start = pfc->info->pins[0].pin;
416
417 for (i = 1; i < pfc->info->nr_pins; ++i) {
418 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
419 continue;
420
421 range->end = pfc->info->pins[i-1].pin;
422 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
423 pfc->nr_gpio_pins = range->end + 1;
424
425 range++;
426 range->start = pfc->info->pins[i].pin;
427 }
428
429 range->end = pfc->info->pins[i-1].pin;
430 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
431 pfc->nr_gpio_pins = range->end + 1;
432
433 return 0;
434 }
435
436 #ifdef CONFIG_OF
437 static const struct of_device_id sh_pfc_of_table[] = {
438 #ifdef CONFIG_PINCTRL_PFC_EMEV2
439 {
440 .compatible = "renesas,pfc-emev2",
441 .data = &emev2_pinmux_info,
442 },
443 #endif
444 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
445 {
446 .compatible = "renesas,pfc-r8a73a4",
447 .data = &r8a73a4_pinmux_info,
448 },
449 #endif
450 #ifdef CONFIG_PINCTRL_PFC_R8A7740
451 {
452 .compatible = "renesas,pfc-r8a7740",
453 .data = &r8a7740_pinmux_info,
454 },
455 #endif
456 #ifdef CONFIG_PINCTRL_PFC_R8A7778
457 {
458 .compatible = "renesas,pfc-r8a7778",
459 .data = &r8a7778_pinmux_info,
460 },
461 #endif
462 #ifdef CONFIG_PINCTRL_PFC_R8A7779
463 {
464 .compatible = "renesas,pfc-r8a7779",
465 .data = &r8a7779_pinmux_info,
466 },
467 #endif
468 #ifdef CONFIG_PINCTRL_PFC_R8A7790
469 {
470 .compatible = "renesas,pfc-r8a7790",
471 .data = &r8a7790_pinmux_info,
472 },
473 #endif
474 #ifdef CONFIG_PINCTRL_PFC_R8A7791
475 {
476 .compatible = "renesas,pfc-r8a7791",
477 .data = &r8a7791_pinmux_info,
478 },
479 #endif
480 #ifdef CONFIG_PINCTRL_PFC_R8A7793
481 {
482 .compatible = "renesas,pfc-r8a7793",
483 .data = &r8a7793_pinmux_info,
484 },
485 #endif
486 #ifdef CONFIG_PINCTRL_PFC_R8A7794
487 {
488 .compatible = "renesas,pfc-r8a7794",
489 .data = &r8a7794_pinmux_info,
490 },
491 #endif
492 #ifdef CONFIG_PINCTRL_PFC_R8A7795
493 {
494 .compatible = "renesas,pfc-r8a7795",
495 .data = &r8a7795_pinmux_info,
496 },
497 #endif
498 #ifdef CONFIG_PINCTRL_PFC_SH73A0
499 {
500 .compatible = "renesas,pfc-sh73a0",
501 .data = &sh73a0_pinmux_info,
502 },
503 #endif
504 { },
505 };
506 MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
507 #endif
508
sh_pfc_probe(struct platform_device * pdev)509 static int sh_pfc_probe(struct platform_device *pdev)
510 {
511 const struct platform_device_id *platid = platform_get_device_id(pdev);
512 #ifdef CONFIG_OF
513 struct device_node *np = pdev->dev.of_node;
514 #endif
515 const struct sh_pfc_soc_info *info;
516 struct sh_pfc *pfc;
517 int ret;
518
519 #ifdef CONFIG_OF
520 if (np)
521 info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
522 else
523 #endif
524 info = platid ? (const void *)platid->driver_data : NULL;
525
526 if (info == NULL)
527 return -ENODEV;
528
529 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
530 if (pfc == NULL)
531 return -ENOMEM;
532
533 pfc->info = info;
534 pfc->dev = &pdev->dev;
535
536 ret = sh_pfc_map_resources(pfc, pdev);
537 if (unlikely(ret < 0))
538 return ret;
539
540 spin_lock_init(&pfc->lock);
541
542 if (info->ops && info->ops->init) {
543 ret = info->ops->init(pfc);
544 if (ret < 0)
545 return ret;
546
547 /* .init() may have overridden pfc->info */
548 info = pfc->info;
549 }
550
551 /* Enable dummy states for those platforms without pinctrl support */
552 if (!of_have_populated_dt())
553 pinctrl_provide_dummies();
554
555 ret = sh_pfc_init_ranges(pfc);
556 if (ret < 0)
557 return ret;
558
559 /*
560 * Initialize pinctrl bindings first
561 */
562 ret = sh_pfc_register_pinctrl(pfc);
563 if (unlikely(ret != 0))
564 return ret;
565
566 #ifdef CONFIG_GPIO_SH_PFC
567 /*
568 * Then the GPIO chip
569 */
570 ret = sh_pfc_register_gpiochip(pfc);
571 if (unlikely(ret != 0)) {
572 /*
573 * If the GPIO chip fails to come up we still leave the
574 * PFC state as it is, given that there are already
575 * extant users of it that have succeeded by this point.
576 */
577 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
578 }
579 #endif
580
581 platform_set_drvdata(pdev, pfc);
582
583 dev_info(pfc->dev, "%s support registered\n", info->name);
584
585 return 0;
586 }
587
sh_pfc_remove(struct platform_device * pdev)588 static int sh_pfc_remove(struct platform_device *pdev)
589 {
590 struct sh_pfc *pfc = platform_get_drvdata(pdev);
591
592 #ifdef CONFIG_GPIO_SH_PFC
593 sh_pfc_unregister_gpiochip(pfc);
594 #endif
595 sh_pfc_unregister_pinctrl(pfc);
596
597 return 0;
598 }
599
600 static const struct platform_device_id sh_pfc_id_table[] = {
601 #ifdef CONFIG_PINCTRL_PFC_SH7203
602 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
603 #endif
604 #ifdef CONFIG_PINCTRL_PFC_SH7264
605 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
606 #endif
607 #ifdef CONFIG_PINCTRL_PFC_SH7269
608 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
609 #endif
610 #ifdef CONFIG_PINCTRL_PFC_SH7720
611 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
612 #endif
613 #ifdef CONFIG_PINCTRL_PFC_SH7722
614 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
615 #endif
616 #ifdef CONFIG_PINCTRL_PFC_SH7723
617 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
618 #endif
619 #ifdef CONFIG_PINCTRL_PFC_SH7724
620 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
621 #endif
622 #ifdef CONFIG_PINCTRL_PFC_SH7734
623 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
624 #endif
625 #ifdef CONFIG_PINCTRL_PFC_SH7757
626 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
627 #endif
628 #ifdef CONFIG_PINCTRL_PFC_SH7785
629 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
630 #endif
631 #ifdef CONFIG_PINCTRL_PFC_SH7786
632 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
633 #endif
634 #ifdef CONFIG_PINCTRL_PFC_SHX3
635 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
636 #endif
637 { "sh-pfc", 0 },
638 { },
639 };
640 MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
641
642 static struct platform_driver sh_pfc_driver = {
643 .probe = sh_pfc_probe,
644 .remove = sh_pfc_remove,
645 .id_table = sh_pfc_id_table,
646 .driver = {
647 .name = DRV_NAME,
648 .of_match_table = of_match_ptr(sh_pfc_of_table),
649 },
650 };
651
sh_pfc_init(void)652 static int __init sh_pfc_init(void)
653 {
654 return platform_driver_register(&sh_pfc_driver);
655 }
656 postcore_initcall(sh_pfc_init);
657
sh_pfc_exit(void)658 static void __exit sh_pfc_exit(void)
659 {
660 platform_driver_unregister(&sh_pfc_driver);
661 }
662 module_exit(sh_pfc_exit);
663
664 MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
665 MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
666 MODULE_LICENSE("GPL v2");
667