1 /*
2 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/err.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/regulator/of_regulator.h>
25 #include <linux/platform_device.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/pfuze100.h>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/regmap.h>
32
33 #define PFUZE_NUMREGS 128
34 #define PFUZE100_VOL_OFFSET 0
35 #define PFUZE100_STANDBY_OFFSET 1
36 #define PFUZE100_MODE_OFFSET 3
37 #define PFUZE100_CONF_OFFSET 4
38
39 #define PFUZE100_DEVICEID 0x0
40 #define PFUZE100_REVID 0x3
41 #define PFUZE100_FABID 0x4
42
43 #define PFUZE100_SW1ABVOL 0x20
44 #define PFUZE100_SW1CVOL 0x2e
45 #define PFUZE100_SW2VOL 0x35
46 #define PFUZE100_SW3AVOL 0x3c
47 #define PFUZE100_SW3BVOL 0x43
48 #define PFUZE100_SW4VOL 0x4a
49 #define PFUZE100_SWBSTCON1 0x66
50 #define PFUZE100_VREFDDRCON 0x6a
51 #define PFUZE100_VSNVSVOL 0x6b
52 #define PFUZE100_VGEN1VOL 0x6c
53 #define PFUZE100_VGEN2VOL 0x6d
54 #define PFUZE100_VGEN3VOL 0x6e
55 #define PFUZE100_VGEN4VOL 0x6f
56 #define PFUZE100_VGEN5VOL 0x70
57 #define PFUZE100_VGEN6VOL 0x71
58
59 enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3 };
60
61 struct pfuze_regulator {
62 struct regulator_desc desc;
63 unsigned char stby_reg;
64 unsigned char stby_mask;
65 };
66
67 struct pfuze_chip {
68 int chip_id;
69 struct regmap *regmap;
70 struct device *dev;
71 struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
72 struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
73 };
74
75 static const int pfuze100_swbst[] = {
76 5000000, 5050000, 5100000, 5150000,
77 };
78
79 static const int pfuze100_vsnvs[] = {
80 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
81 };
82
83 static const int pfuze3000_sw2lo[] = {
84 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
85 };
86
87 static const int pfuze3000_sw2hi[] = {
88 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
89 };
90
91 static const struct i2c_device_id pfuze_device_id[] = {
92 {.name = "pfuze100", .driver_data = PFUZE100},
93 {.name = "pfuze200", .driver_data = PFUZE200},
94 {.name = "pfuze3000", .driver_data = PFUZE3000},
95 { }
96 };
97 MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
98
99 static const struct of_device_id pfuze_dt_ids[] = {
100 { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
101 { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
102 { .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
103 { }
104 };
105 MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
106
pfuze100_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)107 static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
108 {
109 struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
110 int id = rdev_get_id(rdev);
111 unsigned int ramp_bits;
112 int ret;
113
114 if (id < PFUZE100_SWBST) {
115 ramp_delay = 12500 / ramp_delay;
116 ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
117 ret = regmap_update_bits(pfuze100->regmap,
118 rdev->desc->vsel_reg + 4,
119 0xc0, ramp_bits << 6);
120 if (ret < 0)
121 dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
122 } else
123 ret = -EACCES;
124
125 return ret;
126 }
127
128 static struct regulator_ops pfuze100_ldo_regulator_ops = {
129 .enable = regulator_enable_regmap,
130 .disable = regulator_disable_regmap,
131 .is_enabled = regulator_is_enabled_regmap,
132 .list_voltage = regulator_list_voltage_linear,
133 .set_voltage_sel = regulator_set_voltage_sel_regmap,
134 .get_voltage_sel = regulator_get_voltage_sel_regmap,
135 };
136
137 static struct regulator_ops pfuze100_fixed_regulator_ops = {
138 .enable = regulator_enable_regmap,
139 .disable = regulator_disable_regmap,
140 .is_enabled = regulator_is_enabled_regmap,
141 .list_voltage = regulator_list_voltage_linear,
142 };
143
144 static struct regulator_ops pfuze100_sw_regulator_ops = {
145 .list_voltage = regulator_list_voltage_linear,
146 .set_voltage_sel = regulator_set_voltage_sel_regmap,
147 .get_voltage_sel = regulator_get_voltage_sel_regmap,
148 .set_voltage_time_sel = regulator_set_voltage_time_sel,
149 .set_ramp_delay = pfuze100_set_ramp_delay,
150 };
151
152 static struct regulator_ops pfuze100_swb_regulator_ops = {
153 .enable = regulator_enable_regmap,
154 .disable = regulator_disable_regmap,
155 .is_enabled = regulator_is_enabled_regmap,
156 .list_voltage = regulator_list_voltage_table,
157 .map_voltage = regulator_map_voltage_ascend,
158 .set_voltage_sel = regulator_set_voltage_sel_regmap,
159 .get_voltage_sel = regulator_get_voltage_sel_regmap,
160
161 };
162
163 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
164 [_chip ## _ ## _name] = { \
165 .desc = { \
166 .name = #_name, \
167 .n_voltages = 1, \
168 .ops = &pfuze100_fixed_regulator_ops, \
169 .type = REGULATOR_VOLTAGE, \
170 .id = _chip ## _ ## _name, \
171 .owner = THIS_MODULE, \
172 .min_uV = (voltage), \
173 .enable_reg = (base), \
174 .enable_mask = 0x10, \
175 }, \
176 }
177
178 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
179 [_chip ## _ ## _name] = { \
180 .desc = { \
181 .name = #_name,\
182 .n_voltages = ((max) - (min)) / (step) + 1, \
183 .ops = &pfuze100_sw_regulator_ops, \
184 .type = REGULATOR_VOLTAGE, \
185 .id = _chip ## _ ## _name, \
186 .owner = THIS_MODULE, \
187 .min_uV = (min), \
188 .uV_step = (step), \
189 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
190 .vsel_mask = 0x3f, \
191 }, \
192 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
193 .stby_mask = 0x3f, \
194 }
195
196 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
197 [_chip ## _ ## _name] = { \
198 .desc = { \
199 .name = #_name, \
200 .n_voltages = ARRAY_SIZE(voltages), \
201 .ops = &pfuze100_swb_regulator_ops, \
202 .type = REGULATOR_VOLTAGE, \
203 .id = _chip ## _ ## _name, \
204 .owner = THIS_MODULE, \
205 .volt_table = voltages, \
206 .vsel_reg = (base), \
207 .vsel_mask = (mask), \
208 .enable_reg = (base), \
209 .enable_mask = 0x48, \
210 }, \
211 }
212
213 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
214 [_chip ## _ ## _name] = { \
215 .desc = { \
216 .name = #_name, \
217 .n_voltages = ((max) - (min)) / (step) + 1, \
218 .ops = &pfuze100_ldo_regulator_ops, \
219 .type = REGULATOR_VOLTAGE, \
220 .id = _chip ## _ ## _name, \
221 .owner = THIS_MODULE, \
222 .min_uV = (min), \
223 .uV_step = (step), \
224 .vsel_reg = (base), \
225 .vsel_mask = 0xf, \
226 .enable_reg = (base), \
227 .enable_mask = 0x10, \
228 }, \
229 .stby_reg = (base), \
230 .stby_mask = 0x20, \
231 }
232
233 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \
234 .desc = { \
235 .name = #_name, \
236 .n_voltages = ((max) - (min)) / (step) + 1, \
237 .ops = &pfuze100_ldo_regulator_ops, \
238 .type = REGULATOR_VOLTAGE, \
239 .id = _chip ## _ ## _name, \
240 .owner = THIS_MODULE, \
241 .min_uV = (min), \
242 .uV_step = (step), \
243 .vsel_reg = (base), \
244 .vsel_mask = 0x3, \
245 .enable_reg = (base), \
246 .enable_mask = 0x10, \
247 }, \
248 .stby_reg = (base), \
249 .stby_mask = 0x20, \
250 }
251
252
253 #define PFUZE3000_SW2_REG(_chip, _name, base, min, max, step) { \
254 .desc = { \
255 .name = #_name,\
256 .n_voltages = ((max) - (min)) / (step) + 1, \
257 .ops = &pfuze100_sw_regulator_ops, \
258 .type = REGULATOR_VOLTAGE, \
259 .id = _chip ## _ ## _name, \
260 .owner = THIS_MODULE, \
261 .min_uV = (min), \
262 .uV_step = (step), \
263 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
264 .vsel_mask = 0x7, \
265 }, \
266 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
267 .stby_mask = 0x7, \
268 }
269
270 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \
271 .desc = { \
272 .name = #_name,\
273 .n_voltages = ((max) - (min)) / (step) + 1, \
274 .ops = &pfuze100_sw_regulator_ops, \
275 .type = REGULATOR_VOLTAGE, \
276 .id = _chip ## _ ## _name, \
277 .owner = THIS_MODULE, \
278 .min_uV = (min), \
279 .uV_step = (step), \
280 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
281 .vsel_mask = 0xf, \
282 }, \
283 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
284 .stby_mask = 0xf, \
285 }
286
287 /* PFUZE100 */
288 static struct pfuze_regulator pfuze100_regulators[] = {
289 PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
290 PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
291 PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
292 PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
293 PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
294 PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
295 PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
296 PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
297 PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
298 PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
299 PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
300 PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
301 PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
302 PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
303 PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
304 };
305
306 static struct pfuze_regulator pfuze200_regulators[] = {
307 PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
308 PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
309 PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
310 PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
311 PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
312 PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
313 PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
314 PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
315 PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
316 PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
317 PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
318 PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
319 PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
320 };
321
322 static struct pfuze_regulator pfuze3000_regulators[] = {
323 PFUZE100_SW_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 700000, 1475000, 25000),
324 PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
325 PFUZE100_SWB_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
326 PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
327 PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
328 PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
329 PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
330 PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
331 PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
332 PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
333 PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
334 PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
335 PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
336 };
337
338 static struct pfuze_regulator *pfuze_regulators;
339
340 #ifdef CONFIG_OF
341 /* PFUZE100 */
342 static struct of_regulator_match pfuze100_matches[] = {
343 { .name = "sw1ab", },
344 { .name = "sw1c", },
345 { .name = "sw2", },
346 { .name = "sw3a", },
347 { .name = "sw3b", },
348 { .name = "sw4", },
349 { .name = "swbst", },
350 { .name = "vsnvs", },
351 { .name = "vrefddr", },
352 { .name = "vgen1", },
353 { .name = "vgen2", },
354 { .name = "vgen3", },
355 { .name = "vgen4", },
356 { .name = "vgen5", },
357 { .name = "vgen6", },
358 };
359
360 /* PFUZE200 */
361 static struct of_regulator_match pfuze200_matches[] = {
362
363 { .name = "sw1ab", },
364 { .name = "sw2", },
365 { .name = "sw3a", },
366 { .name = "sw3b", },
367 { .name = "swbst", },
368 { .name = "vsnvs", },
369 { .name = "vrefddr", },
370 { .name = "vgen1", },
371 { .name = "vgen2", },
372 { .name = "vgen3", },
373 { .name = "vgen4", },
374 { .name = "vgen5", },
375 { .name = "vgen6", },
376 };
377
378 /* PFUZE3000 */
379 static struct of_regulator_match pfuze3000_matches[] = {
380
381 { .name = "sw1a", },
382 { .name = "sw1b", },
383 { .name = "sw2", },
384 { .name = "sw3", },
385 { .name = "swbst", },
386 { .name = "vsnvs", },
387 { .name = "vrefddr", },
388 { .name = "vldo1", },
389 { .name = "vldo2", },
390 { .name = "vccsd", },
391 { .name = "v33", },
392 { .name = "vldo3", },
393 { .name = "vldo4", },
394 };
395
396 static struct of_regulator_match *pfuze_matches;
397
pfuze_parse_regulators_dt(struct pfuze_chip * chip)398 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
399 {
400 struct device *dev = chip->dev;
401 struct device_node *np, *parent;
402 int ret;
403
404 np = of_node_get(dev->of_node);
405 if (!np)
406 return -EINVAL;
407
408 parent = of_get_child_by_name(np, "regulators");
409 if (!parent) {
410 dev_err(dev, "regulators node not found\n");
411 return -EINVAL;
412 }
413
414 switch (chip->chip_id) {
415 case PFUZE3000:
416 pfuze_matches = pfuze3000_matches;
417 ret = of_regulator_match(dev, parent, pfuze3000_matches,
418 ARRAY_SIZE(pfuze3000_matches));
419 break;
420 case PFUZE200:
421 pfuze_matches = pfuze200_matches;
422 ret = of_regulator_match(dev, parent, pfuze200_matches,
423 ARRAY_SIZE(pfuze200_matches));
424 break;
425
426 case PFUZE100:
427 default:
428 pfuze_matches = pfuze100_matches;
429 ret = of_regulator_match(dev, parent, pfuze100_matches,
430 ARRAY_SIZE(pfuze100_matches));
431 break;
432 }
433
434 of_node_put(parent);
435 if (ret < 0) {
436 dev_err(dev, "Error parsing regulator init data: %d\n",
437 ret);
438 return ret;
439 }
440
441 return 0;
442 }
443
match_init_data(int index)444 static inline struct regulator_init_data *match_init_data(int index)
445 {
446 return pfuze_matches[index].init_data;
447 }
448
match_of_node(int index)449 static inline struct device_node *match_of_node(int index)
450 {
451 return pfuze_matches[index].of_node;
452 }
453 #else
pfuze_parse_regulators_dt(struct pfuze_chip * chip)454 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
455 {
456 return 0;
457 }
458
match_init_data(int index)459 static inline struct regulator_init_data *match_init_data(int index)
460 {
461 return NULL;
462 }
463
match_of_node(int index)464 static inline struct device_node *match_of_node(int index)
465 {
466 return NULL;
467 }
468 #endif
469
pfuze_identify(struct pfuze_chip * pfuze_chip)470 static int pfuze_identify(struct pfuze_chip *pfuze_chip)
471 {
472 unsigned int value;
473 int ret;
474
475 ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
476 if (ret)
477 return ret;
478
479 if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
480 /*
481 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
482 * as ID=8 in PFUZE100
483 */
484 dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
485 } else if ((value & 0x0f) != pfuze_chip->chip_id &&
486 (value & 0xf0) >> 4 != pfuze_chip->chip_id) {
487 /* device id NOT match with your setting */
488 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
489 return -ENODEV;
490 }
491
492 ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
493 if (ret)
494 return ret;
495 dev_info(pfuze_chip->dev,
496 "Full layer: %x, Metal layer: %x\n",
497 (value & 0xf0) >> 4, value & 0x0f);
498
499 ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
500 if (ret)
501 return ret;
502 dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
503 (value & 0xc) >> 2, value & 0x3);
504
505 return 0;
506 }
507
508 static const struct regmap_config pfuze_regmap_config = {
509 .reg_bits = 8,
510 .val_bits = 8,
511 .max_register = PFUZE_NUMREGS - 1,
512 .cache_type = REGCACHE_RBTREE,
513 };
514
pfuze100_regulator_probe(struct i2c_client * client,const struct i2c_device_id * id)515 static int pfuze100_regulator_probe(struct i2c_client *client,
516 const struct i2c_device_id *id)
517 {
518 struct pfuze_chip *pfuze_chip;
519 struct pfuze_regulator_platform_data *pdata =
520 dev_get_platdata(&client->dev);
521 struct regulator_config config = { };
522 int i, ret;
523 const struct of_device_id *match;
524 u32 regulator_num;
525 u32 sw_check_start, sw_check_end, sw_hi = 0x40;
526
527 pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
528 GFP_KERNEL);
529 if (!pfuze_chip)
530 return -ENOMEM;
531
532 if (client->dev.of_node) {
533 match = of_match_device(of_match_ptr(pfuze_dt_ids),
534 &client->dev);
535 if (!match) {
536 dev_err(&client->dev, "Error: No device match found\n");
537 return -ENODEV;
538 }
539 pfuze_chip->chip_id = (int)(long)match->data;
540 } else if (id) {
541 pfuze_chip->chip_id = id->driver_data;
542 } else {
543 dev_err(&client->dev, "No dts match or id table match found\n");
544 return -ENODEV;
545 }
546
547 i2c_set_clientdata(client, pfuze_chip);
548 pfuze_chip->dev = &client->dev;
549
550 pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
551 if (IS_ERR(pfuze_chip->regmap)) {
552 ret = PTR_ERR(pfuze_chip->regmap);
553 dev_err(&client->dev,
554 "regmap allocation failed with err %d\n", ret);
555 return ret;
556 }
557
558 ret = pfuze_identify(pfuze_chip);
559 if (ret) {
560 dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
561 return ret;
562 }
563
564 /* use the right regulators after identify the right device */
565 switch (pfuze_chip->chip_id) {
566 case PFUZE3000:
567 pfuze_regulators = pfuze3000_regulators;
568 regulator_num = ARRAY_SIZE(pfuze3000_regulators);
569 sw_check_start = PFUZE3000_SW2;
570 sw_check_end = PFUZE3000_SW2;
571 sw_hi = 1 << 3;
572 break;
573 case PFUZE200:
574 pfuze_regulators = pfuze200_regulators;
575 regulator_num = ARRAY_SIZE(pfuze200_regulators);
576 sw_check_start = PFUZE200_SW2;
577 sw_check_end = PFUZE200_SW3B;
578 break;
579 case PFUZE100:
580 default:
581 pfuze_regulators = pfuze100_regulators;
582 regulator_num = ARRAY_SIZE(pfuze100_regulators);
583 sw_check_start = PFUZE100_SW2;
584 sw_check_end = PFUZE100_SW4;
585 break;
586 }
587 dev_info(&client->dev, "pfuze%s found.\n",
588 (pfuze_chip->chip_id == PFUZE100) ? "100" :
589 ((pfuze_chip->chip_id == PFUZE200) ? "200" : "3000"));
590
591 memcpy(pfuze_chip->regulator_descs, pfuze_regulators,
592 sizeof(pfuze_chip->regulator_descs));
593
594 ret = pfuze_parse_regulators_dt(pfuze_chip);
595 if (ret)
596 return ret;
597
598 for (i = 0; i < regulator_num; i++) {
599 struct regulator_init_data *init_data;
600 struct regulator_desc *desc;
601 int val;
602
603 desc = &pfuze_chip->regulator_descs[i].desc;
604
605 if (pdata)
606 init_data = pdata->init_data[i];
607 else
608 init_data = match_init_data(i);
609
610 /* SW2~SW4 high bit check and modify the voltage value table */
611 if (i >= sw_check_start && i <= sw_check_end) {
612 ret = regmap_read(pfuze_chip->regmap,
613 desc->vsel_reg, &val);
614 if (ret) {
615 dev_err(&client->dev, "Fails to read from the register.\n");
616 return ret;
617 }
618
619 if (val & sw_hi) {
620 if (pfuze_chip->chip_id == PFUZE3000) {
621 desc->volt_table = pfuze3000_sw2hi;
622 desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
623 } else {
624 desc->min_uV = 800000;
625 desc->uV_step = 50000;
626 desc->n_voltages = 51;
627 }
628 }
629 }
630
631 config.dev = &client->dev;
632 config.init_data = init_data;
633 config.driver_data = pfuze_chip;
634 config.of_node = match_of_node(i);
635 config.ena_gpio = -EINVAL;
636
637 pfuze_chip->regulators[i] =
638 devm_regulator_register(&client->dev, desc, &config);
639 if (IS_ERR(pfuze_chip->regulators[i])) {
640 dev_err(&client->dev, "register regulator%s failed\n",
641 pfuze_regulators[i].desc.name);
642 return PTR_ERR(pfuze_chip->regulators[i]);
643 }
644 }
645
646 return 0;
647 }
648
649 static struct i2c_driver pfuze_driver = {
650 .id_table = pfuze_device_id,
651 .driver = {
652 .name = "pfuze100-regulator",
653 .of_match_table = pfuze_dt_ids,
654 },
655 .probe = pfuze100_regulator_probe,
656 };
657 module_i2c_driver(pfuze_driver);
658
659 MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
660 MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/PFUZE200 PMIC");
661 MODULE_LICENSE("GPL v2");
662