1 /*
2 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
3 * bus adaptor found on Power Macintosh computers.
4 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
5 * controller.
6 *
7 * Paul Mackerras, August 1996.
8 * Copyright (C) 1996 Paul Mackerras.
9 *
10 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
11 * Add delay after initial bus reset
12 * Add module parameters
13 *
14 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
15 * issues
16 * To do:
17 * - handle aborts correctly
18 * - retry arbitration if lost (unless higher levels do this for us)
19 * - power down the chip when no device is detected
20 */
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/types.h>
25 #include <linux/string.h>
26 #include <linux/blkdev.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/interrupt.h>
30 #include <linux/reboot.h>
31 #include <linux/spinlock.h>
32 #include <asm/dbdma.h>
33 #include <asm/io.h>
34 #include <asm/pgtable.h>
35 #include <asm/prom.h>
36 #include <asm/irq.h>
37 #include <asm/hydra.h>
38 #include <asm/processor.h>
39 #include <asm/machdep.h>
40 #include <asm/pmac_feature.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/macio.h>
43
44 #include <scsi/scsi.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <scsi/scsi_device.h>
47 #include <scsi/scsi_host.h>
48
49 #include "mesh.h"
50
51 #if 1
52 #undef KERN_DEBUG
53 #define KERN_DEBUG KERN_WARNING
54 #endif
55
56 MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)");
57 MODULE_DESCRIPTION("PowerMac MESH SCSI driver");
58 MODULE_LICENSE("GPL");
59
60 static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE;
61 static int sync_targets = 0xff;
62 static int resel_targets = 0xff;
63 static int debug_targets = 0; /* print debug for these targets */
64 static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS;
65
66 module_param(sync_rate, int, 0);
67 MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)");
68 module_param(sync_targets, int, 0);
69 MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous");
70 module_param(resel_targets, int, 0);
71 MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect");
72 module_param(debug_targets, int, 0644);
73 MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets");
74 module_param(init_reset_delay, int, 0);
75 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
76
77 static int mesh_sync_period = 100;
78 static int mesh_sync_offset = 0;
79 static unsigned char use_active_neg = 0; /* bit mask for SEQ_ACTIVE_NEG if used */
80
81 #define ALLOW_SYNC(tgt) ((sync_targets >> (tgt)) & 1)
82 #define ALLOW_RESEL(tgt) ((resel_targets >> (tgt)) & 1)
83 #define ALLOW_DEBUG(tgt) ((debug_targets >> (tgt)) & 1)
84 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->device->id))
85
86 #undef MESH_DBG
87 #define N_DBG_LOG 50
88 #define N_DBG_SLOG 20
89 #define NUM_DBG_EVENTS 13
90 #undef DBG_USE_TB /* bombs on 601 */
91
92 struct dbglog {
93 char *fmt;
94 u32 tb;
95 u8 phase;
96 u8 bs0;
97 u8 bs1;
98 u8 tgt;
99 int d;
100 };
101
102 enum mesh_phase {
103 idle,
104 arbitrating,
105 selecting,
106 commanding,
107 dataing,
108 statusing,
109 busfreeing,
110 disconnecting,
111 reselecting,
112 sleeping
113 };
114
115 enum msg_phase {
116 msg_none,
117 msg_out,
118 msg_out_xxx,
119 msg_out_last,
120 msg_in,
121 msg_in_bad,
122 };
123
124 enum sdtr_phase {
125 do_sdtr,
126 sdtr_sent,
127 sdtr_done
128 };
129
130 struct mesh_target {
131 enum sdtr_phase sdtr_state;
132 int sync_params;
133 int data_goes_out; /* guess as to data direction */
134 struct scsi_cmnd *current_req;
135 u32 saved_ptr;
136 #ifdef MESH_DBG
137 int log_ix;
138 int n_log;
139 struct dbglog log[N_DBG_LOG];
140 #endif
141 };
142
143 struct mesh_state {
144 volatile struct mesh_regs __iomem *mesh;
145 int meshintr;
146 volatile struct dbdma_regs __iomem *dma;
147 int dmaintr;
148 struct Scsi_Host *host;
149 struct mesh_state *next;
150 struct scsi_cmnd *request_q;
151 struct scsi_cmnd *request_qtail;
152 enum mesh_phase phase; /* what we're currently trying to do */
153 enum msg_phase msgphase;
154 int conn_tgt; /* target we're connected to */
155 struct scsi_cmnd *current_req; /* req we're currently working on */
156 int data_ptr;
157 int dma_started;
158 int dma_count;
159 int stat;
160 int aborting;
161 int expect_reply;
162 int n_msgin;
163 u8 msgin[16];
164 int n_msgout;
165 int last_n_msgout;
166 u8 msgout[16];
167 struct dbdma_cmd *dma_cmds; /* space for dbdma commands, aligned */
168 dma_addr_t dma_cmd_bus;
169 void *dma_cmd_space;
170 int dma_cmd_size;
171 int clk_freq;
172 struct mesh_target tgts[8];
173 struct macio_dev *mdev;
174 struct pci_dev* pdev;
175 #ifdef MESH_DBG
176 int log_ix;
177 int n_log;
178 struct dbglog log[N_DBG_SLOG];
179 #endif
180 };
181
182 /*
183 * Driver is too messy, we need a few prototypes...
184 */
185 static void mesh_done(struct mesh_state *ms, int start_next);
186 static void mesh_interrupt(struct mesh_state *ms);
187 static void cmd_complete(struct mesh_state *ms);
188 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd);
189 static void halt_dma(struct mesh_state *ms);
190 static void phase_mismatch(struct mesh_state *ms);
191
192
193 /*
194 * Some debugging & logging routines
195 */
196
197 #ifdef MESH_DBG
198
readtb(void)199 static inline u32 readtb(void)
200 {
201 u32 tb;
202
203 #ifdef DBG_USE_TB
204 /* Beware: if you enable this, it will crash on 601s. */
205 asm ("mftb %0" : "=r" (tb) : );
206 #else
207 tb = 0;
208 #endif
209 return tb;
210 }
211
dlog(struct mesh_state * ms,char * fmt,int a)212 static void dlog(struct mesh_state *ms, char *fmt, int a)
213 {
214 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
215 struct dbglog *tlp, *slp;
216
217 tlp = &tp->log[tp->log_ix];
218 slp = &ms->log[ms->log_ix];
219 tlp->fmt = fmt;
220 tlp->tb = readtb();
221 tlp->phase = (ms->msgphase << 4) + ms->phase;
222 tlp->bs0 = ms->mesh->bus_status0;
223 tlp->bs1 = ms->mesh->bus_status1;
224 tlp->tgt = ms->conn_tgt;
225 tlp->d = a;
226 *slp = *tlp;
227 if (++tp->log_ix >= N_DBG_LOG)
228 tp->log_ix = 0;
229 if (tp->n_log < N_DBG_LOG)
230 ++tp->n_log;
231 if (++ms->log_ix >= N_DBG_SLOG)
232 ms->log_ix = 0;
233 if (ms->n_log < N_DBG_SLOG)
234 ++ms->n_log;
235 }
236
dumplog(struct mesh_state * ms,int t)237 static void dumplog(struct mesh_state *ms, int t)
238 {
239 struct mesh_target *tp = &ms->tgts[t];
240 struct dbglog *lp;
241 int i;
242
243 if (tp->n_log == 0)
244 return;
245 i = tp->log_ix - tp->n_log;
246 if (i < 0)
247 i += N_DBG_LOG;
248 tp->n_log = 0;
249 do {
250 lp = &tp->log[i];
251 printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
252 t, lp->bs1, lp->bs0, lp->phase);
253 #ifdef DBG_USE_TB
254 printk("tb=%10u ", lp->tb);
255 #endif
256 printk(lp->fmt, lp->d);
257 printk("\n");
258 if (++i >= N_DBG_LOG)
259 i = 0;
260 } while (i != tp->log_ix);
261 }
262
dumpslog(struct mesh_state * ms)263 static void dumpslog(struct mesh_state *ms)
264 {
265 struct dbglog *lp;
266 int i;
267
268 if (ms->n_log == 0)
269 return;
270 i = ms->log_ix - ms->n_log;
271 if (i < 0)
272 i += N_DBG_SLOG;
273 ms->n_log = 0;
274 do {
275 lp = &ms->log[i];
276 printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
277 lp->bs1, lp->bs0, lp->phase, lp->tgt);
278 #ifdef DBG_USE_TB
279 printk("tb=%10u ", lp->tb);
280 #endif
281 printk(lp->fmt, lp->d);
282 printk("\n");
283 if (++i >= N_DBG_SLOG)
284 i = 0;
285 } while (i != ms->log_ix);
286 }
287
288 #else
289
dlog(struct mesh_state * ms,char * fmt,int a)290 static inline void dlog(struct mesh_state *ms, char *fmt, int a)
291 {}
dumplog(struct mesh_state * ms,int tgt)292 static inline void dumplog(struct mesh_state *ms, int tgt)
293 {}
dumpslog(struct mesh_state * ms)294 static inline void dumpslog(struct mesh_state *ms)
295 {}
296
297 #endif /* MESH_DBG */
298
299 #define MKWORD(a, b, c, d) (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
300
301 static void
mesh_dump_regs(struct mesh_state * ms)302 mesh_dump_regs(struct mesh_state *ms)
303 {
304 volatile struct mesh_regs __iomem *mr = ms->mesh;
305 volatile struct dbdma_regs __iomem *md = ms->dma;
306 int t;
307 struct mesh_target *tp;
308
309 printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
310 ms, mr, md);
311 printk(KERN_DEBUG " ct=%4x seq=%2x bs=%4x fc=%2x "
312 "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
313 (mr->count_hi << 8) + mr->count_lo, mr->sequence,
314 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
315 mr->exception, mr->error, mr->intr_mask, mr->interrupt,
316 mr->sync_params);
317 while(in_8(&mr->fifo_count))
318 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
319 printk(KERN_DEBUG " dma stat=%x cmdptr=%x\n",
320 in_le32(&md->status), in_le32(&md->cmdptr));
321 printk(KERN_DEBUG " phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
322 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
323 printk(KERN_DEBUG " dma_st=%d dma_ct=%d n_msgout=%d\n",
324 ms->dma_started, ms->dma_count, ms->n_msgout);
325 for (t = 0; t < 8; ++t) {
326 tp = &ms->tgts[t];
327 if (tp->current_req == NULL)
328 continue;
329 printk(KERN_DEBUG " target %d: req=%p goes_out=%d saved_ptr=%d\n",
330 t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
331 }
332 }
333
334
335 /*
336 * Flush write buffers on the bus path to the mesh
337 */
mesh_flush_io(volatile struct mesh_regs __iomem * mr)338 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr)
339 {
340 (void)in_8(&mr->mesh_id);
341 }
342
343
344 /*
345 * Complete a SCSI command
346 */
mesh_completed(struct mesh_state * ms,struct scsi_cmnd * cmd)347 static void mesh_completed(struct mesh_state *ms, struct scsi_cmnd *cmd)
348 {
349 (*cmd->scsi_done)(cmd);
350 }
351
352
353 /* Called with meshinterrupt disabled, initialize the chipset
354 * and eventually do the initial bus reset. The lock must not be
355 * held since we can schedule.
356 */
mesh_init(struct mesh_state * ms)357 static void mesh_init(struct mesh_state *ms)
358 {
359 volatile struct mesh_regs __iomem *mr = ms->mesh;
360 volatile struct dbdma_regs __iomem *md = ms->dma;
361
362 mesh_flush_io(mr);
363 udelay(100);
364
365 /* Reset controller */
366 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
367 out_8(&mr->exception, 0xff); /* clear all exception bits */
368 out_8(&mr->error, 0xff); /* clear all error bits */
369 out_8(&mr->sequence, SEQ_RESETMESH);
370 mesh_flush_io(mr);
371 udelay(10);
372 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
373 out_8(&mr->source_id, ms->host->this_id);
374 out_8(&mr->sel_timeout, 25); /* 250ms */
375 out_8(&mr->sync_params, ASYNC_PARAMS);
376
377 if (init_reset_delay) {
378 printk(KERN_INFO "mesh: performing initial bus reset...\n");
379
380 /* Reset bus */
381 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
382 mesh_flush_io(mr);
383 udelay(30); /* leave it on for >= 25us */
384 out_8(&mr->bus_status1, 0); /* negate RST */
385 mesh_flush_io(mr);
386
387 /* Wait for bus to come back */
388 msleep(init_reset_delay);
389 }
390
391 /* Reconfigure controller */
392 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */
393 out_8(&mr->sequence, SEQ_FLUSHFIFO);
394 mesh_flush_io(mr);
395 udelay(1);
396 out_8(&mr->sync_params, ASYNC_PARAMS);
397 out_8(&mr->sequence, SEQ_ENBRESEL);
398
399 ms->phase = idle;
400 ms->msgphase = msg_none;
401 }
402
403
mesh_start_cmd(struct mesh_state * ms,struct scsi_cmnd * cmd)404 static void mesh_start_cmd(struct mesh_state *ms, struct scsi_cmnd *cmd)
405 {
406 volatile struct mesh_regs __iomem *mr = ms->mesh;
407 int t, id;
408
409 id = cmd->device->id;
410 ms->current_req = cmd;
411 ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE;
412 ms->tgts[id].current_req = cmd;
413
414 #if 1
415 if (DEBUG_TARGET(cmd)) {
416 int i;
417 printk(KERN_DEBUG "mesh_start: %p tgt=%d cmd=", cmd, id);
418 for (i = 0; i < cmd->cmd_len; ++i)
419 printk(" %x", cmd->cmnd[i]);
420 printk(" use_sg=%d buffer=%p bufflen=%u\n",
421 scsi_sg_count(cmd), scsi_sglist(cmd), scsi_bufflen(cmd));
422 }
423 #endif
424 if (ms->dma_started)
425 panic("mesh: double DMA start !\n");
426
427 ms->phase = arbitrating;
428 ms->msgphase = msg_none;
429 ms->data_ptr = 0;
430 ms->dma_started = 0;
431 ms->n_msgout = 0;
432 ms->last_n_msgout = 0;
433 ms->expect_reply = 0;
434 ms->conn_tgt = id;
435 ms->tgts[id].saved_ptr = 0;
436 ms->stat = DID_OK;
437 ms->aborting = 0;
438 #ifdef MESH_DBG
439 ms->tgts[id].n_log = 0;
440 dlog(ms, "start cmd=%x", (int) cmd);
441 #endif
442
443 /* Off we go */
444 dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
445 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
446 out_8(&mr->interrupt, INT_CMDDONE);
447 out_8(&mr->sequence, SEQ_ENBRESEL);
448 mesh_flush_io(mr);
449 udelay(1);
450
451 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
452 /*
453 * Some other device has the bus or is arbitrating for it -
454 * probably a target which is about to reselect us.
455 */
456 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
457 MKWORD(mr->interrupt, mr->exception,
458 mr->error, mr->fifo_count));
459 for (t = 100; t > 0; --t) {
460 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0)
461 break;
462 if (in_8(&mr->interrupt) != 0) {
463 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
464 MKWORD(mr->interrupt, mr->exception,
465 mr->error, mr->fifo_count));
466 mesh_interrupt(ms);
467 if (ms->phase != arbitrating)
468 return;
469 }
470 udelay(1);
471 }
472 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
473 /* XXX should try again in a little while */
474 ms->stat = DID_BUS_BUSY;
475 ms->phase = idle;
476 mesh_done(ms, 0);
477 return;
478 }
479 }
480
481 /*
482 * Apparently the mesh has a bug where it will assert both its
483 * own bit and the target's bit on the bus during arbitration.
484 */
485 out_8(&mr->dest_id, mr->source_id);
486
487 /*
488 * There appears to be a race with reselection sometimes,
489 * where a target reselects us just as we issue the
490 * arbitrate command. It seems that then the arbitrate
491 * command just hangs waiting for the bus to be free
492 * without giving us a reselection exception.
493 * The only way I have found to get it to respond correctly
494 * is this: disable reselection before issuing the arbitrate
495 * command, then after issuing it, if it looks like a target
496 * is trying to reselect us, reset the mesh and then enable
497 * reselection.
498 */
499 out_8(&mr->sequence, SEQ_DISRESEL);
500 if (in_8(&mr->interrupt) != 0) {
501 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
502 MKWORD(mr->interrupt, mr->exception,
503 mr->error, mr->fifo_count));
504 mesh_interrupt(ms);
505 if (ms->phase != arbitrating)
506 return;
507 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
508 MKWORD(mr->interrupt, mr->exception,
509 mr->error, mr->fifo_count));
510 }
511
512 out_8(&mr->sequence, SEQ_ARBITRATE);
513
514 for (t = 230; t > 0; --t) {
515 if (in_8(&mr->interrupt) != 0)
516 break;
517 udelay(1);
518 }
519 dlog(ms, "after arb, intr/exc/err/fc=%.8x",
520 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
521 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
522 && (in_8(&mr->bus_status0) & BS0_IO)) {
523 /* looks like a reselection - try resetting the mesh */
524 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
525 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
526 out_8(&mr->sequence, SEQ_RESETMESH);
527 mesh_flush_io(mr);
528 udelay(10);
529 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
530 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
531 out_8(&mr->sequence, SEQ_ENBRESEL);
532 mesh_flush_io(mr);
533 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t)
534 udelay(1);
535 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
536 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
537 #ifndef MESH_MULTIPLE_HOSTS
538 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
539 && (in_8(&mr->bus_status0) & BS0_IO)) {
540 printk(KERN_ERR "mesh: controller not responding"
541 " to reselection!\n");
542 /*
543 * If this is a target reselecting us, and the
544 * mesh isn't responding, the higher levels of
545 * the scsi code will eventually time out and
546 * reset the bus.
547 */
548 }
549 #endif
550 }
551 }
552
553 /*
554 * Start the next command for a MESH.
555 * Should be called with interrupts disabled.
556 */
mesh_start(struct mesh_state * ms)557 static void mesh_start(struct mesh_state *ms)
558 {
559 struct scsi_cmnd *cmd, *prev, *next;
560
561 if (ms->phase != idle || ms->current_req != NULL) {
562 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
563 ms->phase, ms);
564 return;
565 }
566
567 while (ms->phase == idle) {
568 prev = NULL;
569 for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) {
570 if (cmd == NULL)
571 return;
572 if (ms->tgts[cmd->device->id].current_req == NULL)
573 break;
574 prev = cmd;
575 }
576 next = (struct scsi_cmnd *) cmd->host_scribble;
577 if (prev == NULL)
578 ms->request_q = next;
579 else
580 prev->host_scribble = (void *) next;
581 if (next == NULL)
582 ms->request_qtail = prev;
583
584 mesh_start_cmd(ms, cmd);
585 }
586 }
587
mesh_done(struct mesh_state * ms,int start_next)588 static void mesh_done(struct mesh_state *ms, int start_next)
589 {
590 struct scsi_cmnd *cmd;
591 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
592
593 cmd = ms->current_req;
594 ms->current_req = NULL;
595 tp->current_req = NULL;
596 if (cmd) {
597 cmd->result = (ms->stat << 16) + cmd->SCp.Status;
598 if (ms->stat == DID_OK)
599 cmd->result += (cmd->SCp.Message << 8);
600 if (DEBUG_TARGET(cmd)) {
601 printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
602 cmd->result, ms->data_ptr, scsi_bufflen(cmd));
603 #if 0
604 /* needs to use sg? */
605 if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3)
606 && cmd->request_buffer != 0) {
607 unsigned char *b = cmd->request_buffer;
608 printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n",
609 b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
610 }
611 #endif
612 }
613 cmd->SCp.this_residual -= ms->data_ptr;
614 mesh_completed(ms, cmd);
615 }
616 if (start_next) {
617 out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
618 mesh_flush_io(ms->mesh);
619 udelay(1);
620 ms->phase = idle;
621 mesh_start(ms);
622 }
623 }
624
add_sdtr_msg(struct mesh_state * ms)625 static inline void add_sdtr_msg(struct mesh_state *ms)
626 {
627 int i = ms->n_msgout;
628
629 ms->msgout[i] = EXTENDED_MESSAGE;
630 ms->msgout[i+1] = 3;
631 ms->msgout[i+2] = EXTENDED_SDTR;
632 ms->msgout[i+3] = mesh_sync_period/4;
633 ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
634 ms->n_msgout = i + 5;
635 }
636
set_sdtr(struct mesh_state * ms,int period,int offset)637 static void set_sdtr(struct mesh_state *ms, int period, int offset)
638 {
639 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
640 volatile struct mesh_regs __iomem *mr = ms->mesh;
641 int v, tr;
642
643 tp->sdtr_state = sdtr_done;
644 if (offset == 0) {
645 /* asynchronous */
646 if (SYNC_OFF(tp->sync_params))
647 printk(KERN_INFO "mesh: target %d now asynchronous\n",
648 ms->conn_tgt);
649 tp->sync_params = ASYNC_PARAMS;
650 out_8(&mr->sync_params, ASYNC_PARAMS);
651 return;
652 }
653 /*
654 * We need to compute ceil(clk_freq * period / 500e6) - 2
655 * without incurring overflow.
656 */
657 v = (ms->clk_freq / 5000) * period;
658 if (v <= 250000) {
659 /* special case: sync_period == 5 * clk_period */
660 v = 0;
661 /* units of tr are 100kB/s */
662 tr = (ms->clk_freq + 250000) / 500000;
663 } else {
664 /* sync_period == (v + 2) * 2 * clk_period */
665 v = (v + 99999) / 100000 - 2;
666 if (v > 15)
667 v = 15; /* oops */
668 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
669 }
670 if (offset > 15)
671 offset = 15; /* can't happen */
672 tp->sync_params = SYNC_PARAMS(offset, v);
673 out_8(&mr->sync_params, tp->sync_params);
674 printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
675 ms->conn_tgt, tr/10, tr%10);
676 }
677
start_phase(struct mesh_state * ms)678 static void start_phase(struct mesh_state *ms)
679 {
680 int i, seq, nb;
681 volatile struct mesh_regs __iomem *mr = ms->mesh;
682 volatile struct dbdma_regs __iomem *md = ms->dma;
683 struct scsi_cmnd *cmd = ms->current_req;
684 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
685
686 dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
687 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
688 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
689 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
690 switch (ms->msgphase) {
691 case msg_none:
692 break;
693
694 case msg_in:
695 out_8(&mr->count_hi, 0);
696 out_8(&mr->count_lo, 1);
697 out_8(&mr->sequence, SEQ_MSGIN + seq);
698 ms->n_msgin = 0;
699 return;
700
701 case msg_out:
702 /*
703 * To make sure ATN drops before we assert ACK for
704 * the last byte of the message, we have to do the
705 * last byte specially.
706 */
707 if (ms->n_msgout <= 0) {
708 printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
709 ms->n_msgout);
710 mesh_dump_regs(ms);
711 ms->msgphase = msg_none;
712 break;
713 }
714 if (ALLOW_DEBUG(ms->conn_tgt)) {
715 printk(KERN_DEBUG "mesh: sending %d msg bytes:",
716 ms->n_msgout);
717 for (i = 0; i < ms->n_msgout; ++i)
718 printk(" %x", ms->msgout[i]);
719 printk("\n");
720 }
721 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
722 ms->msgout[1], ms->msgout[2]));
723 out_8(&mr->count_hi, 0);
724 out_8(&mr->sequence, SEQ_FLUSHFIFO);
725 mesh_flush_io(mr);
726 udelay(1);
727 /*
728 * If ATN is not already asserted, we assert it, then
729 * issue a SEQ_MSGOUT to get the mesh to drop ACK.
730 */
731 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) {
732 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0);
733 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
734 mesh_flush_io(mr);
735 udelay(1);
736 out_8(&mr->count_lo, 1);
737 out_8(&mr->sequence, SEQ_MSGOUT + seq);
738 out_8(&mr->bus_status0, 0); /* release explicit ATN */
739 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
740 }
741 if (ms->n_msgout == 1) {
742 /*
743 * We can't issue the SEQ_MSGOUT without ATN
744 * until the target has asserted REQ. The logic
745 * in cmd_complete handles both situations:
746 * REQ already asserted or not.
747 */
748 cmd_complete(ms);
749 } else {
750 out_8(&mr->count_lo, ms->n_msgout - 1);
751 out_8(&mr->sequence, SEQ_MSGOUT + seq);
752 for (i = 0; i < ms->n_msgout - 1; ++i)
753 out_8(&mr->fifo, ms->msgout[i]);
754 }
755 return;
756
757 default:
758 printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
759 ms->msgphase);
760 }
761
762 switch (ms->phase) {
763 case selecting:
764 out_8(&mr->dest_id, ms->conn_tgt);
765 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
766 break;
767 case commanding:
768 out_8(&mr->sync_params, tp->sync_params);
769 out_8(&mr->count_hi, 0);
770 if (cmd) {
771 out_8(&mr->count_lo, cmd->cmd_len);
772 out_8(&mr->sequence, SEQ_COMMAND + seq);
773 for (i = 0; i < cmd->cmd_len; ++i)
774 out_8(&mr->fifo, cmd->cmnd[i]);
775 } else {
776 out_8(&mr->count_lo, 6);
777 out_8(&mr->sequence, SEQ_COMMAND + seq);
778 for (i = 0; i < 6; ++i)
779 out_8(&mr->fifo, 0);
780 }
781 break;
782 case dataing:
783 /* transfer data, if any */
784 if (!ms->dma_started) {
785 set_dma_cmds(ms, cmd);
786 out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
787 out_le32(&md->control, (RUN << 16) | RUN);
788 ms->dma_started = 1;
789 }
790 nb = ms->dma_count;
791 if (nb > 0xfff0)
792 nb = 0xfff0;
793 ms->dma_count -= nb;
794 ms->data_ptr += nb;
795 out_8(&mr->count_lo, nb);
796 out_8(&mr->count_hi, nb >> 8);
797 out_8(&mr->sequence, (tp->data_goes_out?
798 SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
799 break;
800 case statusing:
801 out_8(&mr->count_hi, 0);
802 out_8(&mr->count_lo, 1);
803 out_8(&mr->sequence, SEQ_STATUS + seq);
804 break;
805 case busfreeing:
806 case disconnecting:
807 out_8(&mr->sequence, SEQ_ENBRESEL);
808 mesh_flush_io(mr);
809 udelay(1);
810 dlog(ms, "enbresel intr/exc/err/fc=%.8x",
811 MKWORD(mr->interrupt, mr->exception, mr->error,
812 mr->fifo_count));
813 out_8(&mr->sequence, SEQ_BUSFREE);
814 break;
815 default:
816 printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
817 ms->phase);
818 dumpslog(ms);
819 }
820
821 }
822
get_msgin(struct mesh_state * ms)823 static inline void get_msgin(struct mesh_state *ms)
824 {
825 volatile struct mesh_regs __iomem *mr = ms->mesh;
826 int i, n;
827
828 n = mr->fifo_count;
829 if (n != 0) {
830 i = ms->n_msgin;
831 ms->n_msgin = i + n;
832 for (; n > 0; --n)
833 ms->msgin[i++] = in_8(&mr->fifo);
834 }
835 }
836
msgin_length(struct mesh_state * ms)837 static inline int msgin_length(struct mesh_state *ms)
838 {
839 int b, n;
840
841 n = 1;
842 if (ms->n_msgin > 0) {
843 b = ms->msgin[0];
844 if (b == 1) {
845 /* extended message */
846 n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
847 } else if (0x20 <= b && b <= 0x2f) {
848 /* 2-byte message */
849 n = 2;
850 }
851 }
852 return n;
853 }
854
reselected(struct mesh_state * ms)855 static void reselected(struct mesh_state *ms)
856 {
857 volatile struct mesh_regs __iomem *mr = ms->mesh;
858 struct scsi_cmnd *cmd;
859 struct mesh_target *tp;
860 int b, t, prev;
861
862 switch (ms->phase) {
863 case idle:
864 break;
865 case arbitrating:
866 if ((cmd = ms->current_req) != NULL) {
867 /* put the command back on the queue */
868 cmd->host_scribble = (void *) ms->request_q;
869 if (ms->request_q == NULL)
870 ms->request_qtail = cmd;
871 ms->request_q = cmd;
872 tp = &ms->tgts[cmd->device->id];
873 tp->current_req = NULL;
874 }
875 break;
876 case busfreeing:
877 ms->phase = reselecting;
878 mesh_done(ms, 0);
879 break;
880 case disconnecting:
881 break;
882 default:
883 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
884 ms->msgphase, ms->phase, ms->conn_tgt);
885 dumplog(ms, ms->conn_tgt);
886 dumpslog(ms);
887 }
888
889 if (ms->dma_started) {
890 printk(KERN_ERR "mesh: reselected with DMA started !\n");
891 halt_dma(ms);
892 }
893 ms->current_req = NULL;
894 ms->phase = dataing;
895 ms->msgphase = msg_in;
896 ms->n_msgout = 0;
897 ms->last_n_msgout = 0;
898 prev = ms->conn_tgt;
899
900 /*
901 * We seem to get abortive reselections sometimes.
902 */
903 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) {
904 static int mesh_aborted_resels;
905 mesh_aborted_resels++;
906 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
907 mesh_flush_io(mr);
908 udelay(1);
909 out_8(&mr->sequence, SEQ_ENBRESEL);
910 mesh_flush_io(mr);
911 udelay(5);
912 dlog(ms, "extra resel err/exc/fc = %.6x",
913 MKWORD(0, mr->error, mr->exception, mr->fifo_count));
914 }
915 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
916 mesh_flush_io(mr);
917 udelay(1);
918 out_8(&mr->sequence, SEQ_ENBRESEL);
919 mesh_flush_io(mr);
920 udelay(1);
921 out_8(&mr->sync_params, ASYNC_PARAMS);
922
923 /*
924 * Find out who reselected us.
925 */
926 if (in_8(&mr->fifo_count) == 0) {
927 printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
928 ms->conn_tgt = ms->host->this_id;
929 goto bogus;
930 }
931 /* get the last byte in the fifo */
932 do {
933 b = in_8(&mr->fifo);
934 dlog(ms, "reseldata %x", b);
935 } while (in_8(&mr->fifo_count));
936 for (t = 0; t < 8; ++t)
937 if ((b & (1 << t)) != 0 && t != ms->host->this_id)
938 break;
939 if (b != (1 << t) + (1 << ms->host->this_id)) {
940 printk(KERN_ERR "mesh: bad reselection data %x\n", b);
941 ms->conn_tgt = ms->host->this_id;
942 goto bogus;
943 }
944
945
946 /*
947 * Set up to continue with that target's transfer.
948 */
949 ms->conn_tgt = t;
950 tp = &ms->tgts[t];
951 out_8(&mr->sync_params, tp->sync_params);
952 if (ALLOW_DEBUG(t)) {
953 printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
954 printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
955 tp->saved_ptr, tp->data_goes_out, tp->current_req);
956 }
957 ms->current_req = tp->current_req;
958 if (tp->current_req == NULL) {
959 printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
960 goto bogus;
961 }
962 ms->data_ptr = tp->saved_ptr;
963 dlog(ms, "resel prev tgt=%d", prev);
964 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
965 start_phase(ms);
966 return;
967
968 bogus:
969 dumplog(ms, ms->conn_tgt);
970 dumpslog(ms);
971 ms->data_ptr = 0;
972 ms->aborting = 1;
973 start_phase(ms);
974 }
975
do_abort(struct mesh_state * ms)976 static void do_abort(struct mesh_state *ms)
977 {
978 ms->msgout[0] = ABORT;
979 ms->n_msgout = 1;
980 ms->aborting = 1;
981 ms->stat = DID_ABORT;
982 dlog(ms, "abort", 0);
983 }
984
handle_reset(struct mesh_state * ms)985 static void handle_reset(struct mesh_state *ms)
986 {
987 int tgt;
988 struct mesh_target *tp;
989 struct scsi_cmnd *cmd;
990 volatile struct mesh_regs __iomem *mr = ms->mesh;
991
992 for (tgt = 0; tgt < 8; ++tgt) {
993 tp = &ms->tgts[tgt];
994 if ((cmd = tp->current_req) != NULL) {
995 cmd->result = DID_RESET << 16;
996 tp->current_req = NULL;
997 mesh_completed(ms, cmd);
998 }
999 ms->tgts[tgt].sdtr_state = do_sdtr;
1000 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1001 }
1002 ms->current_req = NULL;
1003 while ((cmd = ms->request_q) != NULL) {
1004 ms->request_q = (struct scsi_cmnd *) cmd->host_scribble;
1005 cmd->result = DID_RESET << 16;
1006 mesh_completed(ms, cmd);
1007 }
1008 ms->phase = idle;
1009 ms->msgphase = msg_none;
1010 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1011 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1012 mesh_flush_io(mr);
1013 udelay(1);
1014 out_8(&mr->sync_params, ASYNC_PARAMS);
1015 out_8(&mr->sequence, SEQ_ENBRESEL);
1016 }
1017
do_mesh_interrupt(int irq,void * dev_id)1018 static irqreturn_t do_mesh_interrupt(int irq, void *dev_id)
1019 {
1020 unsigned long flags;
1021 struct mesh_state *ms = dev_id;
1022 struct Scsi_Host *dev = ms->host;
1023
1024 spin_lock_irqsave(dev->host_lock, flags);
1025 mesh_interrupt(ms);
1026 spin_unlock_irqrestore(dev->host_lock, flags);
1027 return IRQ_HANDLED;
1028 }
1029
handle_error(struct mesh_state * ms)1030 static void handle_error(struct mesh_state *ms)
1031 {
1032 int err, exc, count;
1033 volatile struct mesh_regs __iomem *mr = ms->mesh;
1034
1035 err = in_8(&mr->error);
1036 exc = in_8(&mr->exception);
1037 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1038 dlog(ms, "error err/exc/fc/cl=%.8x",
1039 MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1040 if (err & ERR_SCSIRESET) {
1041 /* SCSI bus was reset */
1042 printk(KERN_INFO "mesh: SCSI bus reset detected: "
1043 "waiting for end...");
1044 while ((in_8(&mr->bus_status1) & BS1_RST) != 0)
1045 udelay(1);
1046 printk("done\n");
1047 if (ms->dma_started)
1048 halt_dma(ms);
1049 handle_reset(ms);
1050 /* request_q is empty, no point in mesh_start() */
1051 return;
1052 }
1053 if (err & ERR_UNEXPDISC) {
1054 /* Unexpected disconnect */
1055 if (exc & EXC_RESELECTED) {
1056 reselected(ms);
1057 return;
1058 }
1059 if (!ms->aborting) {
1060 printk(KERN_WARNING "mesh: target %d aborted\n",
1061 ms->conn_tgt);
1062 dumplog(ms, ms->conn_tgt);
1063 dumpslog(ms);
1064 }
1065 out_8(&mr->interrupt, INT_CMDDONE);
1066 ms->stat = DID_ABORT;
1067 mesh_done(ms, 1);
1068 return;
1069 }
1070 if (err & ERR_PARITY) {
1071 if (ms->msgphase == msg_in) {
1072 printk(KERN_ERR "mesh: msg parity error, target %d\n",
1073 ms->conn_tgt);
1074 ms->msgout[0] = MSG_PARITY_ERROR;
1075 ms->n_msgout = 1;
1076 ms->msgphase = msg_in_bad;
1077 cmd_complete(ms);
1078 return;
1079 }
1080 if (ms->stat == DID_OK) {
1081 printk(KERN_ERR "mesh: parity error, target %d\n",
1082 ms->conn_tgt);
1083 ms->stat = DID_PARITY;
1084 }
1085 count = (mr->count_hi << 8) + mr->count_lo;
1086 if (count == 0) {
1087 cmd_complete(ms);
1088 } else {
1089 /* reissue the data transfer command */
1090 out_8(&mr->sequence, mr->sequence);
1091 }
1092 return;
1093 }
1094 if (err & ERR_SEQERR) {
1095 if (exc & EXC_RESELECTED) {
1096 /* This can happen if we issue a command to
1097 get the bus just after the target reselects us. */
1098 static int mesh_resel_seqerr;
1099 mesh_resel_seqerr++;
1100 reselected(ms);
1101 return;
1102 }
1103 if (exc == EXC_PHASEMM) {
1104 static int mesh_phasemm_seqerr;
1105 mesh_phasemm_seqerr++;
1106 phase_mismatch(ms);
1107 return;
1108 }
1109 printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
1110 err, exc);
1111 } else {
1112 printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
1113 }
1114 mesh_dump_regs(ms);
1115 dumplog(ms, ms->conn_tgt);
1116 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) {
1117 /* try to do what the target wants */
1118 do_abort(ms);
1119 phase_mismatch(ms);
1120 return;
1121 }
1122 ms->stat = DID_ERROR;
1123 mesh_done(ms, 1);
1124 }
1125
handle_exception(struct mesh_state * ms)1126 static void handle_exception(struct mesh_state *ms)
1127 {
1128 int exc;
1129 volatile struct mesh_regs __iomem *mr = ms->mesh;
1130
1131 exc = in_8(&mr->exception);
1132 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1133 if (exc & EXC_RESELECTED) {
1134 static int mesh_resel_exc;
1135 mesh_resel_exc++;
1136 reselected(ms);
1137 } else if (exc == EXC_ARBLOST) {
1138 printk(KERN_DEBUG "mesh: lost arbitration\n");
1139 ms->stat = DID_BUS_BUSY;
1140 mesh_done(ms, 1);
1141 } else if (exc == EXC_SELTO) {
1142 /* selection timed out */
1143 ms->stat = DID_BAD_TARGET;
1144 mesh_done(ms, 1);
1145 } else if (exc == EXC_PHASEMM) {
1146 /* target wants to do something different:
1147 find out what it wants and do it. */
1148 phase_mismatch(ms);
1149 } else {
1150 printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
1151 mesh_dump_regs(ms);
1152 dumplog(ms, ms->conn_tgt);
1153 do_abort(ms);
1154 phase_mismatch(ms);
1155 }
1156 }
1157
handle_msgin(struct mesh_state * ms)1158 static void handle_msgin(struct mesh_state *ms)
1159 {
1160 int i, code;
1161 struct scsi_cmnd *cmd = ms->current_req;
1162 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1163
1164 if (ms->n_msgin == 0)
1165 return;
1166 code = ms->msgin[0];
1167 if (ALLOW_DEBUG(ms->conn_tgt)) {
1168 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
1169 for (i = 0; i < ms->n_msgin; ++i)
1170 printk(" %x", ms->msgin[i]);
1171 printk("\n");
1172 }
1173 dlog(ms, "msgin msg=%.8x",
1174 MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
1175
1176 ms->expect_reply = 0;
1177 ms->n_msgout = 0;
1178 if (ms->n_msgin < msgin_length(ms))
1179 goto reject;
1180 if (cmd)
1181 cmd->SCp.Message = code;
1182 switch (code) {
1183 case COMMAND_COMPLETE:
1184 break;
1185 case EXTENDED_MESSAGE:
1186 switch (ms->msgin[2]) {
1187 case EXTENDED_MODIFY_DATA_POINTER:
1188 ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
1189 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
1190 break;
1191 case EXTENDED_SDTR:
1192 if (tp->sdtr_state != sdtr_sent) {
1193 /* reply with an SDTR */
1194 add_sdtr_msg(ms);
1195 /* limit period to at least his value,
1196 offset to no more than his */
1197 if (ms->msgout[3] < ms->msgin[3])
1198 ms->msgout[3] = ms->msgin[3];
1199 if (ms->msgout[4] > ms->msgin[4])
1200 ms->msgout[4] = ms->msgin[4];
1201 set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
1202 ms->msgphase = msg_out;
1203 } else {
1204 set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
1205 }
1206 break;
1207 default:
1208 goto reject;
1209 }
1210 break;
1211 case SAVE_POINTERS:
1212 tp->saved_ptr = ms->data_ptr;
1213 break;
1214 case RESTORE_POINTERS:
1215 ms->data_ptr = tp->saved_ptr;
1216 break;
1217 case DISCONNECT:
1218 ms->phase = disconnecting;
1219 break;
1220 case ABORT:
1221 break;
1222 case MESSAGE_REJECT:
1223 if (tp->sdtr_state == sdtr_sent)
1224 set_sdtr(ms, 0, 0);
1225 break;
1226 case NOP:
1227 break;
1228 default:
1229 if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
1230 if (cmd == NULL) {
1231 do_abort(ms);
1232 ms->msgphase = msg_out;
1233 } else if (code != cmd->device->lun + IDENTIFY_BASE) {
1234 printk(KERN_WARNING "mesh: lun mismatch "
1235 "(%d != %llu) on reselection from "
1236 "target %d\n", code - IDENTIFY_BASE,
1237 cmd->device->lun, ms->conn_tgt);
1238 }
1239 break;
1240 }
1241 goto reject;
1242 }
1243 return;
1244
1245 reject:
1246 printk(KERN_WARNING "mesh: rejecting message from target %d:",
1247 ms->conn_tgt);
1248 for (i = 0; i < ms->n_msgin; ++i)
1249 printk(" %x", ms->msgin[i]);
1250 printk("\n");
1251 ms->msgout[0] = MESSAGE_REJECT;
1252 ms->n_msgout = 1;
1253 ms->msgphase = msg_out;
1254 }
1255
1256 /*
1257 * Set up DMA commands for transferring data.
1258 */
set_dma_cmds(struct mesh_state * ms,struct scsi_cmnd * cmd)1259 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd)
1260 {
1261 int i, dma_cmd, total, off, dtot;
1262 struct scatterlist *scl;
1263 struct dbdma_cmd *dcmds;
1264
1265 dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
1266 OUTPUT_MORE: INPUT_MORE;
1267 dcmds = ms->dma_cmds;
1268 dtot = 0;
1269 if (cmd) {
1270 int nseg;
1271
1272 cmd->SCp.this_residual = scsi_bufflen(cmd);
1273
1274 nseg = scsi_dma_map(cmd);
1275 BUG_ON(nseg < 0);
1276
1277 if (nseg) {
1278 total = 0;
1279 off = ms->data_ptr;
1280
1281 scsi_for_each_sg(cmd, scl, nseg, i) {
1282 u32 dma_addr = sg_dma_address(scl);
1283 u32 dma_len = sg_dma_len(scl);
1284
1285 total += scl->length;
1286 if (off >= dma_len) {
1287 off -= dma_len;
1288 continue;
1289 }
1290 if (dma_len > 0xffff)
1291 panic("mesh: scatterlist element >= 64k");
1292 dcmds->req_count = cpu_to_le16(dma_len - off);
1293 dcmds->command = cpu_to_le16(dma_cmd);
1294 dcmds->phy_addr = cpu_to_le32(dma_addr + off);
1295 dcmds->xfer_status = 0;
1296 ++dcmds;
1297 dtot += dma_len - off;
1298 off = 0;
1299 }
1300 }
1301 }
1302 if (dtot == 0) {
1303 /* Either the target has overrun our buffer,
1304 or the caller didn't provide a buffer. */
1305 static char mesh_extra_buf[64];
1306
1307 dtot = sizeof(mesh_extra_buf);
1308 dcmds->req_count = cpu_to_le16(dtot);
1309 dcmds->phy_addr = cpu_to_le32(virt_to_phys(mesh_extra_buf));
1310 dcmds->xfer_status = 0;
1311 ++dcmds;
1312 }
1313 dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
1314 dcmds[-1].command = cpu_to_le16(dma_cmd);
1315 memset(dcmds, 0, sizeof(*dcmds));
1316 dcmds->command = cpu_to_le16(DBDMA_STOP);
1317 ms->dma_count = dtot;
1318 }
1319
halt_dma(struct mesh_state * ms)1320 static void halt_dma(struct mesh_state *ms)
1321 {
1322 volatile struct dbdma_regs __iomem *md = ms->dma;
1323 volatile struct mesh_regs __iomem *mr = ms->mesh;
1324 struct scsi_cmnd *cmd = ms->current_req;
1325 int t, nb;
1326
1327 if (!ms->tgts[ms->conn_tgt].data_goes_out) {
1328 /* wait a little while until the fifo drains */
1329 t = 50;
1330 while (t > 0 && in_8(&mr->fifo_count) != 0
1331 && (in_le32(&md->status) & ACTIVE) != 0) {
1332 --t;
1333 udelay(1);
1334 }
1335 }
1336 out_le32(&md->control, RUN << 16); /* turn off RUN bit */
1337 nb = (mr->count_hi << 8) + mr->count_lo;
1338 dlog(ms, "halt_dma fc/count=%.6x",
1339 MKWORD(0, mr->fifo_count, 0, nb));
1340 if (ms->tgts[ms->conn_tgt].data_goes_out)
1341 nb += mr->fifo_count;
1342 /* nb is the number of bytes not yet transferred
1343 to/from the target. */
1344 ms->data_ptr -= nb;
1345 dlog(ms, "data_ptr %x", ms->data_ptr);
1346 if (ms->data_ptr < 0) {
1347 printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
1348 ms->data_ptr, nb, ms);
1349 ms->data_ptr = 0;
1350 #ifdef MESH_DBG
1351 dumplog(ms, ms->conn_tgt);
1352 dumpslog(ms);
1353 #endif /* MESH_DBG */
1354 } else if (cmd && scsi_bufflen(cmd) &&
1355 ms->data_ptr > scsi_bufflen(cmd)) {
1356 printk(KERN_DEBUG "mesh: target %d overrun, "
1357 "data_ptr=%x total=%x goes_out=%d\n",
1358 ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd),
1359 ms->tgts[ms->conn_tgt].data_goes_out);
1360 }
1361 if (cmd)
1362 scsi_dma_unmap(cmd);
1363 ms->dma_started = 0;
1364 }
1365
phase_mismatch(struct mesh_state * ms)1366 static void phase_mismatch(struct mesh_state *ms)
1367 {
1368 volatile struct mesh_regs __iomem *mr = ms->mesh;
1369 int phase;
1370
1371 dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
1372 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1373 phase = in_8(&mr->bus_status0) & BS0_PHASE;
1374 if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
1375 /* output the last byte of the message, without ATN */
1376 out_8(&mr->count_lo, 1);
1377 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1378 mesh_flush_io(mr);
1379 udelay(1);
1380 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1381 ms->msgphase = msg_out_last;
1382 return;
1383 }
1384
1385 if (ms->msgphase == msg_in) {
1386 get_msgin(ms);
1387 if (ms->n_msgin)
1388 handle_msgin(ms);
1389 }
1390
1391 if (ms->dma_started)
1392 halt_dma(ms);
1393 if (mr->fifo_count) {
1394 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1395 mesh_flush_io(mr);
1396 udelay(1);
1397 }
1398
1399 ms->msgphase = msg_none;
1400 switch (phase) {
1401 case BP_DATAIN:
1402 ms->tgts[ms->conn_tgt].data_goes_out = 0;
1403 ms->phase = dataing;
1404 break;
1405 case BP_DATAOUT:
1406 ms->tgts[ms->conn_tgt].data_goes_out = 1;
1407 ms->phase = dataing;
1408 break;
1409 case BP_COMMAND:
1410 ms->phase = commanding;
1411 break;
1412 case BP_STATUS:
1413 ms->phase = statusing;
1414 break;
1415 case BP_MSGIN:
1416 ms->msgphase = msg_in;
1417 ms->n_msgin = 0;
1418 break;
1419 case BP_MSGOUT:
1420 ms->msgphase = msg_out;
1421 if (ms->n_msgout == 0) {
1422 if (ms->aborting) {
1423 do_abort(ms);
1424 } else {
1425 if (ms->last_n_msgout == 0) {
1426 printk(KERN_DEBUG
1427 "mesh: no msg to repeat\n");
1428 ms->msgout[0] = NOP;
1429 ms->last_n_msgout = 1;
1430 }
1431 ms->n_msgout = ms->last_n_msgout;
1432 }
1433 }
1434 break;
1435 default:
1436 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
1437 ms->stat = DID_ERROR;
1438 mesh_done(ms, 1);
1439 return;
1440 }
1441
1442 start_phase(ms);
1443 }
1444
cmd_complete(struct mesh_state * ms)1445 static void cmd_complete(struct mesh_state *ms)
1446 {
1447 volatile struct mesh_regs __iomem *mr = ms->mesh;
1448 struct scsi_cmnd *cmd = ms->current_req;
1449 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1450 int seq, n, t;
1451
1452 dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
1453 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
1454 switch (ms->msgphase) {
1455 case msg_out_xxx:
1456 /* huh? we expected a phase mismatch */
1457 ms->n_msgin = 0;
1458 ms->msgphase = msg_in;
1459 /* fall through */
1460
1461 case msg_in:
1462 /* should have some message bytes in fifo */
1463 get_msgin(ms);
1464 n = msgin_length(ms);
1465 if (ms->n_msgin < n) {
1466 out_8(&mr->count_lo, n - ms->n_msgin);
1467 out_8(&mr->sequence, SEQ_MSGIN + seq);
1468 } else {
1469 ms->msgphase = msg_none;
1470 handle_msgin(ms);
1471 start_phase(ms);
1472 }
1473 break;
1474
1475 case msg_in_bad:
1476 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1477 mesh_flush_io(mr);
1478 udelay(1);
1479 out_8(&mr->count_lo, 1);
1480 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
1481 break;
1482
1483 case msg_out:
1484 /*
1485 * To get the right timing on ATN wrt ACK, we have
1486 * to get the MESH to drop ACK, wait until REQ gets
1487 * asserted, then drop ATN. To do this we first
1488 * issue a SEQ_MSGOUT with ATN and wait for REQ,
1489 * then change the command to a SEQ_MSGOUT w/o ATN.
1490 * If we don't see REQ in a reasonable time, we
1491 * change the command to SEQ_MSGIN with ATN,
1492 * wait for the phase mismatch interrupt, then
1493 * issue the SEQ_MSGOUT without ATN.
1494 */
1495 out_8(&mr->count_lo, 1);
1496 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1497 t = 30; /* wait up to 30us */
1498 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0)
1499 udelay(1);
1500 dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
1501 MKWORD(mr->error, mr->exception,
1502 mr->fifo_count, mr->count_lo));
1503 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1504 /* whoops, target didn't do what we expected */
1505 ms->last_n_msgout = ms->n_msgout;
1506 ms->n_msgout = 0;
1507 if (in_8(&mr->interrupt) & INT_ERROR) {
1508 printk(KERN_ERR "mesh: error %x in msg_out\n",
1509 in_8(&mr->error));
1510 handle_error(ms);
1511 return;
1512 }
1513 if (in_8(&mr->exception) != EXC_PHASEMM)
1514 printk(KERN_ERR "mesh: exc %x in msg_out\n",
1515 in_8(&mr->exception));
1516 else
1517 printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
1518 in_8(&mr->bus_status0));
1519 handle_exception(ms);
1520 return;
1521 }
1522 if (in_8(&mr->bus_status0) & BS0_REQ) {
1523 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1524 mesh_flush_io(mr);
1525 udelay(1);
1526 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1527 ms->msgphase = msg_out_last;
1528 } else {
1529 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1530 ms->msgphase = msg_out_xxx;
1531 }
1532 break;
1533
1534 case msg_out_last:
1535 ms->last_n_msgout = ms->n_msgout;
1536 ms->n_msgout = 0;
1537 ms->msgphase = ms->expect_reply? msg_in: msg_none;
1538 start_phase(ms);
1539 break;
1540
1541 case msg_none:
1542 switch (ms->phase) {
1543 case idle:
1544 printk(KERN_ERR "mesh: interrupt in idle phase?\n");
1545 dumpslog(ms);
1546 return;
1547 case selecting:
1548 dlog(ms, "Selecting phase at command completion",0);
1549 ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
1550 (cmd? cmd->device->lun: 0));
1551 ms->n_msgout = 1;
1552 ms->expect_reply = 0;
1553 if (ms->aborting) {
1554 ms->msgout[0] = ABORT;
1555 ms->n_msgout++;
1556 } else if (tp->sdtr_state == do_sdtr) {
1557 /* add SDTR message */
1558 add_sdtr_msg(ms);
1559 ms->expect_reply = 1;
1560 tp->sdtr_state = sdtr_sent;
1561 }
1562 ms->msgphase = msg_out;
1563 /*
1564 * We need to wait for REQ before dropping ATN.
1565 * We wait for at most 30us, then fall back to
1566 * a scheme where we issue a SEQ_COMMAND with ATN,
1567 * which will give us a phase mismatch interrupt
1568 * when REQ does come, and then we send the message.
1569 */
1570 t = 230; /* wait up to 230us */
1571 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) {
1572 if (--t < 0) {
1573 dlog(ms, "impatient for req", ms->n_msgout);
1574 ms->msgphase = msg_none;
1575 break;
1576 }
1577 udelay(1);
1578 }
1579 break;
1580 case dataing:
1581 if (ms->dma_count != 0) {
1582 start_phase(ms);
1583 return;
1584 }
1585 /*
1586 * We can get a phase mismatch here if the target
1587 * changes to the status phase, even though we have
1588 * had a command complete interrupt. Then, if we
1589 * issue the SEQ_STATUS command, we'll get a sequence
1590 * error interrupt. Which isn't so bad except that
1591 * occasionally the mesh actually executes the
1592 * SEQ_STATUS *as well as* giving us the sequence
1593 * error and phase mismatch exception.
1594 */
1595 out_8(&mr->sequence, 0);
1596 out_8(&mr->interrupt,
1597 INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1598 halt_dma(ms);
1599 break;
1600 case statusing:
1601 if (cmd) {
1602 cmd->SCp.Status = mr->fifo;
1603 if (DEBUG_TARGET(cmd))
1604 printk(KERN_DEBUG "mesh: status is %x\n",
1605 cmd->SCp.Status);
1606 }
1607 ms->msgphase = msg_in;
1608 break;
1609 case busfreeing:
1610 mesh_done(ms, 1);
1611 return;
1612 case disconnecting:
1613 ms->current_req = NULL;
1614 ms->phase = idle;
1615 mesh_start(ms);
1616 return;
1617 default:
1618 break;
1619 }
1620 ++ms->phase;
1621 start_phase(ms);
1622 break;
1623 }
1624 }
1625
1626
1627 /*
1628 * Called by midlayer with host locked to queue a new
1629 * request
1630 */
mesh_queue_lck(struct scsi_cmnd * cmd,void (* done)(struct scsi_cmnd *))1631 static int mesh_queue_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
1632 {
1633 struct mesh_state *ms;
1634
1635 cmd->scsi_done = done;
1636 cmd->host_scribble = NULL;
1637
1638 ms = (struct mesh_state *) cmd->device->host->hostdata;
1639
1640 if (ms->request_q == NULL)
1641 ms->request_q = cmd;
1642 else
1643 ms->request_qtail->host_scribble = (void *) cmd;
1644 ms->request_qtail = cmd;
1645
1646 if (ms->phase == idle)
1647 mesh_start(ms);
1648
1649 return 0;
1650 }
1651
DEF_SCSI_QCMD(mesh_queue)1652 static DEF_SCSI_QCMD(mesh_queue)
1653
1654 /*
1655 * Called to handle interrupts, either call by the interrupt
1656 * handler (do_mesh_interrupt) or by other functions in
1657 * exceptional circumstances
1658 */
1659 static void mesh_interrupt(struct mesh_state *ms)
1660 {
1661 volatile struct mesh_regs __iomem *mr = ms->mesh;
1662 int intr;
1663
1664 #if 0
1665 if (ALLOW_DEBUG(ms->conn_tgt))
1666 printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x "
1667 "phase=%d msgphase=%d\n", mr->bus_status0,
1668 mr->interrupt, mr->exception, mr->error,
1669 ms->phase, ms->msgphase);
1670 #endif
1671 while ((intr = in_8(&mr->interrupt)) != 0) {
1672 dlog(ms, "interrupt intr/err/exc/seq=%.8x",
1673 MKWORD(intr, mr->error, mr->exception, mr->sequence));
1674 if (intr & INT_ERROR) {
1675 handle_error(ms);
1676 } else if (intr & INT_EXCEPTION) {
1677 handle_exception(ms);
1678 } else if (intr & INT_CMDDONE) {
1679 out_8(&mr->interrupt, INT_CMDDONE);
1680 cmd_complete(ms);
1681 }
1682 }
1683 }
1684
1685 /* Todo: here we can at least try to remove the command from the
1686 * queue if it isn't connected yet, and for pending command, assert
1687 * ATN until the bus gets freed.
1688 */
mesh_abort(struct scsi_cmnd * cmd)1689 static int mesh_abort(struct scsi_cmnd *cmd)
1690 {
1691 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1692
1693 printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
1694 mesh_dump_regs(ms);
1695 dumplog(ms, cmd->device->id);
1696 dumpslog(ms);
1697 return FAILED;
1698 }
1699
1700 /*
1701 * Called by the midlayer with the lock held to reset the
1702 * SCSI host and bus.
1703 * The midlayer will wait for devices to come back, we don't need
1704 * to do that ourselves
1705 */
mesh_host_reset(struct scsi_cmnd * cmd)1706 static int mesh_host_reset(struct scsi_cmnd *cmd)
1707 {
1708 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1709 volatile struct mesh_regs __iomem *mr = ms->mesh;
1710 volatile struct dbdma_regs __iomem *md = ms->dma;
1711 unsigned long flags;
1712
1713 printk(KERN_DEBUG "mesh_host_reset\n");
1714
1715 spin_lock_irqsave(ms->host->host_lock, flags);
1716
1717 if (ms->dma_started)
1718 halt_dma(ms);
1719
1720 /* Reset the controller & dbdma channel */
1721 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
1722 out_8(&mr->exception, 0xff); /* clear all exception bits */
1723 out_8(&mr->error, 0xff); /* clear all error bits */
1724 out_8(&mr->sequence, SEQ_RESETMESH);
1725 mesh_flush_io(mr);
1726 udelay(1);
1727 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1728 out_8(&mr->source_id, ms->host->this_id);
1729 out_8(&mr->sel_timeout, 25); /* 250ms */
1730 out_8(&mr->sync_params, ASYNC_PARAMS);
1731
1732 /* Reset the bus */
1733 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
1734 mesh_flush_io(mr);
1735 udelay(30); /* leave it on for >= 25us */
1736 out_8(&mr->bus_status1, 0); /* negate RST */
1737
1738 /* Complete pending commands */
1739 handle_reset(ms);
1740
1741 spin_unlock_irqrestore(ms->host->host_lock, flags);
1742 return SUCCESS;
1743 }
1744
set_mesh_power(struct mesh_state * ms,int state)1745 static void set_mesh_power(struct mesh_state *ms, int state)
1746 {
1747 if (!machine_is(powermac))
1748 return;
1749 if (state) {
1750 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1);
1751 msleep(200);
1752 } else {
1753 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0);
1754 msleep(10);
1755 }
1756 }
1757
1758
1759 #ifdef CONFIG_PM
mesh_suspend(struct macio_dev * mdev,pm_message_t mesg)1760 static int mesh_suspend(struct macio_dev *mdev, pm_message_t mesg)
1761 {
1762 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1763 unsigned long flags;
1764
1765 switch (mesg.event) {
1766 case PM_EVENT_SUSPEND:
1767 case PM_EVENT_HIBERNATE:
1768 case PM_EVENT_FREEZE:
1769 break;
1770 default:
1771 return 0;
1772 }
1773 if (ms->phase == sleeping)
1774 return 0;
1775
1776 scsi_block_requests(ms->host);
1777 spin_lock_irqsave(ms->host->host_lock, flags);
1778 while(ms->phase != idle) {
1779 spin_unlock_irqrestore(ms->host->host_lock, flags);
1780 msleep(10);
1781 spin_lock_irqsave(ms->host->host_lock, flags);
1782 }
1783 ms->phase = sleeping;
1784 spin_unlock_irqrestore(ms->host->host_lock, flags);
1785 disable_irq(ms->meshintr);
1786 set_mesh_power(ms, 0);
1787
1788 return 0;
1789 }
1790
mesh_resume(struct macio_dev * mdev)1791 static int mesh_resume(struct macio_dev *mdev)
1792 {
1793 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1794 unsigned long flags;
1795
1796 if (ms->phase != sleeping)
1797 return 0;
1798
1799 set_mesh_power(ms, 1);
1800 mesh_init(ms);
1801 spin_lock_irqsave(ms->host->host_lock, flags);
1802 mesh_start(ms);
1803 spin_unlock_irqrestore(ms->host->host_lock, flags);
1804 enable_irq(ms->meshintr);
1805 scsi_unblock_requests(ms->host);
1806
1807 return 0;
1808 }
1809
1810 #endif /* CONFIG_PM */
1811
1812 /*
1813 * If we leave drives set for synchronous transfers (especially
1814 * CDROMs), and reboot to MacOS, it gets confused, poor thing.
1815 * So, on reboot we reset the SCSI bus.
1816 */
mesh_shutdown(struct macio_dev * mdev)1817 static int mesh_shutdown(struct macio_dev *mdev)
1818 {
1819 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1820 volatile struct mesh_regs __iomem *mr;
1821 unsigned long flags;
1822
1823 printk(KERN_INFO "resetting MESH scsi bus(es)\n");
1824 spin_lock_irqsave(ms->host->host_lock, flags);
1825 mr = ms->mesh;
1826 out_8(&mr->intr_mask, 0);
1827 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1828 out_8(&mr->bus_status1, BS1_RST);
1829 mesh_flush_io(mr);
1830 udelay(30);
1831 out_8(&mr->bus_status1, 0);
1832 spin_unlock_irqrestore(ms->host->host_lock, flags);
1833
1834 return 0;
1835 }
1836
1837 static struct scsi_host_template mesh_template = {
1838 .proc_name = "mesh",
1839 .name = "MESH",
1840 .queuecommand = mesh_queue,
1841 .eh_abort_handler = mesh_abort,
1842 .eh_host_reset_handler = mesh_host_reset,
1843 .can_queue = 20,
1844 .this_id = 7,
1845 .sg_tablesize = SG_ALL,
1846 .cmd_per_lun = 2,
1847 .use_clustering = DISABLE_CLUSTERING,
1848 };
1849
mesh_probe(struct macio_dev * mdev,const struct of_device_id * match)1850 static int mesh_probe(struct macio_dev *mdev, const struct of_device_id *match)
1851 {
1852 struct device_node *mesh = macio_get_of_node(mdev);
1853 struct pci_dev* pdev = macio_get_pci_dev(mdev);
1854 int tgt, minper;
1855 const int *cfp;
1856 struct mesh_state *ms;
1857 struct Scsi_Host *mesh_host;
1858 void *dma_cmd_space;
1859 dma_addr_t dma_cmd_bus;
1860
1861 switch (mdev->bus->chip->type) {
1862 case macio_heathrow:
1863 case macio_gatwick:
1864 case macio_paddington:
1865 use_active_neg = 0;
1866 break;
1867 default:
1868 use_active_neg = SEQ_ACTIVE_NEG;
1869 }
1870
1871 if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) {
1872 printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
1873 " (got %d,%d)\n", macio_resource_count(mdev),
1874 macio_irq_count(mdev));
1875 return -ENODEV;
1876 }
1877
1878 if (macio_request_resources(mdev, "mesh") != 0) {
1879 printk(KERN_ERR "mesh: unable to request memory resources");
1880 return -EBUSY;
1881 }
1882 mesh_host = scsi_host_alloc(&mesh_template, sizeof(struct mesh_state));
1883 if (mesh_host == NULL) {
1884 printk(KERN_ERR "mesh: couldn't register host");
1885 goto out_release;
1886 }
1887
1888 /* Old junk for root discovery, that will die ultimately */
1889 #if !defined(MODULE)
1890 note_scsi_host(mesh, mesh_host);
1891 #endif
1892
1893 mesh_host->base = macio_resource_start(mdev, 0);
1894 mesh_host->irq = macio_irq(mdev, 0);
1895 ms = (struct mesh_state *) mesh_host->hostdata;
1896 macio_set_drvdata(mdev, ms);
1897 ms->host = mesh_host;
1898 ms->mdev = mdev;
1899 ms->pdev = pdev;
1900
1901 ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000);
1902 if (ms->mesh == NULL) {
1903 printk(KERN_ERR "mesh: can't map registers\n");
1904 goto out_free;
1905 }
1906 ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
1907 if (ms->dma == NULL) {
1908 printk(KERN_ERR "mesh: can't map registers\n");
1909 iounmap(ms->mesh);
1910 goto out_free;
1911 }
1912
1913 ms->meshintr = macio_irq(mdev, 0);
1914 ms->dmaintr = macio_irq(mdev, 1);
1915
1916 /* Space for dma command list: +1 for stop command,
1917 * +1 to allow for aligning.
1918 */
1919 ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd);
1920
1921 /* We use the PCI APIs for now until the generic one gets fixed
1922 * enough or until we get some macio-specific versions
1923 */
1924 dma_cmd_space = pci_zalloc_consistent(macio_get_pci_dev(mdev),
1925 ms->dma_cmd_size, &dma_cmd_bus);
1926 if (dma_cmd_space == NULL) {
1927 printk(KERN_ERR "mesh: can't allocate DMA table\n");
1928 goto out_unmap;
1929 }
1930
1931 ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
1932 ms->dma_cmd_space = dma_cmd_space;
1933 ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds)
1934 - (unsigned long)dma_cmd_space;
1935 ms->current_req = NULL;
1936 for (tgt = 0; tgt < 8; ++tgt) {
1937 ms->tgts[tgt].sdtr_state = do_sdtr;
1938 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1939 ms->tgts[tgt].current_req = NULL;
1940 }
1941
1942 if ((cfp = of_get_property(mesh, "clock-frequency", NULL)))
1943 ms->clk_freq = *cfp;
1944 else {
1945 printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
1946 ms->clk_freq = 50000000;
1947 }
1948
1949 /* The maximum sync rate is clock / 5; increase
1950 * mesh_sync_period if necessary.
1951 */
1952 minper = 1000000000 / (ms->clk_freq / 5); /* ns */
1953 if (mesh_sync_period < minper)
1954 mesh_sync_period = minper;
1955
1956 /* Power up the chip */
1957 set_mesh_power(ms, 1);
1958
1959 /* Set it up */
1960 mesh_init(ms);
1961
1962 /* Request interrupt */
1963 if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
1964 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
1965 goto out_shutdown;
1966 }
1967
1968 /* Add scsi host & scan */
1969 if (scsi_add_host(mesh_host, &mdev->ofdev.dev))
1970 goto out_release_irq;
1971 scsi_scan_host(mesh_host);
1972
1973 return 0;
1974
1975 out_release_irq:
1976 free_irq(ms->meshintr, ms);
1977 out_shutdown:
1978 /* shutdown & reset bus in case of error or macos can be confused
1979 * at reboot if the bus was set to synchronous mode already
1980 */
1981 mesh_shutdown(mdev);
1982 set_mesh_power(ms, 0);
1983 pci_free_consistent(macio_get_pci_dev(mdev), ms->dma_cmd_size,
1984 ms->dma_cmd_space, ms->dma_cmd_bus);
1985 out_unmap:
1986 iounmap(ms->dma);
1987 iounmap(ms->mesh);
1988 out_free:
1989 scsi_host_put(mesh_host);
1990 out_release:
1991 macio_release_resources(mdev);
1992
1993 return -ENODEV;
1994 }
1995
mesh_remove(struct macio_dev * mdev)1996 static int mesh_remove(struct macio_dev *mdev)
1997 {
1998 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1999 struct Scsi_Host *mesh_host = ms->host;
2000
2001 scsi_remove_host(mesh_host);
2002
2003 free_irq(ms->meshintr, ms);
2004
2005 /* Reset scsi bus */
2006 mesh_shutdown(mdev);
2007
2008 /* Shut down chip & termination */
2009 set_mesh_power(ms, 0);
2010
2011 /* Unmap registers & dma controller */
2012 iounmap(ms->mesh);
2013 iounmap(ms->dma);
2014
2015 /* Free DMA commands memory */
2016 pci_free_consistent(macio_get_pci_dev(mdev), ms->dma_cmd_size,
2017 ms->dma_cmd_space, ms->dma_cmd_bus);
2018
2019 /* Release memory resources */
2020 macio_release_resources(mdev);
2021
2022 scsi_host_put(mesh_host);
2023
2024 return 0;
2025 }
2026
2027
2028 static struct of_device_id mesh_match[] =
2029 {
2030 {
2031 .name = "mesh",
2032 },
2033 {
2034 .type = "scsi",
2035 .compatible = "chrp,mesh0"
2036 },
2037 {},
2038 };
2039 MODULE_DEVICE_TABLE (of, mesh_match);
2040
2041 static struct macio_driver mesh_driver =
2042 {
2043 .driver = {
2044 .name = "mesh",
2045 .owner = THIS_MODULE,
2046 .of_match_table = mesh_match,
2047 },
2048 .probe = mesh_probe,
2049 .remove = mesh_remove,
2050 .shutdown = mesh_shutdown,
2051 #ifdef CONFIG_PM
2052 .suspend = mesh_suspend,
2053 .resume = mesh_resume,
2054 #endif
2055 };
2056
2057
init_mesh(void)2058 static int __init init_mesh(void)
2059 {
2060
2061 /* Calculate sync rate from module parameters */
2062 if (sync_rate > 10)
2063 sync_rate = 10;
2064 if (sync_rate > 0) {
2065 printk(KERN_INFO "mesh: configured for synchronous %d MB/s\n", sync_rate);
2066 mesh_sync_period = 1000 / sync_rate; /* ns */
2067 mesh_sync_offset = 15;
2068 } else
2069 printk(KERN_INFO "mesh: configured for asynchronous\n");
2070
2071 return macio_register_driver(&mesh_driver);
2072 }
2073
exit_mesh(void)2074 static void __exit exit_mesh(void)
2075 {
2076 return macio_unregister_driver(&mesh_driver);
2077 }
2078
2079 module_init(init_mesh);
2080 module_exit(exit_mesh);
2081