1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <scsi/scsi_tcq.h>
17 #include <scsi/scsicam.h>
18 #include <scsi/scsi_transport.h>
19 #include <scsi/scsi_transport_fc.h>
20
21 #include "qla_target.h"
22
23 /*
24 * Driver version
25 */
26 char qla2x00_version_str[40];
27
28 static int apidev_major;
29
30 /*
31 * SRB allocation cache
32 */
33 static struct kmem_cache *srb_cachep;
34
35 /*
36 * CT6 CTX allocation cache
37 */
38 static struct kmem_cache *ctx_cachep;
39 /*
40 * error level for logging
41 */
42 int ql_errlev = ql_log_all;
43
44 static int ql2xenableclass2;
45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46 MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
50
51 int ql2xlogintimeout = 20;
52 module_param(ql2xlogintimeout, int, S_IRUGO);
53 MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
56 int qlport_down_retry;
57 module_param(qlport_down_retry, int, S_IRUGO);
58 MODULE_PARM_DESC(qlport_down_retry,
59 "Maximum number of command retries to a port that returns "
60 "a PORT-DOWN status.");
61
62 int ql2xplogiabsentdevice;
63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64 MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
66 "a Fabric scan. This is needed for several broken switches. "
67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
69 int ql2xloginretrycount = 0;
70 module_param(ql2xloginretrycount, int, S_IRUGO);
71 MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
74 int ql2xallocfwdump = 1;
75 module_param(ql2xallocfwdump, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
81 int ql2xextended_error_logging;
82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
83 MODULE_PARM_DESC(ql2xextended_error_logging,
84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
99 "\t\tDo LOGICAL OR of the value to enable more than one level");
100
101 int ql2xshiftctondsd = 6;
102 module_param(ql2xshiftctondsd, int, S_IRUGO);
103 MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
107 int ql2xfdmienable=1;
108 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
109 MODULE_PARM_DESC(ql2xfdmienable,
110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
112
113 #define MAX_Q_DEPTH 32
114 static int ql2xmaxqdepth = MAX_Q_DEPTH;
115 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116 MODULE_PARM_DESC(ql2xmaxqdepth,
117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
119
120 int ql2xenabledif = 2;
121 module_param(ql2xenabledif, int, S_IRUGO);
122 MODULE_PARM_DESC(ql2xenabledif,
123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
128
129 int ql2xenablehba_err_chk = 2;
130 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131 MODULE_PARM_DESC(ql2xenablehba_err_chk,
132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
133 " Default is 2.\n"
134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
137
138 int ql2xiidmaenable=1;
139 module_param(ql2xiidmaenable, int, S_IRUGO);
140 MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
144 int ql2xmaxqueues = 1;
145 module_param(ql2xmaxqueues, int, S_IRUGO);
146 MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
150
151 int ql2xmultique_tag;
152 module_param(ql2xmultique_tag, int, S_IRUGO);
153 MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
157
158 int ql2xfwloadbin;
159 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
160 MODULE_PARM_DESC(ql2xfwloadbin,
161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
167 int ql2xetsenable;
168 module_param(ql2xetsenable, int, S_IRUGO);
169 MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
173 int ql2xdbwr = 1;
174 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
175 MODULE_PARM_DESC(ql2xdbwr,
176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
179
180 int ql2xgffidenable;
181 module_param(ql2xgffidenable, int, S_IRUGO);
182 MODULE_PARM_DESC(ql2xgffidenable,
183 "Enables GFF_ID checks of port type. "
184 "Default is 0 - Do not use GFF_ID information.");
185
186 int ql2xasynctmfenable;
187 module_param(ql2xasynctmfenable, int, S_IRUGO);
188 MODULE_PARM_DESC(ql2xasynctmfenable,
189 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
190 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
191
192 int ql2xdontresethba;
193 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
194 MODULE_PARM_DESC(ql2xdontresethba,
195 "Option to specify reset behaviour.\n"
196 " 0 (Default) -- Reset on failure.\n"
197 " 1 -- Do not reset on failure.\n");
198
199 uint64_t ql2xmaxlun = MAX_LUNS;
200 module_param(ql2xmaxlun, ullong, S_IRUGO);
201 MODULE_PARM_DESC(ql2xmaxlun,
202 "Defines the maximum LU number to register with the SCSI "
203 "midlayer. Default is 65535.");
204
205 int ql2xmdcapmask = 0x1F;
206 module_param(ql2xmdcapmask, int, S_IRUGO);
207 MODULE_PARM_DESC(ql2xmdcapmask,
208 "Set the Minidump driver capture mask level. "
209 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
210
211 int ql2xmdenable = 1;
212 module_param(ql2xmdenable, int, S_IRUGO);
213 MODULE_PARM_DESC(ql2xmdenable,
214 "Enable/disable MiniDump. "
215 "0 - MiniDump disabled. "
216 "1 (Default) - MiniDump enabled.");
217
218 /*
219 * SCSI host template entry points
220 */
221 static int qla2xxx_slave_configure(struct scsi_device * device);
222 static int qla2xxx_slave_alloc(struct scsi_device *);
223 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
224 static void qla2xxx_scan_start(struct Scsi_Host *);
225 static void qla2xxx_slave_destroy(struct scsi_device *);
226 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
227 static int qla2xxx_eh_abort(struct scsi_cmnd *);
228 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
229 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
230 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
231 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
232
233 static void qla2x00_clear_drv_active(struct qla_hw_data *);
234 static void qla2x00_free_device(scsi_qla_host_t *);
235 static void qla83xx_disable_laser(scsi_qla_host_t *vha);
236
237 struct scsi_host_template qla2xxx_driver_template = {
238 .module = THIS_MODULE,
239 .name = QLA2XXX_DRIVER_NAME,
240 .queuecommand = qla2xxx_queuecommand,
241
242 .eh_abort_handler = qla2xxx_eh_abort,
243 .eh_device_reset_handler = qla2xxx_eh_device_reset,
244 .eh_target_reset_handler = qla2xxx_eh_target_reset,
245 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
246 .eh_host_reset_handler = qla2xxx_eh_host_reset,
247
248 .slave_configure = qla2xxx_slave_configure,
249
250 .slave_alloc = qla2xxx_slave_alloc,
251 .slave_destroy = qla2xxx_slave_destroy,
252 .scan_finished = qla2xxx_scan_finished,
253 .scan_start = qla2xxx_scan_start,
254 .change_queue_depth = scsi_change_queue_depth,
255 .this_id = -1,
256 .cmd_per_lun = 3,
257 .use_clustering = ENABLE_CLUSTERING,
258 .sg_tablesize = SG_ALL,
259
260 .max_sectors = 0xFFFF,
261 .shost_attrs = qla2x00_host_attrs,
262
263 .supported_mode = MODE_INITIATOR,
264 .track_queue_depth = 1,
265 };
266
267 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
268 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
269
270 /* TODO Convert to inlines
271 *
272 * Timer routines
273 */
274
275 __inline__ void
qla2x00_start_timer(scsi_qla_host_t * vha,void * func,unsigned long interval)276 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
277 {
278 init_timer(&vha->timer);
279 vha->timer.expires = jiffies + interval * HZ;
280 vha->timer.data = (unsigned long)vha;
281 vha->timer.function = (void (*)(unsigned long))func;
282 add_timer(&vha->timer);
283 vha->timer_active = 1;
284 }
285
286 static inline void
qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)287 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
288 {
289 /* Currently used for 82XX only. */
290 if (vha->device_flags & DFLG_DEV_FAILED) {
291 ql_dbg(ql_dbg_timer, vha, 0x600d,
292 "Device in a failed state, returning.\n");
293 return;
294 }
295
296 mod_timer(&vha->timer, jiffies + interval * HZ);
297 }
298
299 static __inline__ void
qla2x00_stop_timer(scsi_qla_host_t * vha)300 qla2x00_stop_timer(scsi_qla_host_t *vha)
301 {
302 del_timer_sync(&vha->timer);
303 vha->timer_active = 0;
304 }
305
306 static int qla2x00_do_dpc(void *data);
307
308 static void qla2x00_rst_aen(scsi_qla_host_t *);
309
310 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
311 struct req_que **, struct rsp_que **);
312 static void qla2x00_free_fw_dump(struct qla_hw_data *);
313 static void qla2x00_mem_free(struct qla_hw_data *);
314
315 /* -------------------------------------------------------------------------- */
qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)316 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
317 struct rsp_que *rsp)
318 {
319 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
320 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
321 GFP_KERNEL);
322 if (!ha->req_q_map) {
323 ql_log(ql_log_fatal, vha, 0x003b,
324 "Unable to allocate memory for request queue ptrs.\n");
325 goto fail_req_map;
326 }
327
328 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
329 GFP_KERNEL);
330 if (!ha->rsp_q_map) {
331 ql_log(ql_log_fatal, vha, 0x003c,
332 "Unable to allocate memory for response queue ptrs.\n");
333 goto fail_rsp_map;
334 }
335 /*
336 * Make sure we record at least the request and response queue zero in
337 * case we need to free them if part of the probe fails.
338 */
339 ha->rsp_q_map[0] = rsp;
340 ha->req_q_map[0] = req;
341 set_bit(0, ha->rsp_qid_map);
342 set_bit(0, ha->req_qid_map);
343 return 1;
344
345 fail_rsp_map:
346 kfree(ha->req_q_map);
347 ha->req_q_map = NULL;
348 fail_req_map:
349 return -ENOMEM;
350 }
351
qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)352 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
353 {
354 if (IS_QLAFX00(ha)) {
355 if (req && req->ring_fx00)
356 dma_free_coherent(&ha->pdev->dev,
357 (req->length_fx00 + 1) * sizeof(request_t),
358 req->ring_fx00, req->dma_fx00);
359 } else if (req && req->ring)
360 dma_free_coherent(&ha->pdev->dev,
361 (req->length + 1) * sizeof(request_t),
362 req->ring, req->dma);
363
364 if (req)
365 kfree(req->outstanding_cmds);
366
367 kfree(req);
368 req = NULL;
369 }
370
qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)371 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
372 {
373 if (IS_QLAFX00(ha)) {
374 if (rsp && rsp->ring)
375 dma_free_coherent(&ha->pdev->dev,
376 (rsp->length_fx00 + 1) * sizeof(request_t),
377 rsp->ring_fx00, rsp->dma_fx00);
378 } else if (rsp && rsp->ring) {
379 dma_free_coherent(&ha->pdev->dev,
380 (rsp->length + 1) * sizeof(response_t),
381 rsp->ring, rsp->dma);
382 }
383 kfree(rsp);
384 rsp = NULL;
385 }
386
qla2x00_free_queues(struct qla_hw_data * ha)387 static void qla2x00_free_queues(struct qla_hw_data *ha)
388 {
389 struct req_que *req;
390 struct rsp_que *rsp;
391 int cnt;
392
393 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
394 if (!test_bit(cnt, ha->req_qid_map))
395 continue;
396
397 req = ha->req_q_map[cnt];
398 qla2x00_free_req_que(ha, req);
399 }
400 kfree(ha->req_q_map);
401 ha->req_q_map = NULL;
402
403 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
404 if (!test_bit(cnt, ha->rsp_qid_map))
405 continue;
406
407 rsp = ha->rsp_q_map[cnt];
408 qla2x00_free_rsp_que(ha, rsp);
409 }
410 kfree(ha->rsp_q_map);
411 ha->rsp_q_map = NULL;
412 }
413
qla25xx_setup_mode(struct scsi_qla_host * vha)414 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
415 {
416 uint16_t options = 0;
417 int ques, req, ret;
418 struct qla_hw_data *ha = vha->hw;
419
420 if (!(ha->fw_attributes & BIT_6)) {
421 ql_log(ql_log_warn, vha, 0x00d8,
422 "Firmware is not multi-queue capable.\n");
423 goto fail;
424 }
425 if (ql2xmultique_tag) {
426 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
427 if (unlikely(!ha->wq)) {
428 ql_log(ql_log_warn, vha, 0x01e0,
429 "Failed to alloc workqueue.\n");
430 goto fail;
431 }
432 /* create a request queue for IO */
433 options |= BIT_7;
434 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
435 QLA_DEFAULT_QUE_QOS);
436 if (!req) {
437 ql_log(ql_log_warn, vha, 0x00e0,
438 "Failed to create request queue.\n");
439 goto fail2;
440 }
441 vha->req = ha->req_q_map[req];
442 options |= BIT_1;
443 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
444 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
445 if (!ret) {
446 ql_log(ql_log_warn, vha, 0x00e8,
447 "Failed to create response queue.\n");
448 goto fail3;
449 }
450 }
451 ha->flags.cpu_affinity_enabled = 1;
452 ql_dbg(ql_dbg_multiq, vha, 0xc007,
453 "CPU affinity mode enabled, "
454 "no. of response queues:%d no. of request queues:%d.\n",
455 ha->max_rsp_queues, ha->max_req_queues);
456 ql_dbg(ql_dbg_init, vha, 0x00e9,
457 "CPU affinity mode enabled, "
458 "no. of response queues:%d no. of request queues:%d.\n",
459 ha->max_rsp_queues, ha->max_req_queues);
460 }
461 return 0;
462
463 fail3:
464 qla25xx_delete_queues(vha);
465 vha->req = ha->req_q_map[0];
466 fail2:
467 destroy_workqueue(ha->wq);
468 ha->wq = NULL;
469 fail:
470 ha->mqenable = 0;
471 kfree(ha->req_q_map);
472 kfree(ha->rsp_q_map);
473 ha->max_req_queues = ha->max_rsp_queues = 1;
474 return 1;
475 }
476
477 static char *
qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str)478 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
479 {
480 struct qla_hw_data *ha = vha->hw;
481 static char *pci_bus_modes[] = {
482 "33", "66", "100", "133",
483 };
484 uint16_t pci_bus;
485
486 strcpy(str, "PCI");
487 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
488 if (pci_bus) {
489 strcat(str, "-X (");
490 strcat(str, pci_bus_modes[pci_bus]);
491 } else {
492 pci_bus = (ha->pci_attr & BIT_8) >> 8;
493 strcat(str, " (");
494 strcat(str, pci_bus_modes[pci_bus]);
495 }
496 strcat(str, " MHz)");
497
498 return (str);
499 }
500
501 static char *
qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str)502 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
503 {
504 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
505 struct qla_hw_data *ha = vha->hw;
506 uint32_t pci_bus;
507
508 if (pci_is_pcie(ha->pdev)) {
509 char lwstr[6];
510 uint32_t lstat, lspeed, lwidth;
511
512 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
513 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
514 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
515
516 strcpy(str, "PCIe (");
517 switch (lspeed) {
518 case 1:
519 strcat(str, "2.5GT/s ");
520 break;
521 case 2:
522 strcat(str, "5.0GT/s ");
523 break;
524 case 3:
525 strcat(str, "8.0GT/s ");
526 break;
527 default:
528 strcat(str, "<unknown> ");
529 break;
530 }
531 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
532 strcat(str, lwstr);
533
534 return str;
535 }
536
537 strcpy(str, "PCI");
538 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
539 if (pci_bus == 0 || pci_bus == 8) {
540 strcat(str, " (");
541 strcat(str, pci_bus_modes[pci_bus >> 3]);
542 } else {
543 strcat(str, "-X ");
544 if (pci_bus & BIT_2)
545 strcat(str, "Mode 2");
546 else
547 strcat(str, "Mode 1");
548 strcat(str, " (");
549 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
550 }
551 strcat(str, " MHz)");
552
553 return str;
554 }
555
556 static char *
qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)557 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
558 {
559 char un_str[10];
560 struct qla_hw_data *ha = vha->hw;
561
562 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
563 ha->fw_minor_version, ha->fw_subminor_version);
564
565 if (ha->fw_attributes & BIT_9) {
566 strcat(str, "FLX");
567 return (str);
568 }
569
570 switch (ha->fw_attributes & 0xFF) {
571 case 0x7:
572 strcat(str, "EF");
573 break;
574 case 0x17:
575 strcat(str, "TP");
576 break;
577 case 0x37:
578 strcat(str, "IP");
579 break;
580 case 0x77:
581 strcat(str, "VI");
582 break;
583 default:
584 sprintf(un_str, "(%x)", ha->fw_attributes);
585 strcat(str, un_str);
586 break;
587 }
588 if (ha->fw_attributes & 0x100)
589 strcat(str, "X");
590
591 return (str);
592 }
593
594 static char *
qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)595 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
596 {
597 struct qla_hw_data *ha = vha->hw;
598
599 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
600 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
601 return str;
602 }
603
604 void
qla2x00_sp_free_dma(void * vha,void * ptr)605 qla2x00_sp_free_dma(void *vha, void *ptr)
606 {
607 srb_t *sp = (srb_t *)ptr;
608 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
609 struct qla_hw_data *ha = sp->fcport->vha->hw;
610 void *ctx = GET_CMD_CTX_SP(sp);
611
612 if (sp->flags & SRB_DMA_VALID) {
613 scsi_dma_unmap(cmd);
614 sp->flags &= ~SRB_DMA_VALID;
615 }
616
617 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
618 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
619 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
620 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
621 }
622
623 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
624 /* List assured to be having elements */
625 qla2x00_clean_dsd_pool(ha, sp, NULL);
626 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
627 }
628
629 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
630 dma_pool_free(ha->dl_dma_pool, ctx,
631 ((struct crc_context *)ctx)->crc_ctx_dma);
632 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
633 }
634
635 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
636 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
637
638 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
639 ctx1->fcp_cmnd_dma);
640 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
641 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
642 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
643 mempool_free(ctx1, ha->ctx_mempool);
644 ctx1 = NULL;
645 }
646
647 CMD_SP(cmd) = NULL;
648 qla2x00_rel_sp(sp->fcport->vha, sp);
649 }
650
651 static void
qla2x00_sp_compl(void * data,void * ptr,int res)652 qla2x00_sp_compl(void *data, void *ptr, int res)
653 {
654 struct qla_hw_data *ha = (struct qla_hw_data *)data;
655 srb_t *sp = (srb_t *)ptr;
656 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
657
658 cmd->result = res;
659
660 if (atomic_read(&sp->ref_count) == 0) {
661 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
662 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
663 sp, GET_CMD_SP(sp));
664 if (ql2xextended_error_logging & ql_dbg_io)
665 WARN_ON(atomic_read(&sp->ref_count) == 0);
666 return;
667 }
668 if (!atomic_dec_and_test(&sp->ref_count))
669 return;
670
671 qla2x00_sp_free_dma(ha, sp);
672 cmd->scsi_done(cmd);
673 }
674
675 /* If we are SP1 here, we need to still take and release the host_lock as SP1
676 * does not have the changes necessary to avoid taking host->host_lock.
677 */
678 static int
qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)679 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
680 {
681 scsi_qla_host_t *vha = shost_priv(host);
682 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
683 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
684 struct qla_hw_data *ha = vha->hw;
685 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
686 srb_t *sp;
687 int rval;
688
689 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
690 cmd->result = DID_NO_CONNECT << 16;
691 goto qc24_fail_command;
692 }
693
694 if (ha->flags.eeh_busy) {
695 if (ha->flags.pci_channel_io_perm_failure) {
696 ql_dbg(ql_dbg_aer, vha, 0x9010,
697 "PCI Channel IO permanent failure, exiting "
698 "cmd=%p.\n", cmd);
699 cmd->result = DID_NO_CONNECT << 16;
700 } else {
701 ql_dbg(ql_dbg_aer, vha, 0x9011,
702 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
703 cmd->result = DID_REQUEUE << 16;
704 }
705 goto qc24_fail_command;
706 }
707
708 rval = fc_remote_port_chkready(rport);
709 if (rval) {
710 cmd->result = rval;
711 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
712 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
713 cmd, rval);
714 goto qc24_fail_command;
715 }
716
717 if (!vha->flags.difdix_supported &&
718 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
719 ql_dbg(ql_dbg_io, vha, 0x3004,
720 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
721 cmd);
722 cmd->result = DID_NO_CONNECT << 16;
723 goto qc24_fail_command;
724 }
725
726 if (!fcport) {
727 cmd->result = DID_NO_CONNECT << 16;
728 goto qc24_fail_command;
729 }
730
731 if (atomic_read(&fcport->state) != FCS_ONLINE) {
732 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
733 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
734 ql_dbg(ql_dbg_io, vha, 0x3005,
735 "Returning DNC, fcport_state=%d loop_state=%d.\n",
736 atomic_read(&fcport->state),
737 atomic_read(&base_vha->loop_state));
738 cmd->result = DID_NO_CONNECT << 16;
739 goto qc24_fail_command;
740 }
741 goto qc24_target_busy;
742 }
743
744 /*
745 * Return target busy if we've received a non-zero retry_delay_timer
746 * in a FCP_RSP.
747 */
748 if (fcport->retry_delay_timestamp == 0) {
749 /* retry delay not set */
750 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
751 fcport->retry_delay_timestamp = 0;
752 else
753 goto qc24_target_busy;
754
755 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
756 if (!sp)
757 goto qc24_host_busy;
758
759 sp->u.scmd.cmd = cmd;
760 sp->type = SRB_SCSI_CMD;
761 atomic_set(&sp->ref_count, 1);
762 CMD_SP(cmd) = (void *)sp;
763 sp->free = qla2x00_sp_free_dma;
764 sp->done = qla2x00_sp_compl;
765
766 rval = ha->isp_ops->start_scsi(sp);
767 if (rval != QLA_SUCCESS) {
768 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
769 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
770 goto qc24_host_busy_free_sp;
771 }
772
773 return 0;
774
775 qc24_host_busy_free_sp:
776 qla2x00_sp_free_dma(ha, sp);
777
778 qc24_host_busy:
779 return SCSI_MLQUEUE_HOST_BUSY;
780
781 qc24_target_busy:
782 return SCSI_MLQUEUE_TARGET_BUSY;
783
784 qc24_fail_command:
785 cmd->scsi_done(cmd);
786
787 return 0;
788 }
789
790 /*
791 * qla2x00_eh_wait_on_command
792 * Waits for the command to be returned by the Firmware for some
793 * max time.
794 *
795 * Input:
796 * cmd = Scsi Command to wait on.
797 *
798 * Return:
799 * Not Found : 0
800 * Found : 1
801 */
802 static int
qla2x00_eh_wait_on_command(struct scsi_cmnd * cmd)803 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
804 {
805 #define ABORT_POLLING_PERIOD 1000
806 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
807 unsigned long wait_iter = ABORT_WAIT_ITER;
808 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
809 struct qla_hw_data *ha = vha->hw;
810 int ret = QLA_SUCCESS;
811
812 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
813 ql_dbg(ql_dbg_taskm, vha, 0x8005,
814 "Return:eh_wait.\n");
815 return ret;
816 }
817
818 while (CMD_SP(cmd) && wait_iter--) {
819 msleep(ABORT_POLLING_PERIOD);
820 }
821 if (CMD_SP(cmd))
822 ret = QLA_FUNCTION_FAILED;
823
824 return ret;
825 }
826
827 /*
828 * qla2x00_wait_for_hba_online
829 * Wait till the HBA is online after going through
830 * <= MAX_RETRIES_OF_ISP_ABORT or
831 * finally HBA is disabled ie marked offline
832 *
833 * Input:
834 * ha - pointer to host adapter structure
835 *
836 * Note:
837 * Does context switching-Release SPIN_LOCK
838 * (if any) before calling this routine.
839 *
840 * Return:
841 * Success (Adapter is online) : 0
842 * Failed (Adapter is offline/disabled) : 1
843 */
844 int
qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)845 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
846 {
847 int return_status;
848 unsigned long wait_online;
849 struct qla_hw_data *ha = vha->hw;
850 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
851
852 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
853 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
854 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
855 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
856 ha->dpc_active) && time_before(jiffies, wait_online)) {
857
858 msleep(1000);
859 }
860 if (base_vha->flags.online)
861 return_status = QLA_SUCCESS;
862 else
863 return_status = QLA_FUNCTION_FAILED;
864
865 return (return_status);
866 }
867
868 /*
869 * qla2x00_wait_for_hba_ready
870 * Wait till the HBA is ready before doing driver unload
871 *
872 * Input:
873 * ha - pointer to host adapter structure
874 *
875 * Note:
876 * Does context switching-Release SPIN_LOCK
877 * (if any) before calling this routine.
878 *
879 */
880 static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)881 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
882 {
883 struct qla_hw_data *ha = vha->hw;
884
885 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
886 ha->flags.mbox_busy) ||
887 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
888 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
889 msleep(1000);
890 }
891
892 int
qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)893 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
894 {
895 int return_status;
896 unsigned long wait_reset;
897 struct qla_hw_data *ha = vha->hw;
898 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
899
900 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
901 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
902 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
903 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
904 ha->dpc_active) && time_before(jiffies, wait_reset)) {
905
906 msleep(1000);
907
908 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
909 ha->flags.chip_reset_done)
910 break;
911 }
912 if (ha->flags.chip_reset_done)
913 return_status = QLA_SUCCESS;
914 else
915 return_status = QLA_FUNCTION_FAILED;
916
917 return return_status;
918 }
919
920 static void
sp_get(struct srb * sp)921 sp_get(struct srb *sp)
922 {
923 atomic_inc(&sp->ref_count);
924 }
925
926 /**************************************************************************
927 * qla2xxx_eh_abort
928 *
929 * Description:
930 * The abort function will abort the specified command.
931 *
932 * Input:
933 * cmd = Linux SCSI command packet to be aborted.
934 *
935 * Returns:
936 * Either SUCCESS or FAILED.
937 *
938 * Note:
939 * Only return FAILED if command not returned by firmware.
940 **************************************************************************/
941 static int
qla2xxx_eh_abort(struct scsi_cmnd * cmd)942 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
943 {
944 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
945 srb_t *sp;
946 int ret;
947 unsigned int id;
948 uint64_t lun;
949 unsigned long flags;
950 int rval, wait = 0;
951 struct qla_hw_data *ha = vha->hw;
952
953 if (!CMD_SP(cmd))
954 return SUCCESS;
955
956 ret = fc_block_scsi_eh(cmd);
957 if (ret != 0)
958 return ret;
959 ret = SUCCESS;
960
961 id = cmd->device->id;
962 lun = cmd->device->lun;
963
964 spin_lock_irqsave(&ha->hardware_lock, flags);
965 sp = (srb_t *) CMD_SP(cmd);
966 if (!sp) {
967 spin_unlock_irqrestore(&ha->hardware_lock, flags);
968 return SUCCESS;
969 }
970
971 ql_dbg(ql_dbg_taskm, vha, 0x8002,
972 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
973 vha->host_no, id, lun, sp, cmd, sp->handle);
974
975 /* Get a reference to the sp and drop the lock.*/
976 sp_get(sp);
977
978 spin_unlock_irqrestore(&ha->hardware_lock, flags);
979 rval = ha->isp_ops->abort_command(sp);
980 if (rval) {
981 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
982 ret = SUCCESS;
983 else
984 ret = FAILED;
985
986 ql_dbg(ql_dbg_taskm, vha, 0x8003,
987 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
988 } else {
989 ql_dbg(ql_dbg_taskm, vha, 0x8004,
990 "Abort command mbx success cmd=%p.\n", cmd);
991 wait = 1;
992 }
993
994 spin_lock_irqsave(&ha->hardware_lock, flags);
995 sp->done(ha, sp, 0);
996 spin_unlock_irqrestore(&ha->hardware_lock, flags);
997
998 /* Did the command return during mailbox execution? */
999 if (ret == FAILED && !CMD_SP(cmd))
1000 ret = SUCCESS;
1001
1002 /* Wait for the command to be returned. */
1003 if (wait) {
1004 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
1005 ql_log(ql_log_warn, vha, 0x8006,
1006 "Abort handler timed out cmd=%p.\n", cmd);
1007 ret = FAILED;
1008 }
1009 }
1010
1011 ql_log(ql_log_info, vha, 0x801c,
1012 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
1013 vha->host_no, id, lun, wait, ret);
1014
1015 return ret;
1016 }
1017
1018 int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1019 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1020 uint64_t l, enum nexus_wait_type type)
1021 {
1022 int cnt, match, status;
1023 unsigned long flags;
1024 struct qla_hw_data *ha = vha->hw;
1025 struct req_que *req;
1026 srb_t *sp;
1027 struct scsi_cmnd *cmd;
1028
1029 status = QLA_SUCCESS;
1030
1031 spin_lock_irqsave(&ha->hardware_lock, flags);
1032 req = vha->req;
1033 for (cnt = 1; status == QLA_SUCCESS &&
1034 cnt < req->num_outstanding_cmds; cnt++) {
1035 sp = req->outstanding_cmds[cnt];
1036 if (!sp)
1037 continue;
1038 if (sp->type != SRB_SCSI_CMD)
1039 continue;
1040 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1041 continue;
1042 match = 0;
1043 cmd = GET_CMD_SP(sp);
1044 switch (type) {
1045 case WAIT_HOST:
1046 match = 1;
1047 break;
1048 case WAIT_TARGET:
1049 match = cmd->device->id == t;
1050 break;
1051 case WAIT_LUN:
1052 match = (cmd->device->id == t &&
1053 cmd->device->lun == l);
1054 break;
1055 }
1056 if (!match)
1057 continue;
1058
1059 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1060 status = qla2x00_eh_wait_on_command(cmd);
1061 spin_lock_irqsave(&ha->hardware_lock, flags);
1062 }
1063 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1064
1065 return status;
1066 }
1067
1068 static char *reset_errors[] = {
1069 "HBA not online",
1070 "HBA not ready",
1071 "Task management failed",
1072 "Waiting for command completions",
1073 };
1074
1075 static int
__qla2xxx_eh_generic_reset(char * name,enum nexus_wait_type type,struct scsi_cmnd * cmd,int (* do_reset)(struct fc_port *,uint64_t,int))1076 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1077 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1078 {
1079 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1080 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1081 int err;
1082
1083 if (!fcport) {
1084 return FAILED;
1085 }
1086
1087 err = fc_block_scsi_eh(cmd);
1088 if (err != 0)
1089 return err;
1090
1091 ql_log(ql_log_info, vha, 0x8009,
1092 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1093 cmd->device->id, cmd->device->lun, cmd);
1094
1095 err = 0;
1096 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1097 ql_log(ql_log_warn, vha, 0x800a,
1098 "Wait for hba online failed for cmd=%p.\n", cmd);
1099 goto eh_reset_failed;
1100 }
1101 err = 2;
1102 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1103 != QLA_SUCCESS) {
1104 ql_log(ql_log_warn, vha, 0x800c,
1105 "do_reset failed for cmd=%p.\n", cmd);
1106 goto eh_reset_failed;
1107 }
1108 err = 3;
1109 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1110 cmd->device->lun, type) != QLA_SUCCESS) {
1111 ql_log(ql_log_warn, vha, 0x800d,
1112 "wait for pending cmds failed for cmd=%p.\n", cmd);
1113 goto eh_reset_failed;
1114 }
1115
1116 ql_log(ql_log_info, vha, 0x800e,
1117 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1118 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1119
1120 return SUCCESS;
1121
1122 eh_reset_failed:
1123 ql_log(ql_log_info, vha, 0x800f,
1124 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1125 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1126 cmd);
1127 return FAILED;
1128 }
1129
1130 static int
qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1131 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1132 {
1133 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1134 struct qla_hw_data *ha = vha->hw;
1135
1136 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1137 ha->isp_ops->lun_reset);
1138 }
1139
1140 static int
qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1141 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1142 {
1143 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1144 struct qla_hw_data *ha = vha->hw;
1145
1146 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1147 ha->isp_ops->target_reset);
1148 }
1149
1150 /**************************************************************************
1151 * qla2xxx_eh_bus_reset
1152 *
1153 * Description:
1154 * The bus reset function will reset the bus and abort any executing
1155 * commands.
1156 *
1157 * Input:
1158 * cmd = Linux SCSI command packet of the command that cause the
1159 * bus reset.
1160 *
1161 * Returns:
1162 * SUCCESS/FAILURE (defined as macro in scsi.h).
1163 *
1164 **************************************************************************/
1165 static int
qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1166 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1167 {
1168 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1169 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1170 int ret = FAILED;
1171 unsigned int id;
1172 uint64_t lun;
1173
1174 id = cmd->device->id;
1175 lun = cmd->device->lun;
1176
1177 if (!fcport) {
1178 return ret;
1179 }
1180
1181 ret = fc_block_scsi_eh(cmd);
1182 if (ret != 0)
1183 return ret;
1184 ret = FAILED;
1185
1186 ql_log(ql_log_info, vha, 0x8012,
1187 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1188
1189 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1190 ql_log(ql_log_fatal, vha, 0x8013,
1191 "Wait for hba online failed board disabled.\n");
1192 goto eh_bus_reset_done;
1193 }
1194
1195 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1196 ret = SUCCESS;
1197
1198 if (ret == FAILED)
1199 goto eh_bus_reset_done;
1200
1201 /* Flush outstanding commands. */
1202 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1203 QLA_SUCCESS) {
1204 ql_log(ql_log_warn, vha, 0x8014,
1205 "Wait for pending commands failed.\n");
1206 ret = FAILED;
1207 }
1208
1209 eh_bus_reset_done:
1210 ql_log(ql_log_warn, vha, 0x802b,
1211 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1212 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1213
1214 return ret;
1215 }
1216
1217 /**************************************************************************
1218 * qla2xxx_eh_host_reset
1219 *
1220 * Description:
1221 * The reset function will reset the Adapter.
1222 *
1223 * Input:
1224 * cmd = Linux SCSI command packet of the command that cause the
1225 * adapter reset.
1226 *
1227 * Returns:
1228 * Either SUCCESS or FAILED.
1229 *
1230 * Note:
1231 **************************************************************************/
1232 static int
qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1233 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1234 {
1235 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1236 struct qla_hw_data *ha = vha->hw;
1237 int ret = FAILED;
1238 unsigned int id;
1239 uint64_t lun;
1240 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1241
1242 id = cmd->device->id;
1243 lun = cmd->device->lun;
1244
1245 ql_log(ql_log_info, vha, 0x8018,
1246 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1247
1248 /*
1249 * No point in issuing another reset if one is active. Also do not
1250 * attempt a reset if we are updating flash.
1251 */
1252 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1253 goto eh_host_reset_lock;
1254
1255 if (vha != base_vha) {
1256 if (qla2x00_vp_abort_isp(vha))
1257 goto eh_host_reset_lock;
1258 } else {
1259 if (IS_P3P_TYPE(vha->hw)) {
1260 if (!qla82xx_fcoe_ctx_reset(vha)) {
1261 /* Ctx reset success */
1262 ret = SUCCESS;
1263 goto eh_host_reset_lock;
1264 }
1265 /* fall thru if ctx reset failed */
1266 }
1267 if (ha->wq)
1268 flush_workqueue(ha->wq);
1269
1270 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1271 if (ha->isp_ops->abort_isp(base_vha)) {
1272 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1273 /* failed. schedule dpc to try */
1274 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1275
1276 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1277 ql_log(ql_log_warn, vha, 0x802a,
1278 "wait for hba online failed.\n");
1279 goto eh_host_reset_lock;
1280 }
1281 }
1282 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1283 }
1284
1285 /* Waiting for command to be returned to OS.*/
1286 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1287 QLA_SUCCESS)
1288 ret = SUCCESS;
1289
1290 eh_host_reset_lock:
1291 ql_log(ql_log_info, vha, 0x8017,
1292 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1293 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1294
1295 return ret;
1296 }
1297
1298 /*
1299 * qla2x00_loop_reset
1300 * Issue loop reset.
1301 *
1302 * Input:
1303 * ha = adapter block pointer.
1304 *
1305 * Returns:
1306 * 0 = success
1307 */
1308 int
qla2x00_loop_reset(scsi_qla_host_t * vha)1309 qla2x00_loop_reset(scsi_qla_host_t *vha)
1310 {
1311 int ret;
1312 struct qla_hw_data *ha = vha->hw;
1313
1314 if (IS_QLAFX00(ha))
1315 return QLA_SUCCESS;
1316
1317 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1318 atomic_set(&vha->loop_state, LOOP_DOWN);
1319 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1320 qla2x00_mark_all_devices_lost(vha, 0);
1321 ret = qla2x00_full_login_lip(vha);
1322 if (ret != QLA_SUCCESS) {
1323 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1324 "full_login_lip=%d.\n", ret);
1325 }
1326 }
1327
1328 if (ha->flags.enable_lip_reset) {
1329 ret = qla2x00_lip_reset(vha);
1330 if (ret != QLA_SUCCESS)
1331 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1332 "lip_reset failed (%d).\n", ret);
1333 }
1334
1335 /* Issue marker command only when we are going to start the I/O */
1336 vha->marker_needed = 1;
1337
1338 return QLA_SUCCESS;
1339 }
1340
1341 void
qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1342 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1343 {
1344 int que, cnt;
1345 unsigned long flags;
1346 srb_t *sp;
1347 struct qla_hw_data *ha = vha->hw;
1348 struct req_que *req;
1349
1350 qlt_host_reset_handler(ha);
1351
1352 spin_lock_irqsave(&ha->hardware_lock, flags);
1353 for (que = 0; que < ha->max_req_queues; que++) {
1354 req = ha->req_q_map[que];
1355 if (!req)
1356 continue;
1357 if (!req->outstanding_cmds)
1358 continue;
1359 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1360 sp = req->outstanding_cmds[cnt];
1361 if (sp) {
1362 req->outstanding_cmds[cnt] = NULL;
1363 sp->done(vha, sp, res);
1364 }
1365 }
1366 }
1367 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1368 }
1369
1370 static int
qla2xxx_slave_alloc(struct scsi_device * sdev)1371 qla2xxx_slave_alloc(struct scsi_device *sdev)
1372 {
1373 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1374
1375 if (!rport || fc_remote_port_chkready(rport))
1376 return -ENXIO;
1377
1378 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1379
1380 return 0;
1381 }
1382
1383 static int
qla2xxx_slave_configure(struct scsi_device * sdev)1384 qla2xxx_slave_configure(struct scsi_device *sdev)
1385 {
1386 scsi_qla_host_t *vha = shost_priv(sdev->host);
1387 struct req_que *req = vha->req;
1388
1389 if (IS_T10_PI_CAPABLE(vha->hw))
1390 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1391
1392 scsi_change_queue_depth(sdev, req->max_q_depth);
1393 return 0;
1394 }
1395
1396 static void
qla2xxx_slave_destroy(struct scsi_device * sdev)1397 qla2xxx_slave_destroy(struct scsi_device *sdev)
1398 {
1399 sdev->hostdata = NULL;
1400 }
1401
1402 /**
1403 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1404 * @ha: HA context
1405 *
1406 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1407 * supported addressing method.
1408 */
1409 static void
qla2x00_config_dma_addressing(struct qla_hw_data * ha)1410 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1411 {
1412 /* Assume a 32bit DMA mask. */
1413 ha->flags.enable_64bit_addressing = 0;
1414
1415 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1416 /* Any upper-dword bits set? */
1417 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1418 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1419 /* Ok, a 64bit DMA mask is applicable. */
1420 ha->flags.enable_64bit_addressing = 1;
1421 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1422 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1423 return;
1424 }
1425 }
1426
1427 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1428 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1429 }
1430
1431 static void
qla2x00_enable_intrs(struct qla_hw_data * ha)1432 qla2x00_enable_intrs(struct qla_hw_data *ha)
1433 {
1434 unsigned long flags = 0;
1435 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1436
1437 spin_lock_irqsave(&ha->hardware_lock, flags);
1438 ha->interrupts_on = 1;
1439 /* enable risc and host interrupts */
1440 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
1441 RD_REG_WORD(®->ictrl);
1442 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1443
1444 }
1445
1446 static void
qla2x00_disable_intrs(struct qla_hw_data * ha)1447 qla2x00_disable_intrs(struct qla_hw_data *ha)
1448 {
1449 unsigned long flags = 0;
1450 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1451
1452 spin_lock_irqsave(&ha->hardware_lock, flags);
1453 ha->interrupts_on = 0;
1454 /* disable risc and host interrupts */
1455 WRT_REG_WORD(®->ictrl, 0);
1456 RD_REG_WORD(®->ictrl);
1457 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1458 }
1459
1460 static void
qla24xx_enable_intrs(struct qla_hw_data * ha)1461 qla24xx_enable_intrs(struct qla_hw_data *ha)
1462 {
1463 unsigned long flags = 0;
1464 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1465
1466 spin_lock_irqsave(&ha->hardware_lock, flags);
1467 ha->interrupts_on = 1;
1468 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT);
1469 RD_REG_DWORD(®->ictrl);
1470 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1471 }
1472
1473 static void
qla24xx_disable_intrs(struct qla_hw_data * ha)1474 qla24xx_disable_intrs(struct qla_hw_data *ha)
1475 {
1476 unsigned long flags = 0;
1477 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1478
1479 if (IS_NOPOLLING_TYPE(ha))
1480 return;
1481 spin_lock_irqsave(&ha->hardware_lock, flags);
1482 ha->interrupts_on = 0;
1483 WRT_REG_DWORD(®->ictrl, 0);
1484 RD_REG_DWORD(®->ictrl);
1485 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1486 }
1487
1488 static int
qla2x00_iospace_config(struct qla_hw_data * ha)1489 qla2x00_iospace_config(struct qla_hw_data *ha)
1490 {
1491 resource_size_t pio;
1492 uint16_t msix;
1493 int cpus;
1494
1495 if (pci_request_selected_regions(ha->pdev, ha->bars,
1496 QLA2XXX_DRIVER_NAME)) {
1497 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1498 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1499 pci_name(ha->pdev));
1500 goto iospace_error_exit;
1501 }
1502 if (!(ha->bars & 1))
1503 goto skip_pio;
1504
1505 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1506 pio = pci_resource_start(ha->pdev, 0);
1507 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1508 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1509 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1510 "Invalid pci I/O region size (%s).\n",
1511 pci_name(ha->pdev));
1512 pio = 0;
1513 }
1514 } else {
1515 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1516 "Region #0 no a PIO resource (%s).\n",
1517 pci_name(ha->pdev));
1518 pio = 0;
1519 }
1520 ha->pio_address = pio;
1521 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1522 "PIO address=%llu.\n",
1523 (unsigned long long)ha->pio_address);
1524
1525 skip_pio:
1526 /* Use MMIO operations for all accesses. */
1527 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1528 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1529 "Region #1 not an MMIO resource (%s), aborting.\n",
1530 pci_name(ha->pdev));
1531 goto iospace_error_exit;
1532 }
1533 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1534 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1535 "Invalid PCI mem region size (%s), aborting.\n",
1536 pci_name(ha->pdev));
1537 goto iospace_error_exit;
1538 }
1539
1540 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1541 if (!ha->iobase) {
1542 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1543 "Cannot remap MMIO (%s), aborting.\n",
1544 pci_name(ha->pdev));
1545 goto iospace_error_exit;
1546 }
1547
1548 /* Determine queue resources */
1549 ha->max_req_queues = ha->max_rsp_queues = 1;
1550 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1551 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1552 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1553 goto mqiobase_exit;
1554
1555 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1556 pci_resource_len(ha->pdev, 3));
1557 if (ha->mqiobase) {
1558 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1559 "MQIO Base=%p.\n", ha->mqiobase);
1560 /* Read MSIX vector size of the board */
1561 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1562 ha->msix_count = msix;
1563 /* Max queues are bounded by available msix vectors */
1564 /* queue 0 uses two msix vectors */
1565 if (ql2xmultique_tag) {
1566 cpus = num_online_cpus();
1567 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1568 (cpus + 1) : (ha->msix_count - 1);
1569 ha->max_req_queues = 2;
1570 } else if (ql2xmaxqueues > 1) {
1571 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1572 QLA_MQ_SIZE : ql2xmaxqueues;
1573 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1574 "QoS mode set, max no of request queues:%d.\n",
1575 ha->max_req_queues);
1576 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1577 "QoS mode set, max no of request queues:%d.\n",
1578 ha->max_req_queues);
1579 }
1580 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1581 "MSI-X vector count: %d.\n", msix);
1582 } else
1583 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1584 "BAR 3 not enabled.\n");
1585
1586 mqiobase_exit:
1587 ha->msix_count = ha->max_rsp_queues + 1;
1588 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1589 "MSIX Count:%d.\n", ha->msix_count);
1590 return (0);
1591
1592 iospace_error_exit:
1593 return (-ENOMEM);
1594 }
1595
1596
1597 static int
qla83xx_iospace_config(struct qla_hw_data * ha)1598 qla83xx_iospace_config(struct qla_hw_data *ha)
1599 {
1600 uint16_t msix;
1601 int cpus;
1602
1603 if (pci_request_selected_regions(ha->pdev, ha->bars,
1604 QLA2XXX_DRIVER_NAME)) {
1605 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1606 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1607 pci_name(ha->pdev));
1608
1609 goto iospace_error_exit;
1610 }
1611
1612 /* Use MMIO operations for all accesses. */
1613 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1614 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1615 "Invalid pci I/O region size (%s).\n",
1616 pci_name(ha->pdev));
1617 goto iospace_error_exit;
1618 }
1619 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1620 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1621 "Invalid PCI mem region size (%s), aborting\n",
1622 pci_name(ha->pdev));
1623 goto iospace_error_exit;
1624 }
1625
1626 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1627 if (!ha->iobase) {
1628 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1629 "Cannot remap MMIO (%s), aborting.\n",
1630 pci_name(ha->pdev));
1631 goto iospace_error_exit;
1632 }
1633
1634 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1635 /* 83XX 26XX always use MQ type access for queues
1636 * - mbar 2, a.k.a region 4 */
1637 ha->max_req_queues = ha->max_rsp_queues = 1;
1638 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1639 pci_resource_len(ha->pdev, 4));
1640
1641 if (!ha->mqiobase) {
1642 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1643 "BAR2/region4 not enabled\n");
1644 goto mqiobase_exit;
1645 }
1646
1647 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1648 pci_resource_len(ha->pdev, 2));
1649 if (ha->msixbase) {
1650 /* Read MSIX vector size of the board */
1651 pci_read_config_word(ha->pdev,
1652 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1653 ha->msix_count = msix;
1654 /* Max queues are bounded by available msix vectors */
1655 /* queue 0 uses two msix vectors */
1656 if (ql2xmultique_tag) {
1657 cpus = num_online_cpus();
1658 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1659 (cpus + 1) : (ha->msix_count - 1);
1660 ha->max_req_queues = 2;
1661 } else if (ql2xmaxqueues > 1) {
1662 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1663 QLA_MQ_SIZE : ql2xmaxqueues;
1664 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1665 "QoS mode set, max no of request queues:%d.\n",
1666 ha->max_req_queues);
1667 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1668 "QoS mode set, max no of request queues:%d.\n",
1669 ha->max_req_queues);
1670 }
1671 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1672 "MSI-X vector count: %d.\n", msix);
1673 } else
1674 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1675 "BAR 1 not enabled.\n");
1676
1677 mqiobase_exit:
1678 ha->msix_count = ha->max_rsp_queues + 1;
1679
1680 qlt_83xx_iospace_config(ha);
1681
1682 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1683 "MSIX Count:%d.\n", ha->msix_count);
1684 return 0;
1685
1686 iospace_error_exit:
1687 return -ENOMEM;
1688 }
1689
1690 static struct isp_operations qla2100_isp_ops = {
1691 .pci_config = qla2100_pci_config,
1692 .reset_chip = qla2x00_reset_chip,
1693 .chip_diag = qla2x00_chip_diag,
1694 .config_rings = qla2x00_config_rings,
1695 .reset_adapter = qla2x00_reset_adapter,
1696 .nvram_config = qla2x00_nvram_config,
1697 .update_fw_options = qla2x00_update_fw_options,
1698 .load_risc = qla2x00_load_risc,
1699 .pci_info_str = qla2x00_pci_info_str,
1700 .fw_version_str = qla2x00_fw_version_str,
1701 .intr_handler = qla2100_intr_handler,
1702 .enable_intrs = qla2x00_enable_intrs,
1703 .disable_intrs = qla2x00_disable_intrs,
1704 .abort_command = qla2x00_abort_command,
1705 .target_reset = qla2x00_abort_target,
1706 .lun_reset = qla2x00_lun_reset,
1707 .fabric_login = qla2x00_login_fabric,
1708 .fabric_logout = qla2x00_fabric_logout,
1709 .calc_req_entries = qla2x00_calc_iocbs_32,
1710 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1711 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1712 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1713 .read_nvram = qla2x00_read_nvram_data,
1714 .write_nvram = qla2x00_write_nvram_data,
1715 .fw_dump = qla2100_fw_dump,
1716 .beacon_on = NULL,
1717 .beacon_off = NULL,
1718 .beacon_blink = NULL,
1719 .read_optrom = qla2x00_read_optrom_data,
1720 .write_optrom = qla2x00_write_optrom_data,
1721 .get_flash_version = qla2x00_get_flash_version,
1722 .start_scsi = qla2x00_start_scsi,
1723 .abort_isp = qla2x00_abort_isp,
1724 .iospace_config = qla2x00_iospace_config,
1725 .initialize_adapter = qla2x00_initialize_adapter,
1726 };
1727
1728 static struct isp_operations qla2300_isp_ops = {
1729 .pci_config = qla2300_pci_config,
1730 .reset_chip = qla2x00_reset_chip,
1731 .chip_diag = qla2x00_chip_diag,
1732 .config_rings = qla2x00_config_rings,
1733 .reset_adapter = qla2x00_reset_adapter,
1734 .nvram_config = qla2x00_nvram_config,
1735 .update_fw_options = qla2x00_update_fw_options,
1736 .load_risc = qla2x00_load_risc,
1737 .pci_info_str = qla2x00_pci_info_str,
1738 .fw_version_str = qla2x00_fw_version_str,
1739 .intr_handler = qla2300_intr_handler,
1740 .enable_intrs = qla2x00_enable_intrs,
1741 .disable_intrs = qla2x00_disable_intrs,
1742 .abort_command = qla2x00_abort_command,
1743 .target_reset = qla2x00_abort_target,
1744 .lun_reset = qla2x00_lun_reset,
1745 .fabric_login = qla2x00_login_fabric,
1746 .fabric_logout = qla2x00_fabric_logout,
1747 .calc_req_entries = qla2x00_calc_iocbs_32,
1748 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1749 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1750 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1751 .read_nvram = qla2x00_read_nvram_data,
1752 .write_nvram = qla2x00_write_nvram_data,
1753 .fw_dump = qla2300_fw_dump,
1754 .beacon_on = qla2x00_beacon_on,
1755 .beacon_off = qla2x00_beacon_off,
1756 .beacon_blink = qla2x00_beacon_blink,
1757 .read_optrom = qla2x00_read_optrom_data,
1758 .write_optrom = qla2x00_write_optrom_data,
1759 .get_flash_version = qla2x00_get_flash_version,
1760 .start_scsi = qla2x00_start_scsi,
1761 .abort_isp = qla2x00_abort_isp,
1762 .iospace_config = qla2x00_iospace_config,
1763 .initialize_adapter = qla2x00_initialize_adapter,
1764 };
1765
1766 static struct isp_operations qla24xx_isp_ops = {
1767 .pci_config = qla24xx_pci_config,
1768 .reset_chip = qla24xx_reset_chip,
1769 .chip_diag = qla24xx_chip_diag,
1770 .config_rings = qla24xx_config_rings,
1771 .reset_adapter = qla24xx_reset_adapter,
1772 .nvram_config = qla24xx_nvram_config,
1773 .update_fw_options = qla24xx_update_fw_options,
1774 .load_risc = qla24xx_load_risc,
1775 .pci_info_str = qla24xx_pci_info_str,
1776 .fw_version_str = qla24xx_fw_version_str,
1777 .intr_handler = qla24xx_intr_handler,
1778 .enable_intrs = qla24xx_enable_intrs,
1779 .disable_intrs = qla24xx_disable_intrs,
1780 .abort_command = qla24xx_abort_command,
1781 .target_reset = qla24xx_abort_target,
1782 .lun_reset = qla24xx_lun_reset,
1783 .fabric_login = qla24xx_login_fabric,
1784 .fabric_logout = qla24xx_fabric_logout,
1785 .calc_req_entries = NULL,
1786 .build_iocbs = NULL,
1787 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1788 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1789 .read_nvram = qla24xx_read_nvram_data,
1790 .write_nvram = qla24xx_write_nvram_data,
1791 .fw_dump = qla24xx_fw_dump,
1792 .beacon_on = qla24xx_beacon_on,
1793 .beacon_off = qla24xx_beacon_off,
1794 .beacon_blink = qla24xx_beacon_blink,
1795 .read_optrom = qla24xx_read_optrom_data,
1796 .write_optrom = qla24xx_write_optrom_data,
1797 .get_flash_version = qla24xx_get_flash_version,
1798 .start_scsi = qla24xx_start_scsi,
1799 .abort_isp = qla2x00_abort_isp,
1800 .iospace_config = qla2x00_iospace_config,
1801 .initialize_adapter = qla2x00_initialize_adapter,
1802 };
1803
1804 static struct isp_operations qla25xx_isp_ops = {
1805 .pci_config = qla25xx_pci_config,
1806 .reset_chip = qla24xx_reset_chip,
1807 .chip_diag = qla24xx_chip_diag,
1808 .config_rings = qla24xx_config_rings,
1809 .reset_adapter = qla24xx_reset_adapter,
1810 .nvram_config = qla24xx_nvram_config,
1811 .update_fw_options = qla24xx_update_fw_options,
1812 .load_risc = qla24xx_load_risc,
1813 .pci_info_str = qla24xx_pci_info_str,
1814 .fw_version_str = qla24xx_fw_version_str,
1815 .intr_handler = qla24xx_intr_handler,
1816 .enable_intrs = qla24xx_enable_intrs,
1817 .disable_intrs = qla24xx_disable_intrs,
1818 .abort_command = qla24xx_abort_command,
1819 .target_reset = qla24xx_abort_target,
1820 .lun_reset = qla24xx_lun_reset,
1821 .fabric_login = qla24xx_login_fabric,
1822 .fabric_logout = qla24xx_fabric_logout,
1823 .calc_req_entries = NULL,
1824 .build_iocbs = NULL,
1825 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1826 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1827 .read_nvram = qla25xx_read_nvram_data,
1828 .write_nvram = qla25xx_write_nvram_data,
1829 .fw_dump = qla25xx_fw_dump,
1830 .beacon_on = qla24xx_beacon_on,
1831 .beacon_off = qla24xx_beacon_off,
1832 .beacon_blink = qla24xx_beacon_blink,
1833 .read_optrom = qla25xx_read_optrom_data,
1834 .write_optrom = qla24xx_write_optrom_data,
1835 .get_flash_version = qla24xx_get_flash_version,
1836 .start_scsi = qla24xx_dif_start_scsi,
1837 .abort_isp = qla2x00_abort_isp,
1838 .iospace_config = qla2x00_iospace_config,
1839 .initialize_adapter = qla2x00_initialize_adapter,
1840 };
1841
1842 static struct isp_operations qla81xx_isp_ops = {
1843 .pci_config = qla25xx_pci_config,
1844 .reset_chip = qla24xx_reset_chip,
1845 .chip_diag = qla24xx_chip_diag,
1846 .config_rings = qla24xx_config_rings,
1847 .reset_adapter = qla24xx_reset_adapter,
1848 .nvram_config = qla81xx_nvram_config,
1849 .update_fw_options = qla81xx_update_fw_options,
1850 .load_risc = qla81xx_load_risc,
1851 .pci_info_str = qla24xx_pci_info_str,
1852 .fw_version_str = qla24xx_fw_version_str,
1853 .intr_handler = qla24xx_intr_handler,
1854 .enable_intrs = qla24xx_enable_intrs,
1855 .disable_intrs = qla24xx_disable_intrs,
1856 .abort_command = qla24xx_abort_command,
1857 .target_reset = qla24xx_abort_target,
1858 .lun_reset = qla24xx_lun_reset,
1859 .fabric_login = qla24xx_login_fabric,
1860 .fabric_logout = qla24xx_fabric_logout,
1861 .calc_req_entries = NULL,
1862 .build_iocbs = NULL,
1863 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1864 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1865 .read_nvram = NULL,
1866 .write_nvram = NULL,
1867 .fw_dump = qla81xx_fw_dump,
1868 .beacon_on = qla24xx_beacon_on,
1869 .beacon_off = qla24xx_beacon_off,
1870 .beacon_blink = qla83xx_beacon_blink,
1871 .read_optrom = qla25xx_read_optrom_data,
1872 .write_optrom = qla24xx_write_optrom_data,
1873 .get_flash_version = qla24xx_get_flash_version,
1874 .start_scsi = qla24xx_dif_start_scsi,
1875 .abort_isp = qla2x00_abort_isp,
1876 .iospace_config = qla2x00_iospace_config,
1877 .initialize_adapter = qla2x00_initialize_adapter,
1878 };
1879
1880 static struct isp_operations qla82xx_isp_ops = {
1881 .pci_config = qla82xx_pci_config,
1882 .reset_chip = qla82xx_reset_chip,
1883 .chip_diag = qla24xx_chip_diag,
1884 .config_rings = qla82xx_config_rings,
1885 .reset_adapter = qla24xx_reset_adapter,
1886 .nvram_config = qla81xx_nvram_config,
1887 .update_fw_options = qla24xx_update_fw_options,
1888 .load_risc = qla82xx_load_risc,
1889 .pci_info_str = qla24xx_pci_info_str,
1890 .fw_version_str = qla24xx_fw_version_str,
1891 .intr_handler = qla82xx_intr_handler,
1892 .enable_intrs = qla82xx_enable_intrs,
1893 .disable_intrs = qla82xx_disable_intrs,
1894 .abort_command = qla24xx_abort_command,
1895 .target_reset = qla24xx_abort_target,
1896 .lun_reset = qla24xx_lun_reset,
1897 .fabric_login = qla24xx_login_fabric,
1898 .fabric_logout = qla24xx_fabric_logout,
1899 .calc_req_entries = NULL,
1900 .build_iocbs = NULL,
1901 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1902 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1903 .read_nvram = qla24xx_read_nvram_data,
1904 .write_nvram = qla24xx_write_nvram_data,
1905 .fw_dump = qla82xx_fw_dump,
1906 .beacon_on = qla82xx_beacon_on,
1907 .beacon_off = qla82xx_beacon_off,
1908 .beacon_blink = NULL,
1909 .read_optrom = qla82xx_read_optrom_data,
1910 .write_optrom = qla82xx_write_optrom_data,
1911 .get_flash_version = qla82xx_get_flash_version,
1912 .start_scsi = qla82xx_start_scsi,
1913 .abort_isp = qla82xx_abort_isp,
1914 .iospace_config = qla82xx_iospace_config,
1915 .initialize_adapter = qla2x00_initialize_adapter,
1916 };
1917
1918 static struct isp_operations qla8044_isp_ops = {
1919 .pci_config = qla82xx_pci_config,
1920 .reset_chip = qla82xx_reset_chip,
1921 .chip_diag = qla24xx_chip_diag,
1922 .config_rings = qla82xx_config_rings,
1923 .reset_adapter = qla24xx_reset_adapter,
1924 .nvram_config = qla81xx_nvram_config,
1925 .update_fw_options = qla24xx_update_fw_options,
1926 .load_risc = qla82xx_load_risc,
1927 .pci_info_str = qla24xx_pci_info_str,
1928 .fw_version_str = qla24xx_fw_version_str,
1929 .intr_handler = qla8044_intr_handler,
1930 .enable_intrs = qla82xx_enable_intrs,
1931 .disable_intrs = qla82xx_disable_intrs,
1932 .abort_command = qla24xx_abort_command,
1933 .target_reset = qla24xx_abort_target,
1934 .lun_reset = qla24xx_lun_reset,
1935 .fabric_login = qla24xx_login_fabric,
1936 .fabric_logout = qla24xx_fabric_logout,
1937 .calc_req_entries = NULL,
1938 .build_iocbs = NULL,
1939 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1940 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1941 .read_nvram = NULL,
1942 .write_nvram = NULL,
1943 .fw_dump = qla8044_fw_dump,
1944 .beacon_on = qla82xx_beacon_on,
1945 .beacon_off = qla82xx_beacon_off,
1946 .beacon_blink = NULL,
1947 .read_optrom = qla8044_read_optrom_data,
1948 .write_optrom = qla8044_write_optrom_data,
1949 .get_flash_version = qla82xx_get_flash_version,
1950 .start_scsi = qla82xx_start_scsi,
1951 .abort_isp = qla8044_abort_isp,
1952 .iospace_config = qla82xx_iospace_config,
1953 .initialize_adapter = qla2x00_initialize_adapter,
1954 };
1955
1956 static struct isp_operations qla83xx_isp_ops = {
1957 .pci_config = qla25xx_pci_config,
1958 .reset_chip = qla24xx_reset_chip,
1959 .chip_diag = qla24xx_chip_diag,
1960 .config_rings = qla24xx_config_rings,
1961 .reset_adapter = qla24xx_reset_adapter,
1962 .nvram_config = qla81xx_nvram_config,
1963 .update_fw_options = qla81xx_update_fw_options,
1964 .load_risc = qla81xx_load_risc,
1965 .pci_info_str = qla24xx_pci_info_str,
1966 .fw_version_str = qla24xx_fw_version_str,
1967 .intr_handler = qla24xx_intr_handler,
1968 .enable_intrs = qla24xx_enable_intrs,
1969 .disable_intrs = qla24xx_disable_intrs,
1970 .abort_command = qla24xx_abort_command,
1971 .target_reset = qla24xx_abort_target,
1972 .lun_reset = qla24xx_lun_reset,
1973 .fabric_login = qla24xx_login_fabric,
1974 .fabric_logout = qla24xx_fabric_logout,
1975 .calc_req_entries = NULL,
1976 .build_iocbs = NULL,
1977 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1978 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1979 .read_nvram = NULL,
1980 .write_nvram = NULL,
1981 .fw_dump = qla83xx_fw_dump,
1982 .beacon_on = qla24xx_beacon_on,
1983 .beacon_off = qla24xx_beacon_off,
1984 .beacon_blink = qla83xx_beacon_blink,
1985 .read_optrom = qla25xx_read_optrom_data,
1986 .write_optrom = qla24xx_write_optrom_data,
1987 .get_flash_version = qla24xx_get_flash_version,
1988 .start_scsi = qla24xx_dif_start_scsi,
1989 .abort_isp = qla2x00_abort_isp,
1990 .iospace_config = qla83xx_iospace_config,
1991 .initialize_adapter = qla2x00_initialize_adapter,
1992 };
1993
1994 static struct isp_operations qlafx00_isp_ops = {
1995 .pci_config = qlafx00_pci_config,
1996 .reset_chip = qlafx00_soft_reset,
1997 .chip_diag = qlafx00_chip_diag,
1998 .config_rings = qlafx00_config_rings,
1999 .reset_adapter = qlafx00_soft_reset,
2000 .nvram_config = NULL,
2001 .update_fw_options = NULL,
2002 .load_risc = NULL,
2003 .pci_info_str = qlafx00_pci_info_str,
2004 .fw_version_str = qlafx00_fw_version_str,
2005 .intr_handler = qlafx00_intr_handler,
2006 .enable_intrs = qlafx00_enable_intrs,
2007 .disable_intrs = qlafx00_disable_intrs,
2008 .abort_command = qla24xx_async_abort_command,
2009 .target_reset = qlafx00_abort_target,
2010 .lun_reset = qlafx00_lun_reset,
2011 .fabric_login = NULL,
2012 .fabric_logout = NULL,
2013 .calc_req_entries = NULL,
2014 .build_iocbs = NULL,
2015 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2016 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2017 .read_nvram = qla24xx_read_nvram_data,
2018 .write_nvram = qla24xx_write_nvram_data,
2019 .fw_dump = NULL,
2020 .beacon_on = qla24xx_beacon_on,
2021 .beacon_off = qla24xx_beacon_off,
2022 .beacon_blink = NULL,
2023 .read_optrom = qla24xx_read_optrom_data,
2024 .write_optrom = qla24xx_write_optrom_data,
2025 .get_flash_version = qla24xx_get_flash_version,
2026 .start_scsi = qlafx00_start_scsi,
2027 .abort_isp = qlafx00_abort_isp,
2028 .iospace_config = qlafx00_iospace_config,
2029 .initialize_adapter = qlafx00_initialize_adapter,
2030 };
2031
2032 static struct isp_operations qla27xx_isp_ops = {
2033 .pci_config = qla25xx_pci_config,
2034 .reset_chip = qla24xx_reset_chip,
2035 .chip_diag = qla24xx_chip_diag,
2036 .config_rings = qla24xx_config_rings,
2037 .reset_adapter = qla24xx_reset_adapter,
2038 .nvram_config = qla81xx_nvram_config,
2039 .update_fw_options = qla81xx_update_fw_options,
2040 .load_risc = qla81xx_load_risc,
2041 .pci_info_str = qla24xx_pci_info_str,
2042 .fw_version_str = qla24xx_fw_version_str,
2043 .intr_handler = qla24xx_intr_handler,
2044 .enable_intrs = qla24xx_enable_intrs,
2045 .disable_intrs = qla24xx_disable_intrs,
2046 .abort_command = qla24xx_abort_command,
2047 .target_reset = qla24xx_abort_target,
2048 .lun_reset = qla24xx_lun_reset,
2049 .fabric_login = qla24xx_login_fabric,
2050 .fabric_logout = qla24xx_fabric_logout,
2051 .calc_req_entries = NULL,
2052 .build_iocbs = NULL,
2053 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2054 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2055 .read_nvram = NULL,
2056 .write_nvram = NULL,
2057 .fw_dump = qla27xx_fwdump,
2058 .beacon_on = qla24xx_beacon_on,
2059 .beacon_off = qla24xx_beacon_off,
2060 .beacon_blink = qla83xx_beacon_blink,
2061 .read_optrom = qla25xx_read_optrom_data,
2062 .write_optrom = qla24xx_write_optrom_data,
2063 .get_flash_version = qla24xx_get_flash_version,
2064 .start_scsi = qla24xx_dif_start_scsi,
2065 .abort_isp = qla2x00_abort_isp,
2066 .iospace_config = qla83xx_iospace_config,
2067 .initialize_adapter = qla2x00_initialize_adapter,
2068 };
2069
2070 static inline void
qla2x00_set_isp_flags(struct qla_hw_data * ha)2071 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2072 {
2073 ha->device_type = DT_EXTENDED_IDS;
2074 switch (ha->pdev->device) {
2075 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2076 ha->device_type |= DT_ISP2100;
2077 ha->device_type &= ~DT_EXTENDED_IDS;
2078 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2079 break;
2080 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2081 ha->device_type |= DT_ISP2200;
2082 ha->device_type &= ~DT_EXTENDED_IDS;
2083 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2084 break;
2085 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2086 ha->device_type |= DT_ISP2300;
2087 ha->device_type |= DT_ZIO_SUPPORTED;
2088 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2089 break;
2090 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2091 ha->device_type |= DT_ISP2312;
2092 ha->device_type |= DT_ZIO_SUPPORTED;
2093 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2094 break;
2095 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2096 ha->device_type |= DT_ISP2322;
2097 ha->device_type |= DT_ZIO_SUPPORTED;
2098 if (ha->pdev->subsystem_vendor == 0x1028 &&
2099 ha->pdev->subsystem_device == 0x0170)
2100 ha->device_type |= DT_OEM_001;
2101 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2102 break;
2103 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2104 ha->device_type |= DT_ISP6312;
2105 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2106 break;
2107 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2108 ha->device_type |= DT_ISP6322;
2109 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2110 break;
2111 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2112 ha->device_type |= DT_ISP2422;
2113 ha->device_type |= DT_ZIO_SUPPORTED;
2114 ha->device_type |= DT_FWI2;
2115 ha->device_type |= DT_IIDMA;
2116 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2117 break;
2118 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2119 ha->device_type |= DT_ISP2432;
2120 ha->device_type |= DT_ZIO_SUPPORTED;
2121 ha->device_type |= DT_FWI2;
2122 ha->device_type |= DT_IIDMA;
2123 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2124 break;
2125 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2126 ha->device_type |= DT_ISP8432;
2127 ha->device_type |= DT_ZIO_SUPPORTED;
2128 ha->device_type |= DT_FWI2;
2129 ha->device_type |= DT_IIDMA;
2130 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2131 break;
2132 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2133 ha->device_type |= DT_ISP5422;
2134 ha->device_type |= DT_FWI2;
2135 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2136 break;
2137 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2138 ha->device_type |= DT_ISP5432;
2139 ha->device_type |= DT_FWI2;
2140 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2141 break;
2142 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2143 ha->device_type |= DT_ISP2532;
2144 ha->device_type |= DT_ZIO_SUPPORTED;
2145 ha->device_type |= DT_FWI2;
2146 ha->device_type |= DT_IIDMA;
2147 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2148 break;
2149 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2150 ha->device_type |= DT_ISP8001;
2151 ha->device_type |= DT_ZIO_SUPPORTED;
2152 ha->device_type |= DT_FWI2;
2153 ha->device_type |= DT_IIDMA;
2154 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2155 break;
2156 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2157 ha->device_type |= DT_ISP8021;
2158 ha->device_type |= DT_ZIO_SUPPORTED;
2159 ha->device_type |= DT_FWI2;
2160 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2161 /* Initialize 82XX ISP flags */
2162 qla82xx_init_flags(ha);
2163 break;
2164 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2165 ha->device_type |= DT_ISP8044;
2166 ha->device_type |= DT_ZIO_SUPPORTED;
2167 ha->device_type |= DT_FWI2;
2168 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2169 /* Initialize 82XX ISP flags */
2170 qla82xx_init_flags(ha);
2171 break;
2172 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2173 ha->device_type |= DT_ISP2031;
2174 ha->device_type |= DT_ZIO_SUPPORTED;
2175 ha->device_type |= DT_FWI2;
2176 ha->device_type |= DT_IIDMA;
2177 ha->device_type |= DT_T10_PI;
2178 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2179 break;
2180 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2181 ha->device_type |= DT_ISP8031;
2182 ha->device_type |= DT_ZIO_SUPPORTED;
2183 ha->device_type |= DT_FWI2;
2184 ha->device_type |= DT_IIDMA;
2185 ha->device_type |= DT_T10_PI;
2186 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2187 break;
2188 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2189 ha->device_type |= DT_ISPFX00;
2190 break;
2191 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2192 ha->device_type |= DT_ISP2071;
2193 ha->device_type |= DT_ZIO_SUPPORTED;
2194 ha->device_type |= DT_FWI2;
2195 ha->device_type |= DT_IIDMA;
2196 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2197 break;
2198 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2199 ha->device_type |= DT_ISP2271;
2200 ha->device_type |= DT_ZIO_SUPPORTED;
2201 ha->device_type |= DT_FWI2;
2202 ha->device_type |= DT_IIDMA;
2203 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2204 break;
2205 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2206 ha->device_type |= DT_ISP2261;
2207 ha->device_type |= DT_ZIO_SUPPORTED;
2208 ha->device_type |= DT_FWI2;
2209 ha->device_type |= DT_IIDMA;
2210 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2211 break;
2212 }
2213
2214 if (IS_QLA82XX(ha))
2215 ha->port_no = ha->portnum & 1;
2216 else {
2217 /* Get adapter physical port no from interrupt pin register. */
2218 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2219 if (IS_QLA27XX(ha))
2220 ha->port_no--;
2221 else
2222 ha->port_no = !(ha->port_no & 1);
2223 }
2224
2225 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2226 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2227 ha->device_type, ha->port_no, ha->fw_srisc_address);
2228 }
2229
2230 static void
qla2xxx_scan_start(struct Scsi_Host * shost)2231 qla2xxx_scan_start(struct Scsi_Host *shost)
2232 {
2233 scsi_qla_host_t *vha = shost_priv(shost);
2234
2235 if (vha->hw->flags.running_gold_fw)
2236 return;
2237
2238 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2239 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2240 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2241 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2242 }
2243
2244 static int
qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2245 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2246 {
2247 scsi_qla_host_t *vha = shost_priv(shost);
2248
2249 if (test_bit(UNLOADING, &vha->dpc_flags))
2250 return 1;
2251 if (!vha->host)
2252 return 1;
2253 if (time > vha->hw->loop_reset_delay * HZ)
2254 return 1;
2255
2256 return atomic_read(&vha->loop_state) == LOOP_READY;
2257 }
2258
2259 /*
2260 * PCI driver interface
2261 */
2262 static int
qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2263 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2264 {
2265 int ret = -ENODEV;
2266 struct Scsi_Host *host;
2267 scsi_qla_host_t *base_vha = NULL;
2268 struct qla_hw_data *ha;
2269 char pci_info[30];
2270 char fw_str[30], wq_name[30];
2271 struct scsi_host_template *sht;
2272 int bars, mem_only = 0;
2273 uint16_t req_length = 0, rsp_length = 0;
2274 struct req_que *req = NULL;
2275 struct rsp_que *rsp = NULL;
2276 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2277 sht = &qla2xxx_driver_template;
2278 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2279 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2280 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2281 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2282 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2283 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2284 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2285 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2286 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2287 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2288 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2289 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2290 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2291 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2292 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
2293 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2294 mem_only = 1;
2295 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2296 "Mem only adapter.\n");
2297 }
2298 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2299 "Bars=%d.\n", bars);
2300
2301 if (mem_only) {
2302 if (pci_enable_device_mem(pdev))
2303 return ret;
2304 } else {
2305 if (pci_enable_device(pdev))
2306 return ret;
2307 }
2308
2309 /* This may fail but that's ok */
2310 pci_enable_pcie_error_reporting(pdev);
2311
2312 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2313 if (!ha) {
2314 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2315 "Unable to allocate memory for ha.\n");
2316 goto disable_device;
2317 }
2318 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2319 "Memory allocated for ha=%p.\n", ha);
2320 ha->pdev = pdev;
2321 ha->tgt.enable_class_2 = ql2xenableclass2;
2322 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2323 spin_lock_init(&ha->tgt.q_full_lock);
2324
2325 /* Clear our data area */
2326 ha->bars = bars;
2327 ha->mem_only = mem_only;
2328 spin_lock_init(&ha->hardware_lock);
2329 spin_lock_init(&ha->vport_slock);
2330 mutex_init(&ha->selflogin_lock);
2331 mutex_init(&ha->optrom_mutex);
2332
2333 /* Set ISP-type information. */
2334 qla2x00_set_isp_flags(ha);
2335
2336 /* Set EEH reset type to fundamental if required by hba */
2337 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2338 IS_QLA83XX(ha) || IS_QLA27XX(ha))
2339 pdev->needs_freset = 1;
2340
2341 ha->prev_topology = 0;
2342 ha->init_cb_size = sizeof(init_cb_t);
2343 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2344 ha->optrom_size = OPTROM_SIZE_2300;
2345
2346 /* Assign ISP specific operations. */
2347 if (IS_QLA2100(ha)) {
2348 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2349 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2350 req_length = REQUEST_ENTRY_CNT_2100;
2351 rsp_length = RESPONSE_ENTRY_CNT_2100;
2352 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2353 ha->gid_list_info_size = 4;
2354 ha->flash_conf_off = ~0;
2355 ha->flash_data_off = ~0;
2356 ha->nvram_conf_off = ~0;
2357 ha->nvram_data_off = ~0;
2358 ha->isp_ops = &qla2100_isp_ops;
2359 } else if (IS_QLA2200(ha)) {
2360 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2361 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2362 req_length = REQUEST_ENTRY_CNT_2200;
2363 rsp_length = RESPONSE_ENTRY_CNT_2100;
2364 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2365 ha->gid_list_info_size = 4;
2366 ha->flash_conf_off = ~0;
2367 ha->flash_data_off = ~0;
2368 ha->nvram_conf_off = ~0;
2369 ha->nvram_data_off = ~0;
2370 ha->isp_ops = &qla2100_isp_ops;
2371 } else if (IS_QLA23XX(ha)) {
2372 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2373 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2374 req_length = REQUEST_ENTRY_CNT_2200;
2375 rsp_length = RESPONSE_ENTRY_CNT_2300;
2376 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2377 ha->gid_list_info_size = 6;
2378 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2379 ha->optrom_size = OPTROM_SIZE_2322;
2380 ha->flash_conf_off = ~0;
2381 ha->flash_data_off = ~0;
2382 ha->nvram_conf_off = ~0;
2383 ha->nvram_data_off = ~0;
2384 ha->isp_ops = &qla2300_isp_ops;
2385 } else if (IS_QLA24XX_TYPE(ha)) {
2386 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2387 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2388 req_length = REQUEST_ENTRY_CNT_24XX;
2389 rsp_length = RESPONSE_ENTRY_CNT_2300;
2390 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2391 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2392 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2393 ha->gid_list_info_size = 8;
2394 ha->optrom_size = OPTROM_SIZE_24XX;
2395 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2396 ha->isp_ops = &qla24xx_isp_ops;
2397 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2398 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2399 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2400 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2401 } else if (IS_QLA25XX(ha)) {
2402 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2403 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2404 req_length = REQUEST_ENTRY_CNT_24XX;
2405 rsp_length = RESPONSE_ENTRY_CNT_2300;
2406 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2407 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2408 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2409 ha->gid_list_info_size = 8;
2410 ha->optrom_size = OPTROM_SIZE_25XX;
2411 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2412 ha->isp_ops = &qla25xx_isp_ops;
2413 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2414 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2415 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2416 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2417 } else if (IS_QLA81XX(ha)) {
2418 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2419 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2420 req_length = REQUEST_ENTRY_CNT_24XX;
2421 rsp_length = RESPONSE_ENTRY_CNT_2300;
2422 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2423 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2424 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2425 ha->gid_list_info_size = 8;
2426 ha->optrom_size = OPTROM_SIZE_81XX;
2427 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2428 ha->isp_ops = &qla81xx_isp_ops;
2429 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2430 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2431 ha->nvram_conf_off = ~0;
2432 ha->nvram_data_off = ~0;
2433 } else if (IS_QLA82XX(ha)) {
2434 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2435 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2436 req_length = REQUEST_ENTRY_CNT_82XX;
2437 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2438 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2439 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2440 ha->gid_list_info_size = 8;
2441 ha->optrom_size = OPTROM_SIZE_82XX;
2442 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2443 ha->isp_ops = &qla82xx_isp_ops;
2444 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2445 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2446 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2447 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2448 } else if (IS_QLA8044(ha)) {
2449 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2450 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2451 req_length = REQUEST_ENTRY_CNT_82XX;
2452 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2453 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2454 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2455 ha->gid_list_info_size = 8;
2456 ha->optrom_size = OPTROM_SIZE_83XX;
2457 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2458 ha->isp_ops = &qla8044_isp_ops;
2459 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2460 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2461 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2462 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2463 } else if (IS_QLA83XX(ha)) {
2464 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2465 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2466 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2467 req_length = REQUEST_ENTRY_CNT_83XX;
2468 rsp_length = RESPONSE_ENTRY_CNT_2300;
2469 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2470 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2471 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2472 ha->gid_list_info_size = 8;
2473 ha->optrom_size = OPTROM_SIZE_83XX;
2474 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2475 ha->isp_ops = &qla83xx_isp_ops;
2476 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2477 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2478 ha->nvram_conf_off = ~0;
2479 ha->nvram_data_off = ~0;
2480 } else if (IS_QLAFX00(ha)) {
2481 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2482 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2483 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2484 req_length = REQUEST_ENTRY_CNT_FX00;
2485 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2486 ha->isp_ops = &qlafx00_isp_ops;
2487 ha->port_down_retry_count = 30; /* default value */
2488 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2489 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2490 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2491 ha->mr.fw_hbt_en = 1;
2492 ha->mr.host_info_resend = false;
2493 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
2494 } else if (IS_QLA27XX(ha)) {
2495 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2496 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2497 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2498 req_length = REQUEST_ENTRY_CNT_24XX;
2499 rsp_length = RESPONSE_ENTRY_CNT_2300;
2500 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2501 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2502 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2503 ha->gid_list_info_size = 8;
2504 ha->optrom_size = OPTROM_SIZE_83XX;
2505 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2506 ha->isp_ops = &qla27xx_isp_ops;
2507 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2508 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2509 ha->nvram_conf_off = ~0;
2510 ha->nvram_data_off = ~0;
2511 }
2512
2513 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2514 "mbx_count=%d, req_length=%d, "
2515 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2516 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2517 "max_fibre_devices=%d.\n",
2518 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2519 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2520 ha->nvram_npiv_size, ha->max_fibre_devices);
2521 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2522 "isp_ops=%p, flash_conf_off=%d, "
2523 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2524 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2525 ha->nvram_conf_off, ha->nvram_data_off);
2526
2527 /* Configure PCI I/O space */
2528 ret = ha->isp_ops->iospace_config(ha);
2529 if (ret)
2530 goto iospace_config_failed;
2531
2532 ql_log_pci(ql_log_info, pdev, 0x001d,
2533 "Found an ISP%04X irq %d iobase 0x%p.\n",
2534 pdev->device, pdev->irq, ha->iobase);
2535 mutex_init(&ha->vport_lock);
2536 init_completion(&ha->mbx_cmd_comp);
2537 complete(&ha->mbx_cmd_comp);
2538 init_completion(&ha->mbx_intr_comp);
2539 init_completion(&ha->dcbx_comp);
2540 init_completion(&ha->lb_portup_comp);
2541
2542 set_bit(0, (unsigned long *) ha->vp_idx_map);
2543
2544 qla2x00_config_dma_addressing(ha);
2545 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2546 "64 Bit addressing is %s.\n",
2547 ha->flags.enable_64bit_addressing ? "enable" :
2548 "disable");
2549 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2550 if (ret) {
2551 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2552 "Failed to allocate memory for adapter, aborting.\n");
2553
2554 goto probe_hw_failed;
2555 }
2556
2557 req->max_q_depth = MAX_Q_DEPTH;
2558 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2559 req->max_q_depth = ql2xmaxqdepth;
2560
2561
2562 base_vha = qla2x00_create_host(sht, ha);
2563 if (!base_vha) {
2564 ret = -ENOMEM;
2565 qla2x00_mem_free(ha);
2566 qla2x00_free_req_que(ha, req);
2567 qla2x00_free_rsp_que(ha, rsp);
2568 goto probe_hw_failed;
2569 }
2570
2571 pci_set_drvdata(pdev, base_vha);
2572 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2573
2574 host = base_vha->host;
2575 base_vha->req = req;
2576 if (IS_QLA2XXX_MIDTYPE(ha))
2577 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2578 else
2579 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2580 base_vha->vp_idx;
2581
2582 /* Setup fcport template structure. */
2583 ha->mr.fcport.vha = base_vha;
2584 ha->mr.fcport.port_type = FCT_UNKNOWN;
2585 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2586 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2587 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2588 ha->mr.fcport.scan_state = 1;
2589
2590 /* Set the SG table size based on ISP type */
2591 if (!IS_FWI2_CAPABLE(ha)) {
2592 if (IS_QLA2100(ha))
2593 host->sg_tablesize = 32;
2594 } else {
2595 if (!IS_QLA82XX(ha))
2596 host->sg_tablesize = QLA_SG_ALL;
2597 }
2598 host->max_id = ha->max_fibre_devices;
2599 host->cmd_per_lun = 3;
2600 host->unique_id = host->host_no;
2601 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2602 host->max_cmd_len = 32;
2603 else
2604 host->max_cmd_len = MAX_CMDSZ;
2605 host->max_channel = MAX_BUSES - 1;
2606 /* Older HBAs support only 16-bit LUNs */
2607 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2608 ql2xmaxlun > 0xffff)
2609 host->max_lun = 0xffff;
2610 else
2611 host->max_lun = ql2xmaxlun;
2612 host->transportt = qla2xxx_transport_template;
2613 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2614
2615 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2616 "max_id=%d this_id=%d "
2617 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2618 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
2619 host->this_id, host->cmd_per_lun, host->unique_id,
2620 host->max_cmd_len, host->max_channel, host->max_lun,
2621 host->transportt, sht->vendor_id);
2622
2623 que_init:
2624 /* Alloc arrays of request and response ring ptrs */
2625 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2626 ql_log(ql_log_fatal, base_vha, 0x003d,
2627 "Failed to allocate memory for queue pointers..."
2628 "aborting.\n");
2629 goto probe_init_failed;
2630 }
2631
2632 qlt_probe_one_stage1(base_vha, ha);
2633
2634 /* Set up the irqs */
2635 ret = qla2x00_request_irqs(ha, rsp);
2636 if (ret)
2637 goto probe_init_failed;
2638
2639 pci_save_state(pdev);
2640
2641 /* Assign back pointers */
2642 rsp->req = req;
2643 req->rsp = rsp;
2644
2645 if (IS_QLAFX00(ha)) {
2646 ha->rsp_q_map[0] = rsp;
2647 ha->req_q_map[0] = req;
2648 set_bit(0, ha->req_qid_map);
2649 set_bit(0, ha->rsp_qid_map);
2650 }
2651
2652 /* FWI2-capable only. */
2653 req->req_q_in = &ha->iobase->isp24.req_q_in;
2654 req->req_q_out = &ha->iobase->isp24.req_q_out;
2655 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2656 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2657 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
2658 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2659 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2660 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2661 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
2662 }
2663
2664 if (IS_QLAFX00(ha)) {
2665 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2666 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2667 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2668 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2669 }
2670
2671 if (IS_P3P_TYPE(ha)) {
2672 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2673 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2674 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2675 }
2676
2677 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2678 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2679 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2680 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2681 "req->req_q_in=%p req->req_q_out=%p "
2682 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2683 req->req_q_in, req->req_q_out,
2684 rsp->rsp_q_in, rsp->rsp_q_out);
2685 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2686 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2687 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2688 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2689 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2690 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2691
2692 if (ha->isp_ops->initialize_adapter(base_vha)) {
2693 ql_log(ql_log_fatal, base_vha, 0x00d6,
2694 "Failed to initialize adapter - Adapter flags %x.\n",
2695 base_vha->device_flags);
2696
2697 if (IS_QLA82XX(ha)) {
2698 qla82xx_idc_lock(ha);
2699 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2700 QLA8XXX_DEV_FAILED);
2701 qla82xx_idc_unlock(ha);
2702 ql_log(ql_log_fatal, base_vha, 0x00d7,
2703 "HW State: FAILED.\n");
2704 } else if (IS_QLA8044(ha)) {
2705 qla8044_idc_lock(ha);
2706 qla8044_wr_direct(base_vha,
2707 QLA8044_CRB_DEV_STATE_INDEX,
2708 QLA8XXX_DEV_FAILED);
2709 qla8044_idc_unlock(ha);
2710 ql_log(ql_log_fatal, base_vha, 0x0150,
2711 "HW State: FAILED.\n");
2712 }
2713
2714 ret = -ENODEV;
2715 goto probe_failed;
2716 }
2717
2718 if (IS_QLAFX00(ha))
2719 host->can_queue = QLAFX00_MAX_CANQUEUE;
2720 else
2721 host->can_queue = req->num_outstanding_cmds - 10;
2722
2723 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2724 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2725 host->can_queue, base_vha->req,
2726 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2727
2728 if (ha->mqenable) {
2729 if (qla25xx_setup_mode(base_vha)) {
2730 ql_log(ql_log_warn, base_vha, 0x00ec,
2731 "Failed to create queues, falling back to single queue mode.\n");
2732 goto que_init;
2733 }
2734 }
2735
2736 if (ha->flags.running_gold_fw)
2737 goto skip_dpc;
2738
2739 /*
2740 * Startup the kernel thread for this host adapter
2741 */
2742 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2743 "%s_dpc", base_vha->host_str);
2744 if (IS_ERR(ha->dpc_thread)) {
2745 ql_log(ql_log_fatal, base_vha, 0x00ed,
2746 "Failed to start DPC thread.\n");
2747 ret = PTR_ERR(ha->dpc_thread);
2748 goto probe_failed;
2749 }
2750 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2751 "DPC thread started successfully.\n");
2752
2753 /*
2754 * If we're not coming up in initiator mode, we might sit for
2755 * a while without waking up the dpc thread, which leads to a
2756 * stuck process warning. So just kick the dpc once here and
2757 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2758 */
2759 qla2xxx_wake_dpc(base_vha);
2760
2761 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2762
2763 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2764 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2765 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2766 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2767
2768 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2769 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2770 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2771 INIT_WORK(&ha->idc_state_handler,
2772 qla83xx_idc_state_handler_work);
2773 INIT_WORK(&ha->nic_core_unrecoverable,
2774 qla83xx_nic_core_unrecoverable_work);
2775 }
2776
2777 skip_dpc:
2778 list_add_tail(&base_vha->list, &ha->vp_list);
2779 base_vha->host->irq = ha->pdev->irq;
2780
2781 /* Initialized the timer */
2782 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2783 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2784 "Started qla2x00_timer with "
2785 "interval=%d.\n", WATCH_INTERVAL);
2786 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2787 "Detected hba at address=%p.\n",
2788 ha);
2789
2790 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2791 if (ha->fw_attributes & BIT_4) {
2792 int prot = 0, guard;
2793 base_vha->flags.difdix_supported = 1;
2794 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2795 "Registering for DIF/DIX type 1 and 3 protection.\n");
2796 if (ql2xenabledif == 1)
2797 prot = SHOST_DIX_TYPE0_PROTECTION;
2798 scsi_host_set_prot(host,
2799 prot | SHOST_DIF_TYPE1_PROTECTION
2800 | SHOST_DIF_TYPE2_PROTECTION
2801 | SHOST_DIF_TYPE3_PROTECTION
2802 | SHOST_DIX_TYPE1_PROTECTION
2803 | SHOST_DIX_TYPE2_PROTECTION
2804 | SHOST_DIX_TYPE3_PROTECTION);
2805
2806 guard = SHOST_DIX_GUARD_CRC;
2807
2808 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2809 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2810 guard |= SHOST_DIX_GUARD_IP;
2811
2812 scsi_host_set_guard(host, guard);
2813 } else
2814 base_vha->flags.difdix_supported = 0;
2815 }
2816
2817 ha->isp_ops->enable_intrs(ha);
2818
2819 if (IS_QLAFX00(ha)) {
2820 ret = qlafx00_fx_disc(base_vha,
2821 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2822 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2823 QLA_SG_ALL : 128;
2824 }
2825
2826 ret = scsi_add_host(host, &pdev->dev);
2827 if (ret)
2828 goto probe_failed;
2829
2830 base_vha->flags.init_done = 1;
2831 base_vha->flags.online = 1;
2832 ha->prev_minidump_failed = 0;
2833
2834 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2835 "Init done and hba is online.\n");
2836
2837 if (qla_ini_mode_enabled(base_vha))
2838 scsi_scan_host(host);
2839 else
2840 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2841 "skipping scsi_scan_host() for non-initiator port\n");
2842
2843 qla2x00_alloc_sysfs_attr(base_vha);
2844
2845 if (IS_QLAFX00(ha)) {
2846 ret = qlafx00_fx_disc(base_vha,
2847 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2848
2849 /* Register system information */
2850 ret = qlafx00_fx_disc(base_vha,
2851 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2852 }
2853
2854 qla2x00_init_host_attr(base_vha);
2855
2856 qla2x00_dfs_setup(base_vha);
2857
2858 ql_log(ql_log_info, base_vha, 0x00fb,
2859 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
2860 ql_log(ql_log_info, base_vha, 0x00fc,
2861 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2862 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2863 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2864 base_vha->host_no,
2865 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
2866
2867 qlt_add_target(ha, base_vha);
2868
2869 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2870 return 0;
2871
2872 probe_init_failed:
2873 qla2x00_free_req_que(ha, req);
2874 ha->req_q_map[0] = NULL;
2875 clear_bit(0, ha->req_qid_map);
2876 qla2x00_free_rsp_que(ha, rsp);
2877 ha->rsp_q_map[0] = NULL;
2878 clear_bit(0, ha->rsp_qid_map);
2879 ha->max_req_queues = ha->max_rsp_queues = 0;
2880
2881 probe_failed:
2882 if (base_vha->timer_active)
2883 qla2x00_stop_timer(base_vha);
2884 base_vha->flags.online = 0;
2885 if (ha->dpc_thread) {
2886 struct task_struct *t = ha->dpc_thread;
2887
2888 ha->dpc_thread = NULL;
2889 kthread_stop(t);
2890 }
2891
2892 qla2x00_free_device(base_vha);
2893
2894 scsi_host_put(base_vha->host);
2895
2896 probe_hw_failed:
2897 qla2x00_clear_drv_active(ha);
2898
2899 iospace_config_failed:
2900 if (IS_P3P_TYPE(ha)) {
2901 if (!ha->nx_pcibase)
2902 iounmap((device_reg_t *)ha->nx_pcibase);
2903 if (!ql2xdbwr)
2904 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
2905 } else {
2906 if (ha->iobase)
2907 iounmap(ha->iobase);
2908 if (ha->cregbase)
2909 iounmap(ha->cregbase);
2910 }
2911 pci_release_selected_regions(ha->pdev, ha->bars);
2912 kfree(ha);
2913 ha = NULL;
2914
2915 disable_device:
2916 pci_disable_device(pdev);
2917 return ret;
2918 }
2919
2920 static void
qla2x00_shutdown(struct pci_dev * pdev)2921 qla2x00_shutdown(struct pci_dev *pdev)
2922 {
2923 scsi_qla_host_t *vha;
2924 struct qla_hw_data *ha;
2925
2926 if (!atomic_read(&pdev->enable_cnt))
2927 return;
2928
2929 vha = pci_get_drvdata(pdev);
2930 ha = vha->hw;
2931
2932 /* Notify ISPFX00 firmware */
2933 if (IS_QLAFX00(ha))
2934 qlafx00_driver_shutdown(vha, 20);
2935
2936 /* Turn-off FCE trace */
2937 if (ha->flags.fce_enabled) {
2938 qla2x00_disable_fce_trace(vha, NULL, NULL);
2939 ha->flags.fce_enabled = 0;
2940 }
2941
2942 /* Turn-off EFT trace */
2943 if (ha->eft)
2944 qla2x00_disable_eft_trace(vha);
2945
2946 /* Stop currently executing firmware. */
2947 qla2x00_try_to_stop_firmware(vha);
2948
2949 /* Disable timer */
2950 if (vha->timer_active)
2951 qla2x00_stop_timer(vha);
2952
2953 /* Turn adapter off line */
2954 vha->flags.online = 0;
2955
2956 /* turn-off interrupts on the card */
2957 if (ha->interrupts_on) {
2958 vha->flags.init_done = 0;
2959 ha->isp_ops->disable_intrs(ha);
2960 }
2961
2962 qla2x00_free_irqs(vha);
2963
2964 qla2x00_free_fw_dump(ha);
2965
2966 pci_disable_pcie_error_reporting(pdev);
2967 pci_disable_device(pdev);
2968 }
2969
2970 /* Deletes all the virtual ports for a given ha */
2971 static void
qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)2972 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
2973 {
2974 scsi_qla_host_t *vha;
2975 unsigned long flags;
2976
2977 mutex_lock(&ha->vport_lock);
2978 while (ha->cur_vport_count) {
2979 spin_lock_irqsave(&ha->vport_slock, flags);
2980
2981 BUG_ON(base_vha->list.next == &ha->vp_list);
2982 /* This assumes first entry in ha->vp_list is always base vha */
2983 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2984 scsi_host_get(vha->host);
2985
2986 spin_unlock_irqrestore(&ha->vport_slock, flags);
2987 mutex_unlock(&ha->vport_lock);
2988
2989 fc_vport_terminate(vha->fc_vport);
2990 scsi_host_put(vha->host);
2991
2992 mutex_lock(&ha->vport_lock);
2993 }
2994 mutex_unlock(&ha->vport_lock);
2995 }
2996
2997 /* Stops all deferred work threads */
2998 static void
qla2x00_destroy_deferred_work(struct qla_hw_data * ha)2999 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3000 {
3001 /* Flush the work queue and remove it */
3002 if (ha->wq) {
3003 flush_workqueue(ha->wq);
3004 destroy_workqueue(ha->wq);
3005 ha->wq = NULL;
3006 }
3007
3008 /* Cancel all work and destroy DPC workqueues */
3009 if (ha->dpc_lp_wq) {
3010 cancel_work_sync(&ha->idc_aen);
3011 destroy_workqueue(ha->dpc_lp_wq);
3012 ha->dpc_lp_wq = NULL;
3013 }
3014
3015 if (ha->dpc_hp_wq) {
3016 cancel_work_sync(&ha->nic_core_reset);
3017 cancel_work_sync(&ha->idc_state_handler);
3018 cancel_work_sync(&ha->nic_core_unrecoverable);
3019 destroy_workqueue(ha->dpc_hp_wq);
3020 ha->dpc_hp_wq = NULL;
3021 }
3022
3023 /* Kill the kernel thread for this host */
3024 if (ha->dpc_thread) {
3025 struct task_struct *t = ha->dpc_thread;
3026
3027 /*
3028 * qla2xxx_wake_dpc checks for ->dpc_thread
3029 * so we need to zero it out.
3030 */
3031 ha->dpc_thread = NULL;
3032 kthread_stop(t);
3033 }
3034 }
3035
3036 static void
qla2x00_unmap_iobases(struct qla_hw_data * ha)3037 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3038 {
3039 if (IS_QLA82XX(ha)) {
3040
3041 iounmap((device_reg_t *)ha->nx_pcibase);
3042 if (!ql2xdbwr)
3043 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3044 } else {
3045 if (ha->iobase)
3046 iounmap(ha->iobase);
3047
3048 if (ha->cregbase)
3049 iounmap(ha->cregbase);
3050
3051 if (ha->mqiobase)
3052 iounmap(ha->mqiobase);
3053
3054 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
3055 iounmap(ha->msixbase);
3056 }
3057 }
3058
3059 static void
qla2x00_clear_drv_active(struct qla_hw_data * ha)3060 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3061 {
3062 if (IS_QLA8044(ha)) {
3063 qla8044_idc_lock(ha);
3064 qla8044_clear_drv_active(ha);
3065 qla8044_idc_unlock(ha);
3066 } else if (IS_QLA82XX(ha)) {
3067 qla82xx_idc_lock(ha);
3068 qla82xx_clear_drv_active(ha);
3069 qla82xx_idc_unlock(ha);
3070 }
3071 }
3072
3073 static void
qla2x00_remove_one(struct pci_dev * pdev)3074 qla2x00_remove_one(struct pci_dev *pdev)
3075 {
3076 scsi_qla_host_t *base_vha;
3077 struct qla_hw_data *ha;
3078
3079 base_vha = pci_get_drvdata(pdev);
3080 ha = base_vha->hw;
3081
3082 /* Indicate device removal to prevent future board_disable and wait
3083 * until any pending board_disable has completed. */
3084 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3085 cancel_work_sync(&ha->board_disable);
3086
3087 /*
3088 * If the PCI device is disabled then there was a PCI-disconnect and
3089 * qla2x00_disable_board_on_pci_error has taken care of most of the
3090 * resources.
3091 */
3092 if (!atomic_read(&pdev->enable_cnt)) {
3093 scsi_host_put(base_vha->host);
3094 kfree(ha);
3095 pci_set_drvdata(pdev, NULL);
3096 return;
3097 }
3098
3099 qla2x00_wait_for_hba_ready(base_vha);
3100
3101 set_bit(UNLOADING, &base_vha->dpc_flags);
3102
3103 if (IS_QLAFX00(ha))
3104 qlafx00_driver_shutdown(base_vha, 20);
3105
3106 qla2x00_delete_all_vps(ha, base_vha);
3107
3108 if (IS_QLA8031(ha)) {
3109 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3110 "Clearing fcoe driver presence.\n");
3111 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3112 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3113 "Error while clearing DRV-Presence.\n");
3114 }
3115
3116 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3117
3118 qla2x00_dfs_remove(base_vha);
3119
3120 qla84xx_put_chip(base_vha);
3121
3122 /* Laser should be disabled only for ISP2031 */
3123 if (IS_QLA2031(ha))
3124 qla83xx_disable_laser(base_vha);
3125
3126 /* Disable timer */
3127 if (base_vha->timer_active)
3128 qla2x00_stop_timer(base_vha);
3129
3130 base_vha->flags.online = 0;
3131
3132 qla2x00_destroy_deferred_work(ha);
3133
3134 qlt_remove_target(ha, base_vha);
3135
3136 qla2x00_free_sysfs_attr(base_vha, true);
3137
3138 fc_remove_host(base_vha->host);
3139
3140 scsi_remove_host(base_vha->host);
3141
3142 qla2x00_free_device(base_vha);
3143
3144 qla2x00_clear_drv_active(ha);
3145
3146 scsi_host_put(base_vha->host);
3147
3148 qla2x00_unmap_iobases(ha);
3149
3150 pci_release_selected_regions(ha->pdev, ha->bars);
3151 kfree(ha);
3152 ha = NULL;
3153
3154 pci_disable_pcie_error_reporting(pdev);
3155
3156 pci_disable_device(pdev);
3157 }
3158
3159 static void
qla2x00_free_device(scsi_qla_host_t * vha)3160 qla2x00_free_device(scsi_qla_host_t *vha)
3161 {
3162 struct qla_hw_data *ha = vha->hw;
3163
3164 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3165
3166 /* Disable timer */
3167 if (vha->timer_active)
3168 qla2x00_stop_timer(vha);
3169
3170 qla25xx_delete_queues(vha);
3171
3172 if (ha->flags.fce_enabled)
3173 qla2x00_disable_fce_trace(vha, NULL, NULL);
3174
3175 if (ha->eft)
3176 qla2x00_disable_eft_trace(vha);
3177
3178 /* Stop currently executing firmware. */
3179 qla2x00_try_to_stop_firmware(vha);
3180
3181 vha->flags.online = 0;
3182
3183 /* turn-off interrupts on the card */
3184 if (ha->interrupts_on) {
3185 vha->flags.init_done = 0;
3186 ha->isp_ops->disable_intrs(ha);
3187 }
3188
3189 qla2x00_free_irqs(vha);
3190
3191 qla2x00_free_fcports(vha);
3192
3193 qla2x00_mem_free(ha);
3194
3195 qla82xx_md_free(vha);
3196
3197 qla2x00_free_queues(ha);
3198 }
3199
qla2x00_free_fcports(struct scsi_qla_host * vha)3200 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3201 {
3202 fc_port_t *fcport, *tfcport;
3203
3204 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3205 list_del(&fcport->list);
3206 qla2x00_clear_loop_id(fcport);
3207 kfree(fcport);
3208 fcport = NULL;
3209 }
3210 }
3211
3212 static inline void
qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport,int defer)3213 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3214 int defer)
3215 {
3216 struct fc_rport *rport;
3217 scsi_qla_host_t *base_vha;
3218 unsigned long flags;
3219
3220 if (!fcport->rport)
3221 return;
3222
3223 rport = fcport->rport;
3224 if (defer) {
3225 base_vha = pci_get_drvdata(vha->hw->pdev);
3226 spin_lock_irqsave(vha->host->host_lock, flags);
3227 fcport->drport = rport;
3228 spin_unlock_irqrestore(vha->host->host_lock, flags);
3229 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
3230 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3231 qla2xxx_wake_dpc(base_vha);
3232 } else {
3233 int now;
3234 if (rport)
3235 fc_remote_port_delete(rport);
3236 qlt_do_generation_tick(vha, &now);
3237 qlt_fc_port_deleted(vha, fcport, now);
3238 }
3239 }
3240
3241 /*
3242 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3243 *
3244 * Input: ha = adapter block pointer. fcport = port structure pointer.
3245 *
3246 * Return: None.
3247 *
3248 * Context:
3249 */
qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login,int defer)3250 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3251 int do_login, int defer)
3252 {
3253 if (IS_QLAFX00(vha->hw)) {
3254 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3255 qla2x00_schedule_rport_del(vha, fcport, defer);
3256 return;
3257 }
3258
3259 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3260 vha->vp_idx == fcport->vha->vp_idx) {
3261 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3262 qla2x00_schedule_rport_del(vha, fcport, defer);
3263 }
3264 /*
3265 * We may need to retry the login, so don't change the state of the
3266 * port but do the retries.
3267 */
3268 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3269 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3270
3271 if (!do_login)
3272 return;
3273
3274 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3275
3276 if (fcport->login_retry == 0) {
3277 fcport->login_retry = vha->hw->login_retry_count;
3278
3279 ql_dbg(ql_dbg_disc, vha, 0x2067,
3280 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3281 fcport->port_name, fcport->loop_id, fcport->login_retry);
3282 }
3283 }
3284
3285 /*
3286 * qla2x00_mark_all_devices_lost
3287 * Updates fcport state when device goes offline.
3288 *
3289 * Input:
3290 * ha = adapter block pointer.
3291 * fcport = port structure pointer.
3292 *
3293 * Return:
3294 * None.
3295 *
3296 * Context:
3297 */
3298 void
qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha,int defer)3299 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3300 {
3301 fc_port_t *fcport;
3302
3303 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3304 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3305 continue;
3306
3307 /*
3308 * No point in marking the device as lost, if the device is
3309 * already DEAD.
3310 */
3311 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3312 continue;
3313 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3314 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3315 if (defer)
3316 qla2x00_schedule_rport_del(vha, fcport, defer);
3317 else if (vha->vp_idx == fcport->vha->vp_idx)
3318 qla2x00_schedule_rport_del(vha, fcport, defer);
3319 }
3320 }
3321 }
3322
3323 /*
3324 * qla2x00_mem_alloc
3325 * Allocates adapter memory.
3326 *
3327 * Returns:
3328 * 0 = success.
3329 * !0 = failure.
3330 */
3331 static int
qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)3332 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3333 struct req_que **req, struct rsp_que **rsp)
3334 {
3335 char name[16];
3336
3337 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3338 &ha->init_cb_dma, GFP_KERNEL);
3339 if (!ha->init_cb)
3340 goto fail;
3341
3342 if (qlt_mem_alloc(ha) < 0)
3343 goto fail_free_init_cb;
3344
3345 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3346 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3347 if (!ha->gid_list)
3348 goto fail_free_tgt_mem;
3349
3350 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3351 if (!ha->srb_mempool)
3352 goto fail_free_gid_list;
3353
3354 if (IS_P3P_TYPE(ha)) {
3355 /* Allocate cache for CT6 Ctx. */
3356 if (!ctx_cachep) {
3357 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3358 sizeof(struct ct6_dsd), 0,
3359 SLAB_HWCACHE_ALIGN, NULL);
3360 if (!ctx_cachep)
3361 goto fail_free_srb_mempool;
3362 }
3363 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3364 ctx_cachep);
3365 if (!ha->ctx_mempool)
3366 goto fail_free_srb_mempool;
3367 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3368 "ctx_cachep=%p ctx_mempool=%p.\n",
3369 ctx_cachep, ha->ctx_mempool);
3370 }
3371
3372 /* Get memory for cached NVRAM */
3373 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3374 if (!ha->nvram)
3375 goto fail_free_ctx_mempool;
3376
3377 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3378 ha->pdev->device);
3379 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3380 DMA_POOL_SIZE, 8, 0);
3381 if (!ha->s_dma_pool)
3382 goto fail_free_nvram;
3383
3384 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3385 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3386 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3387
3388 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3389 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3390 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3391 if (!ha->dl_dma_pool) {
3392 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3393 "Failed to allocate memory for dl_dma_pool.\n");
3394 goto fail_s_dma_pool;
3395 }
3396
3397 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3398 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3399 if (!ha->fcp_cmnd_dma_pool) {
3400 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3401 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3402 goto fail_dl_dma_pool;
3403 }
3404 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3405 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3406 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3407 }
3408
3409 /* Allocate memory for SNS commands */
3410 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3411 /* Get consistent memory allocated for SNS commands */
3412 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3413 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3414 if (!ha->sns_cmd)
3415 goto fail_dma_pool;
3416 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3417 "sns_cmd: %p.\n", ha->sns_cmd);
3418 } else {
3419 /* Get consistent memory allocated for MS IOCB */
3420 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3421 &ha->ms_iocb_dma);
3422 if (!ha->ms_iocb)
3423 goto fail_dma_pool;
3424 /* Get consistent memory allocated for CT SNS commands */
3425 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3426 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3427 if (!ha->ct_sns)
3428 goto fail_free_ms_iocb;
3429 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3430 "ms_iocb=%p ct_sns=%p.\n",
3431 ha->ms_iocb, ha->ct_sns);
3432 }
3433
3434 /* Allocate memory for request ring */
3435 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3436 if (!*req) {
3437 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3438 "Failed to allocate memory for req.\n");
3439 goto fail_req;
3440 }
3441 (*req)->length = req_len;
3442 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3443 ((*req)->length + 1) * sizeof(request_t),
3444 &(*req)->dma, GFP_KERNEL);
3445 if (!(*req)->ring) {
3446 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3447 "Failed to allocate memory for req_ring.\n");
3448 goto fail_req_ring;
3449 }
3450 /* Allocate memory for response ring */
3451 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3452 if (!*rsp) {
3453 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3454 "Failed to allocate memory for rsp.\n");
3455 goto fail_rsp;
3456 }
3457 (*rsp)->hw = ha;
3458 (*rsp)->length = rsp_len;
3459 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3460 ((*rsp)->length + 1) * sizeof(response_t),
3461 &(*rsp)->dma, GFP_KERNEL);
3462 if (!(*rsp)->ring) {
3463 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3464 "Failed to allocate memory for rsp_ring.\n");
3465 goto fail_rsp_ring;
3466 }
3467 (*req)->rsp = *rsp;
3468 (*rsp)->req = *req;
3469 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3470 "req=%p req->length=%d req->ring=%p rsp=%p "
3471 "rsp->length=%d rsp->ring=%p.\n",
3472 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3473 (*rsp)->ring);
3474 /* Allocate memory for NVRAM data for vports */
3475 if (ha->nvram_npiv_size) {
3476 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
3477 ha->nvram_npiv_size, GFP_KERNEL);
3478 if (!ha->npiv_info) {
3479 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3480 "Failed to allocate memory for npiv_info.\n");
3481 goto fail_npiv_info;
3482 }
3483 } else
3484 ha->npiv_info = NULL;
3485
3486 /* Get consistent memory allocated for EX-INIT-CB. */
3487 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3488 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3489 &ha->ex_init_cb_dma);
3490 if (!ha->ex_init_cb)
3491 goto fail_ex_init_cb;
3492 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3493 "ex_init_cb=%p.\n", ha->ex_init_cb);
3494 }
3495
3496 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3497
3498 /* Get consistent memory allocated for Async Port-Database. */
3499 if (!IS_FWI2_CAPABLE(ha)) {
3500 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3501 &ha->async_pd_dma);
3502 if (!ha->async_pd)
3503 goto fail_async_pd;
3504 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3505 "async_pd=%p.\n", ha->async_pd);
3506 }
3507
3508 INIT_LIST_HEAD(&ha->vp_list);
3509
3510 /* Allocate memory for our loop_id bitmap */
3511 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3512 GFP_KERNEL);
3513 if (!ha->loop_id_map)
3514 goto fail_loop_id_map;
3515 else {
3516 qla2x00_set_reserved_loop_ids(ha);
3517 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3518 "loop_id_map=%p.\n", ha->loop_id_map);
3519 }
3520
3521 return 0;
3522
3523 fail_loop_id_map:
3524 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3525 fail_async_pd:
3526 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
3527 fail_ex_init_cb:
3528 kfree(ha->npiv_info);
3529 fail_npiv_info:
3530 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3531 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3532 (*rsp)->ring = NULL;
3533 (*rsp)->dma = 0;
3534 fail_rsp_ring:
3535 kfree(*rsp);
3536 fail_rsp:
3537 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3538 sizeof(request_t), (*req)->ring, (*req)->dma);
3539 (*req)->ring = NULL;
3540 (*req)->dma = 0;
3541 fail_req_ring:
3542 kfree(*req);
3543 fail_req:
3544 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3545 ha->ct_sns, ha->ct_sns_dma);
3546 ha->ct_sns = NULL;
3547 ha->ct_sns_dma = 0;
3548 fail_free_ms_iocb:
3549 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3550 ha->ms_iocb = NULL;
3551 ha->ms_iocb_dma = 0;
3552
3553 if (ha->sns_cmd)
3554 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3555 ha->sns_cmd, ha->sns_cmd_dma);
3556 fail_dma_pool:
3557 if (IS_QLA82XX(ha) || ql2xenabledif) {
3558 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3559 ha->fcp_cmnd_dma_pool = NULL;
3560 }
3561 fail_dl_dma_pool:
3562 if (IS_QLA82XX(ha) || ql2xenabledif) {
3563 dma_pool_destroy(ha->dl_dma_pool);
3564 ha->dl_dma_pool = NULL;
3565 }
3566 fail_s_dma_pool:
3567 dma_pool_destroy(ha->s_dma_pool);
3568 ha->s_dma_pool = NULL;
3569 fail_free_nvram:
3570 kfree(ha->nvram);
3571 ha->nvram = NULL;
3572 fail_free_ctx_mempool:
3573 if (ha->ctx_mempool)
3574 mempool_destroy(ha->ctx_mempool);
3575 ha->ctx_mempool = NULL;
3576 fail_free_srb_mempool:
3577 if (ha->srb_mempool)
3578 mempool_destroy(ha->srb_mempool);
3579 ha->srb_mempool = NULL;
3580 fail_free_gid_list:
3581 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3582 ha->gid_list,
3583 ha->gid_list_dma);
3584 ha->gid_list = NULL;
3585 ha->gid_list_dma = 0;
3586 fail_free_tgt_mem:
3587 qlt_mem_free(ha);
3588 fail_free_init_cb:
3589 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3590 ha->init_cb_dma);
3591 ha->init_cb = NULL;
3592 ha->init_cb_dma = 0;
3593 fail:
3594 ql_log(ql_log_fatal, NULL, 0x0030,
3595 "Memory allocation failure.\n");
3596 return -ENOMEM;
3597 }
3598
3599 /*
3600 * qla2x00_free_fw_dump
3601 * Frees fw dump stuff.
3602 *
3603 * Input:
3604 * ha = adapter block pointer
3605 */
3606 static void
qla2x00_free_fw_dump(struct qla_hw_data * ha)3607 qla2x00_free_fw_dump(struct qla_hw_data *ha)
3608 {
3609 if (ha->fce)
3610 dma_free_coherent(&ha->pdev->dev,
3611 FCE_SIZE, ha->fce, ha->fce_dma);
3612
3613 if (ha->eft)
3614 dma_free_coherent(&ha->pdev->dev,
3615 EFT_SIZE, ha->eft, ha->eft_dma);
3616
3617 if (ha->fw_dump)
3618 vfree(ha->fw_dump);
3619 if (ha->fw_dump_template)
3620 vfree(ha->fw_dump_template);
3621
3622 ha->fce = NULL;
3623 ha->fce_dma = 0;
3624 ha->eft = NULL;
3625 ha->eft_dma = 0;
3626 ha->fw_dumped = 0;
3627 ha->fw_dump_cap_flags = 0;
3628 ha->fw_dump_reading = 0;
3629 ha->fw_dump = NULL;
3630 ha->fw_dump_len = 0;
3631 ha->fw_dump_template = NULL;
3632 ha->fw_dump_template_len = 0;
3633 }
3634
3635 /*
3636 * qla2x00_mem_free
3637 * Frees all adapter allocated memory.
3638 *
3639 * Input:
3640 * ha = adapter block pointer.
3641 */
3642 static void
qla2x00_mem_free(struct qla_hw_data * ha)3643 qla2x00_mem_free(struct qla_hw_data *ha)
3644 {
3645 qla2x00_free_fw_dump(ha);
3646
3647 if (ha->mctp_dump)
3648 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3649 ha->mctp_dump_dma);
3650
3651 if (ha->srb_mempool)
3652 mempool_destroy(ha->srb_mempool);
3653
3654 if (ha->dcbx_tlv)
3655 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3656 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3657
3658 if (ha->xgmac_data)
3659 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3660 ha->xgmac_data, ha->xgmac_data_dma);
3661
3662 if (ha->sns_cmd)
3663 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3664 ha->sns_cmd, ha->sns_cmd_dma);
3665
3666 if (ha->ct_sns)
3667 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3668 ha->ct_sns, ha->ct_sns_dma);
3669
3670 if (ha->sfp_data)
3671 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3672
3673 if (ha->ms_iocb)
3674 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3675
3676 if (ha->ex_init_cb)
3677 dma_pool_free(ha->s_dma_pool,
3678 ha->ex_init_cb, ha->ex_init_cb_dma);
3679
3680 if (ha->async_pd)
3681 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3682
3683 if (ha->s_dma_pool)
3684 dma_pool_destroy(ha->s_dma_pool);
3685
3686 if (ha->gid_list)
3687 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3688 ha->gid_list, ha->gid_list_dma);
3689
3690 if (IS_QLA82XX(ha)) {
3691 if (!list_empty(&ha->gbl_dsd_list)) {
3692 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3693
3694 /* clean up allocated prev pool */
3695 list_for_each_entry_safe(dsd_ptr,
3696 tdsd_ptr, &ha->gbl_dsd_list, list) {
3697 dma_pool_free(ha->dl_dma_pool,
3698 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3699 list_del(&dsd_ptr->list);
3700 kfree(dsd_ptr);
3701 }
3702 }
3703 }
3704
3705 if (ha->dl_dma_pool)
3706 dma_pool_destroy(ha->dl_dma_pool);
3707
3708 if (ha->fcp_cmnd_dma_pool)
3709 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3710
3711 if (ha->ctx_mempool)
3712 mempool_destroy(ha->ctx_mempool);
3713
3714 qlt_mem_free(ha);
3715
3716 if (ha->init_cb)
3717 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3718 ha->init_cb, ha->init_cb_dma);
3719 vfree(ha->optrom_buffer);
3720 kfree(ha->nvram);
3721 kfree(ha->npiv_info);
3722 kfree(ha->swl);
3723 kfree(ha->loop_id_map);
3724
3725 ha->srb_mempool = NULL;
3726 ha->ctx_mempool = NULL;
3727 ha->sns_cmd = NULL;
3728 ha->sns_cmd_dma = 0;
3729 ha->ct_sns = NULL;
3730 ha->ct_sns_dma = 0;
3731 ha->ms_iocb = NULL;
3732 ha->ms_iocb_dma = 0;
3733 ha->init_cb = NULL;
3734 ha->init_cb_dma = 0;
3735 ha->ex_init_cb = NULL;
3736 ha->ex_init_cb_dma = 0;
3737 ha->async_pd = NULL;
3738 ha->async_pd_dma = 0;
3739
3740 ha->s_dma_pool = NULL;
3741 ha->dl_dma_pool = NULL;
3742 ha->fcp_cmnd_dma_pool = NULL;
3743
3744 ha->gid_list = NULL;
3745 ha->gid_list_dma = 0;
3746
3747 ha->tgt.atio_ring = NULL;
3748 ha->tgt.atio_dma = 0;
3749 ha->tgt.tgt_vp_map = NULL;
3750 }
3751
qla2x00_create_host(struct scsi_host_template * sht,struct qla_hw_data * ha)3752 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3753 struct qla_hw_data *ha)
3754 {
3755 struct Scsi_Host *host;
3756 struct scsi_qla_host *vha = NULL;
3757
3758 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3759 if (host == NULL) {
3760 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3761 "Failed to allocate host from the scsi layer, aborting.\n");
3762 goto fail;
3763 }
3764
3765 /* Clear our data area */
3766 vha = shost_priv(host);
3767 memset(vha, 0, sizeof(scsi_qla_host_t));
3768
3769 vha->host = host;
3770 vha->host_no = host->host_no;
3771 vha->hw = ha;
3772
3773 INIT_LIST_HEAD(&vha->vp_fcports);
3774 INIT_LIST_HEAD(&vha->work_list);
3775 INIT_LIST_HEAD(&vha->list);
3776 INIT_LIST_HEAD(&vha->qla_cmd_list);
3777 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
3778
3779 spin_lock_init(&vha->work_lock);
3780 spin_lock_init(&vha->cmd_list_lock);
3781
3782 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3783 ql_dbg(ql_dbg_init, vha, 0x0041,
3784 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3785 vha->host, vha->hw, vha,
3786 dev_name(&(ha->pdev->dev)));
3787
3788 return vha;
3789
3790 fail:
3791 return vha;
3792 }
3793
3794 static struct qla_work_evt *
qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)3795 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3796 {
3797 struct qla_work_evt *e;
3798 uint8_t bail;
3799
3800 QLA_VHA_MARK_BUSY(vha, bail);
3801 if (bail)
3802 return NULL;
3803
3804 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3805 if (!e) {
3806 QLA_VHA_MARK_NOT_BUSY(vha);
3807 return NULL;
3808 }
3809
3810 INIT_LIST_HEAD(&e->list);
3811 e->type = type;
3812 e->flags = QLA_EVT_FLAG_FREE;
3813 return e;
3814 }
3815
3816 static int
qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)3817 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3818 {
3819 unsigned long flags;
3820
3821 spin_lock_irqsave(&vha->work_lock, flags);
3822 list_add_tail(&e->list, &vha->work_list);
3823 spin_unlock_irqrestore(&vha->work_lock, flags);
3824 qla2xxx_wake_dpc(vha);
3825
3826 return QLA_SUCCESS;
3827 }
3828
3829 int
qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)3830 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
3831 u32 data)
3832 {
3833 struct qla_work_evt *e;
3834
3835 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
3836 if (!e)
3837 return QLA_FUNCTION_FAILED;
3838
3839 e->u.aen.code = code;
3840 e->u.aen.data = data;
3841 return qla2x00_post_work(vha, e);
3842 }
3843
3844 int
qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)3845 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3846 {
3847 struct qla_work_evt *e;
3848
3849 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
3850 if (!e)
3851 return QLA_FUNCTION_FAILED;
3852
3853 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3854 return qla2x00_post_work(vha, e);
3855 }
3856
3857 #define qla2x00_post_async_work(name, type) \
3858 int qla2x00_post_async_##name##_work( \
3859 struct scsi_qla_host *vha, \
3860 fc_port_t *fcport, uint16_t *data) \
3861 { \
3862 struct qla_work_evt *e; \
3863 \
3864 e = qla2x00_alloc_work(vha, type); \
3865 if (!e) \
3866 return QLA_FUNCTION_FAILED; \
3867 \
3868 e->u.logio.fcport = fcport; \
3869 if (data) { \
3870 e->u.logio.data[0] = data[0]; \
3871 e->u.logio.data[1] = data[1]; \
3872 } \
3873 return qla2x00_post_work(vha, e); \
3874 }
3875
3876 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3877 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3878 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3879 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
3880 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3881 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
3882
3883 int
qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)3884 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3885 {
3886 struct qla_work_evt *e;
3887
3888 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3889 if (!e)
3890 return QLA_FUNCTION_FAILED;
3891
3892 e->u.uevent.code = code;
3893 return qla2x00_post_work(vha, e);
3894 }
3895
3896 static void
qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)3897 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3898 {
3899 char event_string[40];
3900 char *envp[] = { event_string, NULL };
3901
3902 switch (code) {
3903 case QLA_UEVENT_CODE_FW_DUMP:
3904 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3905 vha->host_no);
3906 break;
3907 default:
3908 /* do nothing */
3909 break;
3910 }
3911 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3912 }
3913
3914 int
qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)3915 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3916 uint32_t *data, int cnt)
3917 {
3918 struct qla_work_evt *e;
3919
3920 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3921 if (!e)
3922 return QLA_FUNCTION_FAILED;
3923
3924 e->u.aenfx.evtcode = evtcode;
3925 e->u.aenfx.count = cnt;
3926 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3927 return qla2x00_post_work(vha, e);
3928 }
3929
3930 void
qla2x00_do_work(struct scsi_qla_host * vha)3931 qla2x00_do_work(struct scsi_qla_host *vha)
3932 {
3933 struct qla_work_evt *e, *tmp;
3934 unsigned long flags;
3935 LIST_HEAD(work);
3936
3937 spin_lock_irqsave(&vha->work_lock, flags);
3938 list_splice_init(&vha->work_list, &work);
3939 spin_unlock_irqrestore(&vha->work_lock, flags);
3940
3941 list_for_each_entry_safe(e, tmp, &work, list) {
3942 list_del_init(&e->list);
3943
3944 switch (e->type) {
3945 case QLA_EVT_AEN:
3946 fc_host_post_event(vha->host, fc_get_event_number(),
3947 e->u.aen.code, e->u.aen.data);
3948 break;
3949 case QLA_EVT_IDC_ACK:
3950 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3951 break;
3952 case QLA_EVT_ASYNC_LOGIN:
3953 qla2x00_async_login(vha, e->u.logio.fcport,
3954 e->u.logio.data);
3955 break;
3956 case QLA_EVT_ASYNC_LOGIN_DONE:
3957 qla2x00_async_login_done(vha, e->u.logio.fcport,
3958 e->u.logio.data);
3959 break;
3960 case QLA_EVT_ASYNC_LOGOUT:
3961 qla2x00_async_logout(vha, e->u.logio.fcport);
3962 break;
3963 case QLA_EVT_ASYNC_LOGOUT_DONE:
3964 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3965 e->u.logio.data);
3966 break;
3967 case QLA_EVT_ASYNC_ADISC:
3968 qla2x00_async_adisc(vha, e->u.logio.fcport,
3969 e->u.logio.data);
3970 break;
3971 case QLA_EVT_ASYNC_ADISC_DONE:
3972 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3973 e->u.logio.data);
3974 break;
3975 case QLA_EVT_UEVENT:
3976 qla2x00_uevent_emit(vha, e->u.uevent.code);
3977 break;
3978 case QLA_EVT_AENFX:
3979 qlafx00_process_aen(vha, e);
3980 break;
3981 }
3982 if (e->flags & QLA_EVT_FLAG_FREE)
3983 kfree(e);
3984
3985 /* For each work completed decrement vha ref count */
3986 QLA_VHA_MARK_NOT_BUSY(vha);
3987 }
3988 }
3989
3990 /* Relogins all the fcports of a vport
3991 * Context: dpc thread
3992 */
qla2x00_relogin(struct scsi_qla_host * vha)3993 void qla2x00_relogin(struct scsi_qla_host *vha)
3994 {
3995 fc_port_t *fcport;
3996 int status;
3997 uint16_t next_loopid = 0;
3998 struct qla_hw_data *ha = vha->hw;
3999 uint16_t data[2];
4000
4001 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4002 /*
4003 * If the port is not ONLINE then try to login
4004 * to it if we haven't run out of retries.
4005 */
4006 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4007 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
4008 fcport->login_retry--;
4009 if (fcport->flags & FCF_FABRIC_DEVICE) {
4010 if (fcport->flags & FCF_FCP2_DEVICE)
4011 ha->isp_ops->fabric_logout(vha,
4012 fcport->loop_id,
4013 fcport->d_id.b.domain,
4014 fcport->d_id.b.area,
4015 fcport->d_id.b.al_pa);
4016
4017 if (fcport->loop_id == FC_NO_LOOP_ID) {
4018 fcport->loop_id = next_loopid =
4019 ha->min_external_loopid;
4020 status = qla2x00_find_new_loop_id(
4021 vha, fcport);
4022 if (status != QLA_SUCCESS) {
4023 /* Ran out of IDs to use */
4024 break;
4025 }
4026 }
4027
4028 if (IS_ALOGIO_CAPABLE(ha)) {
4029 fcport->flags |= FCF_ASYNC_SENT;
4030 data[0] = 0;
4031 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4032 status = qla2x00_post_async_login_work(
4033 vha, fcport, data);
4034 if (status == QLA_SUCCESS)
4035 continue;
4036 /* Attempt a retry. */
4037 status = 1;
4038 } else {
4039 status = qla2x00_fabric_login(vha,
4040 fcport, &next_loopid);
4041 if (status == QLA_SUCCESS) {
4042 int status2;
4043 uint8_t opts;
4044
4045 opts = 0;
4046 if (fcport->flags &
4047 FCF_FCP2_DEVICE)
4048 opts |= BIT_1;
4049 status2 =
4050 qla2x00_get_port_database(
4051 vha, fcport, opts);
4052 if (status2 != QLA_SUCCESS)
4053 status = 1;
4054 }
4055 }
4056 } else
4057 status = qla2x00_local_device_login(vha,
4058 fcport);
4059
4060 if (status == QLA_SUCCESS) {
4061 fcport->old_loop_id = fcport->loop_id;
4062
4063 ql_dbg(ql_dbg_disc, vha, 0x2003,
4064 "Port login OK: logged in ID 0x%x.\n",
4065 fcport->loop_id);
4066
4067 qla2x00_update_fcport(vha, fcport);
4068
4069 } else if (status == 1) {
4070 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4071 /* retry the login again */
4072 ql_dbg(ql_dbg_disc, vha, 0x2007,
4073 "Retrying %d login again loop_id 0x%x.\n",
4074 fcport->login_retry, fcport->loop_id);
4075 } else {
4076 fcport->login_retry = 0;
4077 }
4078
4079 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
4080 qla2x00_clear_loop_id(fcport);
4081 }
4082 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4083 break;
4084 }
4085 }
4086
4087 /* Schedule work on any of the dpc-workqueues */
4088 void
qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)4089 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4090 {
4091 struct qla_hw_data *ha = base_vha->hw;
4092
4093 switch (work_code) {
4094 case MBA_IDC_AEN: /* 0x8200 */
4095 if (ha->dpc_lp_wq)
4096 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4097 break;
4098
4099 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4100 if (!ha->flags.nic_core_reset_hdlr_active) {
4101 if (ha->dpc_hp_wq)
4102 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4103 } else
4104 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4105 "NIC Core reset is already active. Skip "
4106 "scheduling it again.\n");
4107 break;
4108 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4109 if (ha->dpc_hp_wq)
4110 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4111 break;
4112 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4113 if (ha->dpc_hp_wq)
4114 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4115 break;
4116 default:
4117 ql_log(ql_log_warn, base_vha, 0xb05f,
4118 "Unknown work-code=0x%x.\n", work_code);
4119 }
4120
4121 return;
4122 }
4123
4124 /* Work: Perform NIC Core Unrecoverable state handling */
4125 void
qla83xx_nic_core_unrecoverable_work(struct work_struct * work)4126 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4127 {
4128 struct qla_hw_data *ha =
4129 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4130 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4131 uint32_t dev_state = 0;
4132
4133 qla83xx_idc_lock(base_vha, 0);
4134 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4135 qla83xx_reset_ownership(base_vha);
4136 if (ha->flags.nic_core_reset_owner) {
4137 ha->flags.nic_core_reset_owner = 0;
4138 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4139 QLA8XXX_DEV_FAILED);
4140 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4141 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4142 }
4143 qla83xx_idc_unlock(base_vha, 0);
4144 }
4145
4146 /* Work: Execute IDC state handler */
4147 void
qla83xx_idc_state_handler_work(struct work_struct * work)4148 qla83xx_idc_state_handler_work(struct work_struct *work)
4149 {
4150 struct qla_hw_data *ha =
4151 container_of(work, struct qla_hw_data, idc_state_handler);
4152 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4153 uint32_t dev_state = 0;
4154
4155 qla83xx_idc_lock(base_vha, 0);
4156 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4157 if (dev_state == QLA8XXX_DEV_FAILED ||
4158 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4159 qla83xx_idc_state_handler(base_vha);
4160 qla83xx_idc_unlock(base_vha, 0);
4161 }
4162
4163 static int
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)4164 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4165 {
4166 int rval = QLA_SUCCESS;
4167 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4168 uint32_t heart_beat_counter1, heart_beat_counter2;
4169
4170 do {
4171 if (time_after(jiffies, heart_beat_wait)) {
4172 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4173 "Nic Core f/w is not alive.\n");
4174 rval = QLA_FUNCTION_FAILED;
4175 break;
4176 }
4177
4178 qla83xx_idc_lock(base_vha, 0);
4179 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4180 &heart_beat_counter1);
4181 qla83xx_idc_unlock(base_vha, 0);
4182 msleep(100);
4183 qla83xx_idc_lock(base_vha, 0);
4184 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4185 &heart_beat_counter2);
4186 qla83xx_idc_unlock(base_vha, 0);
4187 } while (heart_beat_counter1 == heart_beat_counter2);
4188
4189 return rval;
4190 }
4191
4192 /* Work: Perform NIC Core Reset handling */
4193 void
qla83xx_nic_core_reset_work(struct work_struct * work)4194 qla83xx_nic_core_reset_work(struct work_struct *work)
4195 {
4196 struct qla_hw_data *ha =
4197 container_of(work, struct qla_hw_data, nic_core_reset);
4198 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4199 uint32_t dev_state = 0;
4200
4201 if (IS_QLA2031(ha)) {
4202 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4203 ql_log(ql_log_warn, base_vha, 0xb081,
4204 "Failed to dump mctp\n");
4205 return;
4206 }
4207
4208 if (!ha->flags.nic_core_reset_hdlr_active) {
4209 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4210 qla83xx_idc_lock(base_vha, 0);
4211 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4212 &dev_state);
4213 qla83xx_idc_unlock(base_vha, 0);
4214 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4215 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4216 "Nic Core f/w is alive.\n");
4217 return;
4218 }
4219 }
4220
4221 ha->flags.nic_core_reset_hdlr_active = 1;
4222 if (qla83xx_nic_core_reset(base_vha)) {
4223 /* NIC Core reset failed. */
4224 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4225 "NIC Core reset failed.\n");
4226 }
4227 ha->flags.nic_core_reset_hdlr_active = 0;
4228 }
4229 }
4230
4231 /* Work: Handle 8200 IDC aens */
4232 void
qla83xx_service_idc_aen(struct work_struct * work)4233 qla83xx_service_idc_aen(struct work_struct *work)
4234 {
4235 struct qla_hw_data *ha =
4236 container_of(work, struct qla_hw_data, idc_aen);
4237 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4238 uint32_t dev_state, idc_control;
4239
4240 qla83xx_idc_lock(base_vha, 0);
4241 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4242 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4243 qla83xx_idc_unlock(base_vha, 0);
4244 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4245 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4246 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4247 "Application requested NIC Core Reset.\n");
4248 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4249 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4250 QLA_SUCCESS) {
4251 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4252 "Other protocol driver requested NIC Core Reset.\n");
4253 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4254 }
4255 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4256 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4257 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4258 }
4259 }
4260
4261 static void
qla83xx_wait_logic(void)4262 qla83xx_wait_logic(void)
4263 {
4264 int i;
4265
4266 /* Yield CPU */
4267 if (!in_interrupt()) {
4268 /*
4269 * Wait about 200ms before retrying again.
4270 * This controls the number of retries for single
4271 * lock operation.
4272 */
4273 msleep(100);
4274 schedule();
4275 } else {
4276 for (i = 0; i < 20; i++)
4277 cpu_relax(); /* This a nop instr on i386 */
4278 }
4279 }
4280
4281 static int
qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)4282 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4283 {
4284 int rval;
4285 uint32_t data;
4286 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4287 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4288 struct qla_hw_data *ha = base_vha->hw;
4289 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4290 "Trying force recovery of the IDC lock.\n");
4291
4292 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4293 if (rval)
4294 return rval;
4295
4296 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4297 return QLA_SUCCESS;
4298 } else {
4299 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4300 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4301 data);
4302 if (rval)
4303 return rval;
4304
4305 msleep(200);
4306
4307 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4308 &data);
4309 if (rval)
4310 return rval;
4311
4312 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4313 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4314 ~(idc_lck_rcvry_stage_mask));
4315 rval = qla83xx_wr_reg(base_vha,
4316 QLA83XX_IDC_LOCK_RECOVERY, data);
4317 if (rval)
4318 return rval;
4319
4320 /* Forcefully perform IDC UnLock */
4321 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4322 &data);
4323 if (rval)
4324 return rval;
4325 /* Clear lock-id by setting 0xff */
4326 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4327 0xff);
4328 if (rval)
4329 return rval;
4330 /* Clear lock-recovery by setting 0x0 */
4331 rval = qla83xx_wr_reg(base_vha,
4332 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4333 if (rval)
4334 return rval;
4335 } else
4336 return QLA_SUCCESS;
4337 }
4338
4339 return rval;
4340 }
4341
4342 static int
qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)4343 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4344 {
4345 int rval = QLA_SUCCESS;
4346 uint32_t o_drv_lockid, n_drv_lockid;
4347 unsigned long lock_recovery_timeout;
4348
4349 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4350 retry_lockid:
4351 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4352 if (rval)
4353 goto exit;
4354
4355 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4356 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4357 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4358 return QLA_SUCCESS;
4359 else
4360 return QLA_FUNCTION_FAILED;
4361 }
4362
4363 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4364 if (rval)
4365 goto exit;
4366
4367 if (o_drv_lockid == n_drv_lockid) {
4368 qla83xx_wait_logic();
4369 goto retry_lockid;
4370 } else
4371 return QLA_SUCCESS;
4372
4373 exit:
4374 return rval;
4375 }
4376
4377 void
qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)4378 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4379 {
4380 uint16_t options = (requester_id << 15) | BIT_6;
4381 uint32_t data;
4382 uint32_t lock_owner;
4383 struct qla_hw_data *ha = base_vha->hw;
4384
4385 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4386 retry_lock:
4387 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4388 == QLA_SUCCESS) {
4389 if (data) {
4390 /* Setting lock-id to our function-number */
4391 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4392 ha->portnum);
4393 } else {
4394 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4395 &lock_owner);
4396 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4397 "Failed to acquire IDC lock, acquired by %d, "
4398 "retrying...\n", lock_owner);
4399
4400 /* Retry/Perform IDC-Lock recovery */
4401 if (qla83xx_idc_lock_recovery(base_vha)
4402 == QLA_SUCCESS) {
4403 qla83xx_wait_logic();
4404 goto retry_lock;
4405 } else
4406 ql_log(ql_log_warn, base_vha, 0xb075,
4407 "IDC Lock recovery FAILED.\n");
4408 }
4409
4410 }
4411
4412 return;
4413
4414 /* XXX: IDC-lock implementation using access-control mbx */
4415 retry_lock2:
4416 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4417 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4418 "Failed to acquire IDC lock. retrying...\n");
4419 /* Retry/Perform IDC-Lock recovery */
4420 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4421 qla83xx_wait_logic();
4422 goto retry_lock2;
4423 } else
4424 ql_log(ql_log_warn, base_vha, 0xb076,
4425 "IDC Lock recovery FAILED.\n");
4426 }
4427
4428 return;
4429 }
4430
4431 void
qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)4432 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4433 {
4434 #if 0
4435 uint16_t options = (requester_id << 15) | BIT_7;
4436 #endif
4437 uint16_t retry;
4438 uint32_t data;
4439 struct qla_hw_data *ha = base_vha->hw;
4440
4441 /* IDC-unlock implementation using driver-unlock/lock-id
4442 * remote registers
4443 */
4444 retry = 0;
4445 retry_unlock:
4446 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4447 == QLA_SUCCESS) {
4448 if (data == ha->portnum) {
4449 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4450 /* Clearing lock-id by setting 0xff */
4451 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4452 } else if (retry < 10) {
4453 /* SV: XXX: IDC unlock retrying needed here? */
4454
4455 /* Retry for IDC-unlock */
4456 qla83xx_wait_logic();
4457 retry++;
4458 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4459 "Failed to release IDC lock, retyring=%d\n", retry);
4460 goto retry_unlock;
4461 }
4462 } else if (retry < 10) {
4463 /* Retry for IDC-unlock */
4464 qla83xx_wait_logic();
4465 retry++;
4466 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4467 "Failed to read drv-lockid, retyring=%d\n", retry);
4468 goto retry_unlock;
4469 }
4470
4471 return;
4472
4473 #if 0
4474 /* XXX: IDC-unlock implementation using access-control mbx */
4475 retry = 0;
4476 retry_unlock2:
4477 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4478 if (retry < 10) {
4479 /* Retry for IDC-unlock */
4480 qla83xx_wait_logic();
4481 retry++;
4482 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4483 "Failed to release IDC lock, retyring=%d\n", retry);
4484 goto retry_unlock2;
4485 }
4486 }
4487
4488 return;
4489 #endif
4490 }
4491
4492 int
__qla83xx_set_drv_presence(scsi_qla_host_t * vha)4493 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4494 {
4495 int rval = QLA_SUCCESS;
4496 struct qla_hw_data *ha = vha->hw;
4497 uint32_t drv_presence;
4498
4499 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4500 if (rval == QLA_SUCCESS) {
4501 drv_presence |= (1 << ha->portnum);
4502 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4503 drv_presence);
4504 }
4505
4506 return rval;
4507 }
4508
4509 int
qla83xx_set_drv_presence(scsi_qla_host_t * vha)4510 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4511 {
4512 int rval = QLA_SUCCESS;
4513
4514 qla83xx_idc_lock(vha, 0);
4515 rval = __qla83xx_set_drv_presence(vha);
4516 qla83xx_idc_unlock(vha, 0);
4517
4518 return rval;
4519 }
4520
4521 int
__qla83xx_clear_drv_presence(scsi_qla_host_t * vha)4522 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4523 {
4524 int rval = QLA_SUCCESS;
4525 struct qla_hw_data *ha = vha->hw;
4526 uint32_t drv_presence;
4527
4528 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4529 if (rval == QLA_SUCCESS) {
4530 drv_presence &= ~(1 << ha->portnum);
4531 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4532 drv_presence);
4533 }
4534
4535 return rval;
4536 }
4537
4538 int
qla83xx_clear_drv_presence(scsi_qla_host_t * vha)4539 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4540 {
4541 int rval = QLA_SUCCESS;
4542
4543 qla83xx_idc_lock(vha, 0);
4544 rval = __qla83xx_clear_drv_presence(vha);
4545 qla83xx_idc_unlock(vha, 0);
4546
4547 return rval;
4548 }
4549
4550 static void
qla83xx_need_reset_handler(scsi_qla_host_t * vha)4551 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4552 {
4553 struct qla_hw_data *ha = vha->hw;
4554 uint32_t drv_ack, drv_presence;
4555 unsigned long ack_timeout;
4556
4557 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4558 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4559 while (1) {
4560 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4561 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4562 if ((drv_ack & drv_presence) == drv_presence)
4563 break;
4564
4565 if (time_after_eq(jiffies, ack_timeout)) {
4566 ql_log(ql_log_warn, vha, 0xb067,
4567 "RESET ACK TIMEOUT! drv_presence=0x%x "
4568 "drv_ack=0x%x\n", drv_presence, drv_ack);
4569 /*
4570 * The function(s) which did not ack in time are forced
4571 * to withdraw any further participation in the IDC
4572 * reset.
4573 */
4574 if (drv_ack != drv_presence)
4575 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4576 drv_ack);
4577 break;
4578 }
4579
4580 qla83xx_idc_unlock(vha, 0);
4581 msleep(1000);
4582 qla83xx_idc_lock(vha, 0);
4583 }
4584
4585 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4586 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4587 }
4588
4589 static int
qla83xx_device_bootstrap(scsi_qla_host_t * vha)4590 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4591 {
4592 int rval = QLA_SUCCESS;
4593 uint32_t idc_control;
4594
4595 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4596 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4597
4598 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4599 __qla83xx_get_idc_control(vha, &idc_control);
4600 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4601 __qla83xx_set_idc_control(vha, 0);
4602
4603 qla83xx_idc_unlock(vha, 0);
4604 rval = qla83xx_restart_nic_firmware(vha);
4605 qla83xx_idc_lock(vha, 0);
4606
4607 if (rval != QLA_SUCCESS) {
4608 ql_log(ql_log_fatal, vha, 0xb06a,
4609 "Failed to restart NIC f/w.\n");
4610 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4611 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4612 } else {
4613 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4614 "Success in restarting nic f/w.\n");
4615 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4616 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4617 }
4618
4619 return rval;
4620 }
4621
4622 /* Assumes idc_lock always held on entry */
4623 int
qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)4624 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4625 {
4626 struct qla_hw_data *ha = base_vha->hw;
4627 int rval = QLA_SUCCESS;
4628 unsigned long dev_init_timeout;
4629 uint32_t dev_state;
4630
4631 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4632 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4633
4634 while (1) {
4635
4636 if (time_after_eq(jiffies, dev_init_timeout)) {
4637 ql_log(ql_log_warn, base_vha, 0xb06e,
4638 "Initialization TIMEOUT!\n");
4639 /* Init timeout. Disable further NIC Core
4640 * communication.
4641 */
4642 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4643 QLA8XXX_DEV_FAILED);
4644 ql_log(ql_log_info, base_vha, 0xb06f,
4645 "HW State: FAILED.\n");
4646 }
4647
4648 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4649 switch (dev_state) {
4650 case QLA8XXX_DEV_READY:
4651 if (ha->flags.nic_core_reset_owner)
4652 qla83xx_idc_audit(base_vha,
4653 IDC_AUDIT_COMPLETION);
4654 ha->flags.nic_core_reset_owner = 0;
4655 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4656 "Reset_owner reset by 0x%x.\n",
4657 ha->portnum);
4658 goto exit;
4659 case QLA8XXX_DEV_COLD:
4660 if (ha->flags.nic_core_reset_owner)
4661 rval = qla83xx_device_bootstrap(base_vha);
4662 else {
4663 /* Wait for AEN to change device-state */
4664 qla83xx_idc_unlock(base_vha, 0);
4665 msleep(1000);
4666 qla83xx_idc_lock(base_vha, 0);
4667 }
4668 break;
4669 case QLA8XXX_DEV_INITIALIZING:
4670 /* Wait for AEN to change device-state */
4671 qla83xx_idc_unlock(base_vha, 0);
4672 msleep(1000);
4673 qla83xx_idc_lock(base_vha, 0);
4674 break;
4675 case QLA8XXX_DEV_NEED_RESET:
4676 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4677 qla83xx_need_reset_handler(base_vha);
4678 else {
4679 /* Wait for AEN to change device-state */
4680 qla83xx_idc_unlock(base_vha, 0);
4681 msleep(1000);
4682 qla83xx_idc_lock(base_vha, 0);
4683 }
4684 /* reset timeout value after need reset handler */
4685 dev_init_timeout = jiffies +
4686 (ha->fcoe_dev_init_timeout * HZ);
4687 break;
4688 case QLA8XXX_DEV_NEED_QUIESCENT:
4689 /* XXX: DEBUG for now */
4690 qla83xx_idc_unlock(base_vha, 0);
4691 msleep(1000);
4692 qla83xx_idc_lock(base_vha, 0);
4693 break;
4694 case QLA8XXX_DEV_QUIESCENT:
4695 /* XXX: DEBUG for now */
4696 if (ha->flags.quiesce_owner)
4697 goto exit;
4698
4699 qla83xx_idc_unlock(base_vha, 0);
4700 msleep(1000);
4701 qla83xx_idc_lock(base_vha, 0);
4702 dev_init_timeout = jiffies +
4703 (ha->fcoe_dev_init_timeout * HZ);
4704 break;
4705 case QLA8XXX_DEV_FAILED:
4706 if (ha->flags.nic_core_reset_owner)
4707 qla83xx_idc_audit(base_vha,
4708 IDC_AUDIT_COMPLETION);
4709 ha->flags.nic_core_reset_owner = 0;
4710 __qla83xx_clear_drv_presence(base_vha);
4711 qla83xx_idc_unlock(base_vha, 0);
4712 qla8xxx_dev_failed_handler(base_vha);
4713 rval = QLA_FUNCTION_FAILED;
4714 qla83xx_idc_lock(base_vha, 0);
4715 goto exit;
4716 case QLA8XXX_BAD_VALUE:
4717 qla83xx_idc_unlock(base_vha, 0);
4718 msleep(1000);
4719 qla83xx_idc_lock(base_vha, 0);
4720 break;
4721 default:
4722 ql_log(ql_log_warn, base_vha, 0xb071,
4723 "Unknown Device State: %x.\n", dev_state);
4724 qla83xx_idc_unlock(base_vha, 0);
4725 qla8xxx_dev_failed_handler(base_vha);
4726 rval = QLA_FUNCTION_FAILED;
4727 qla83xx_idc_lock(base_vha, 0);
4728 goto exit;
4729 }
4730 }
4731
4732 exit:
4733 return rval;
4734 }
4735
4736 void
qla2x00_disable_board_on_pci_error(struct work_struct * work)4737 qla2x00_disable_board_on_pci_error(struct work_struct *work)
4738 {
4739 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4740 board_disable);
4741 struct pci_dev *pdev = ha->pdev;
4742 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4743
4744 ql_log(ql_log_warn, base_vha, 0x015b,
4745 "Disabling adapter.\n");
4746
4747 set_bit(UNLOADING, &base_vha->dpc_flags);
4748
4749 qla2x00_delete_all_vps(ha, base_vha);
4750
4751 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4752
4753 qla2x00_dfs_remove(base_vha);
4754
4755 qla84xx_put_chip(base_vha);
4756
4757 if (base_vha->timer_active)
4758 qla2x00_stop_timer(base_vha);
4759
4760 base_vha->flags.online = 0;
4761
4762 qla2x00_destroy_deferred_work(ha);
4763
4764 /*
4765 * Do not try to stop beacon blink as it will issue a mailbox
4766 * command.
4767 */
4768 qla2x00_free_sysfs_attr(base_vha, false);
4769
4770 fc_remove_host(base_vha->host);
4771
4772 scsi_remove_host(base_vha->host);
4773
4774 base_vha->flags.init_done = 0;
4775 qla25xx_delete_queues(base_vha);
4776 qla2x00_free_irqs(base_vha);
4777 qla2x00_free_fcports(base_vha);
4778 qla2x00_mem_free(ha);
4779 qla82xx_md_free(base_vha);
4780 qla2x00_free_queues(ha);
4781
4782 qla2x00_unmap_iobases(ha);
4783
4784 pci_release_selected_regions(ha->pdev, ha->bars);
4785 pci_disable_pcie_error_reporting(pdev);
4786 pci_disable_device(pdev);
4787
4788 /*
4789 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4790 */
4791 }
4792
4793 /**************************************************************************
4794 * qla2x00_do_dpc
4795 * This kernel thread is a task that is schedule by the interrupt handler
4796 * to perform the background processing for interrupts.
4797 *
4798 * Notes:
4799 * This task always run in the context of a kernel thread. It
4800 * is kick-off by the driver's detect code and starts up
4801 * up one per adapter. It immediately goes to sleep and waits for
4802 * some fibre event. When either the interrupt handler or
4803 * the timer routine detects a event it will one of the task
4804 * bits then wake us up.
4805 **************************************************************************/
4806 static int
qla2x00_do_dpc(void * data)4807 qla2x00_do_dpc(void *data)
4808 {
4809 scsi_qla_host_t *base_vha;
4810 struct qla_hw_data *ha;
4811
4812 ha = (struct qla_hw_data *)data;
4813 base_vha = pci_get_drvdata(ha->pdev);
4814
4815 set_user_nice(current, MIN_NICE);
4816
4817 set_current_state(TASK_INTERRUPTIBLE);
4818 while (!kthread_should_stop()) {
4819 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4820 "DPC handler sleeping.\n");
4821
4822 schedule();
4823
4824 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4825 goto end_loop;
4826
4827 if (ha->flags.eeh_busy) {
4828 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4829 "eeh_busy=%d.\n", ha->flags.eeh_busy);
4830 goto end_loop;
4831 }
4832
4833 ha->dpc_active = 1;
4834
4835 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4836 "DPC handler waking up, dpc_flags=0x%lx.\n",
4837 base_vha->dpc_flags);
4838
4839 qla2x00_do_work(base_vha);
4840
4841 if (IS_P3P_TYPE(ha)) {
4842 if (IS_QLA8044(ha)) {
4843 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4844 &base_vha->dpc_flags)) {
4845 qla8044_idc_lock(ha);
4846 qla8044_wr_direct(base_vha,
4847 QLA8044_CRB_DEV_STATE_INDEX,
4848 QLA8XXX_DEV_FAILED);
4849 qla8044_idc_unlock(ha);
4850 ql_log(ql_log_info, base_vha, 0x4004,
4851 "HW State: FAILED.\n");
4852 qla8044_device_state_handler(base_vha);
4853 continue;
4854 }
4855
4856 } else {
4857 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4858 &base_vha->dpc_flags)) {
4859 qla82xx_idc_lock(ha);
4860 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4861 QLA8XXX_DEV_FAILED);
4862 qla82xx_idc_unlock(ha);
4863 ql_log(ql_log_info, base_vha, 0x0151,
4864 "HW State: FAILED.\n");
4865 qla82xx_device_state_handler(base_vha);
4866 continue;
4867 }
4868 }
4869
4870 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4871 &base_vha->dpc_flags)) {
4872
4873 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4874 "FCoE context reset scheduled.\n");
4875 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4876 &base_vha->dpc_flags))) {
4877 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4878 /* FCoE-ctx reset failed.
4879 * Escalate to chip-reset
4880 */
4881 set_bit(ISP_ABORT_NEEDED,
4882 &base_vha->dpc_flags);
4883 }
4884 clear_bit(ABORT_ISP_ACTIVE,
4885 &base_vha->dpc_flags);
4886 }
4887
4888 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4889 "FCoE context reset end.\n");
4890 }
4891 } else if (IS_QLAFX00(ha)) {
4892 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4893 &base_vha->dpc_flags)) {
4894 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4895 "Firmware Reset Recovery\n");
4896 if (qlafx00_reset_initialize(base_vha)) {
4897 /* Failed. Abort isp later. */
4898 if (!test_bit(UNLOADING,
4899 &base_vha->dpc_flags)) {
4900 set_bit(ISP_UNRECOVERABLE,
4901 &base_vha->dpc_flags);
4902 ql_dbg(ql_dbg_dpc, base_vha,
4903 0x4021,
4904 "Reset Recovery Failed\n");
4905 }
4906 }
4907 }
4908
4909 if (test_and_clear_bit(FX00_TARGET_SCAN,
4910 &base_vha->dpc_flags)) {
4911 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4912 "ISPFx00 Target Scan scheduled\n");
4913 if (qlafx00_rescan_isp(base_vha)) {
4914 if (!test_bit(UNLOADING,
4915 &base_vha->dpc_flags))
4916 set_bit(ISP_UNRECOVERABLE,
4917 &base_vha->dpc_flags);
4918 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4919 "ISPFx00 Target Scan Failed\n");
4920 }
4921 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4922 "ISPFx00 Target Scan End\n");
4923 }
4924 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4925 &base_vha->dpc_flags)) {
4926 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4927 "ISPFx00 Host Info resend scheduled\n");
4928 qlafx00_fx_disc(base_vha,
4929 &base_vha->hw->mr.fcport,
4930 FXDISC_REG_HOST_INFO);
4931 }
4932 }
4933
4934 if (test_and_clear_bit
4935 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
4936 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
4937
4938 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4939 "ISP abort scheduled.\n");
4940 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4941 &base_vha->dpc_flags))) {
4942
4943 if (ha->isp_ops->abort_isp(base_vha)) {
4944 /* failed. retry later */
4945 set_bit(ISP_ABORT_NEEDED,
4946 &base_vha->dpc_flags);
4947 }
4948 clear_bit(ABORT_ISP_ACTIVE,
4949 &base_vha->dpc_flags);
4950 }
4951
4952 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4953 "ISP abort end.\n");
4954 }
4955
4956 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4957 &base_vha->dpc_flags)) {
4958 qla2x00_update_fcports(base_vha);
4959 }
4960
4961 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4962 int ret;
4963 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4964 if (ret != QLA_SUCCESS)
4965 ql_log(ql_log_warn, base_vha, 0x121,
4966 "Failed to enable receiving of RSCN "
4967 "requests: 0x%x.\n", ret);
4968 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4969 }
4970
4971 if (IS_QLAFX00(ha))
4972 goto loop_resync_check;
4973
4974 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
4975 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4976 "Quiescence mode scheduled.\n");
4977 if (IS_P3P_TYPE(ha)) {
4978 if (IS_QLA82XX(ha))
4979 qla82xx_device_state_handler(base_vha);
4980 if (IS_QLA8044(ha))
4981 qla8044_device_state_handler(base_vha);
4982 clear_bit(ISP_QUIESCE_NEEDED,
4983 &base_vha->dpc_flags);
4984 if (!ha->flags.quiesce_owner) {
4985 qla2x00_perform_loop_resync(base_vha);
4986 if (IS_QLA82XX(ha)) {
4987 qla82xx_idc_lock(ha);
4988 qla82xx_clear_qsnt_ready(
4989 base_vha);
4990 qla82xx_idc_unlock(ha);
4991 } else if (IS_QLA8044(ha)) {
4992 qla8044_idc_lock(ha);
4993 qla8044_clear_qsnt_ready(
4994 base_vha);
4995 qla8044_idc_unlock(ha);
4996 }
4997 }
4998 } else {
4999 clear_bit(ISP_QUIESCE_NEEDED,
5000 &base_vha->dpc_flags);
5001 qla2x00_quiesce_io(base_vha);
5002 }
5003 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5004 "Quiescence mode end.\n");
5005 }
5006
5007 if (test_and_clear_bit(RESET_MARKER_NEEDED,
5008 &base_vha->dpc_flags) &&
5009 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
5010
5011 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5012 "Reset marker scheduled.\n");
5013 qla2x00_rst_aen(base_vha);
5014 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
5015 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5016 "Reset marker end.\n");
5017 }
5018
5019 /* Retry each device up to login retry count */
5020 if ((test_and_clear_bit(RELOGIN_NEEDED,
5021 &base_vha->dpc_flags)) &&
5022 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5023 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
5024
5025 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5026 "Relogin scheduled.\n");
5027 qla2x00_relogin(base_vha);
5028 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5029 "Relogin end.\n");
5030 }
5031 loop_resync_check:
5032 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
5033 &base_vha->dpc_flags)) {
5034
5035 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5036 "Loop resync scheduled.\n");
5037
5038 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
5039 &base_vha->dpc_flags))) {
5040
5041 qla2x00_loop_resync(base_vha);
5042
5043 clear_bit(LOOP_RESYNC_ACTIVE,
5044 &base_vha->dpc_flags);
5045 }
5046
5047 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5048 "Loop resync end.\n");
5049 }
5050
5051 if (IS_QLAFX00(ha))
5052 goto intr_on_check;
5053
5054 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5055 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5056 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5057 qla2xxx_flash_npiv_conf(base_vha);
5058 }
5059
5060 intr_on_check:
5061 if (!ha->interrupts_on)
5062 ha->isp_ops->enable_intrs(ha);
5063
5064 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5065 &base_vha->dpc_flags)) {
5066 if (ha->beacon_blink_led == 1)
5067 ha->isp_ops->beacon_blink(base_vha);
5068 }
5069
5070 if (!IS_QLAFX00(ha))
5071 qla2x00_do_dpc_all_vps(base_vha);
5072
5073 ha->dpc_active = 0;
5074 end_loop:
5075 set_current_state(TASK_INTERRUPTIBLE);
5076 } /* End of while(1) */
5077 __set_current_state(TASK_RUNNING);
5078
5079 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5080 "DPC handler exiting.\n");
5081
5082 /*
5083 * Make sure that nobody tries to wake us up again.
5084 */
5085 ha->dpc_active = 0;
5086
5087 /* Cleanup any residual CTX SRBs. */
5088 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5089
5090 return 0;
5091 }
5092
5093 void
qla2xxx_wake_dpc(struct scsi_qla_host * vha)5094 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5095 {
5096 struct qla_hw_data *ha = vha->hw;
5097 struct task_struct *t = ha->dpc_thread;
5098
5099 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5100 wake_up_process(t);
5101 }
5102
5103 /*
5104 * qla2x00_rst_aen
5105 * Processes asynchronous reset.
5106 *
5107 * Input:
5108 * ha = adapter block pointer.
5109 */
5110 static void
qla2x00_rst_aen(scsi_qla_host_t * vha)5111 qla2x00_rst_aen(scsi_qla_host_t *vha)
5112 {
5113 if (vha->flags.online && !vha->flags.reset_active &&
5114 !atomic_read(&vha->loop_down_timer) &&
5115 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5116 do {
5117 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5118
5119 /*
5120 * Issue marker command only when we are going to start
5121 * the I/O.
5122 */
5123 vha->marker_needed = 1;
5124 } while (!atomic_read(&vha->loop_down_timer) &&
5125 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
5126 }
5127 }
5128
5129 /**************************************************************************
5130 * qla2x00_timer
5131 *
5132 * Description:
5133 * One second timer
5134 *
5135 * Context: Interrupt
5136 ***************************************************************************/
5137 void
qla2x00_timer(scsi_qla_host_t * vha)5138 qla2x00_timer(scsi_qla_host_t *vha)
5139 {
5140 unsigned long cpu_flags = 0;
5141 int start_dpc = 0;
5142 int index;
5143 srb_t *sp;
5144 uint16_t w;
5145 struct qla_hw_data *ha = vha->hw;
5146 struct req_que *req;
5147
5148 if (ha->flags.eeh_busy) {
5149 ql_dbg(ql_dbg_timer, vha, 0x6000,
5150 "EEH = %d, restarting timer.\n",
5151 ha->flags.eeh_busy);
5152 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5153 return;
5154 }
5155
5156 /*
5157 * Hardware read to raise pending EEH errors during mailbox waits. If
5158 * the read returns -1 then disable the board.
5159 */
5160 if (!pci_channel_offline(ha->pdev)) {
5161 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
5162 qla2x00_check_reg16_for_disconnect(vha, w);
5163 }
5164
5165 /* Make sure qla82xx_watchdog is run only for physical port */
5166 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
5167 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5168 start_dpc++;
5169 if (IS_QLA82XX(ha))
5170 qla82xx_watchdog(vha);
5171 else if (IS_QLA8044(ha))
5172 qla8044_watchdog(vha);
5173 }
5174
5175 if (!vha->vp_idx && IS_QLAFX00(ha))
5176 qlafx00_timer_routine(vha);
5177
5178 /* Loop down handler. */
5179 if (atomic_read(&vha->loop_down_timer) > 0 &&
5180 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5181 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
5182 && vha->flags.online) {
5183
5184 if (atomic_read(&vha->loop_down_timer) ==
5185 vha->loop_down_abort_time) {
5186
5187 ql_log(ql_log_info, vha, 0x6008,
5188 "Loop down - aborting the queues before time expires.\n");
5189
5190 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5191 atomic_set(&vha->loop_state, LOOP_DEAD);
5192
5193 /*
5194 * Schedule an ISP abort to return any FCP2-device
5195 * commands.
5196 */
5197 /* NPIV - scan physical port only */
5198 if (!vha->vp_idx) {
5199 spin_lock_irqsave(&ha->hardware_lock,
5200 cpu_flags);
5201 req = ha->req_q_map[0];
5202 for (index = 1;
5203 index < req->num_outstanding_cmds;
5204 index++) {
5205 fc_port_t *sfcp;
5206
5207 sp = req->outstanding_cmds[index];
5208 if (!sp)
5209 continue;
5210 if (sp->type != SRB_SCSI_CMD)
5211 continue;
5212 sfcp = sp->fcport;
5213 if (!(sfcp->flags & FCF_FCP2_DEVICE))
5214 continue;
5215
5216 if (IS_QLA82XX(ha))
5217 set_bit(FCOE_CTX_RESET_NEEDED,
5218 &vha->dpc_flags);
5219 else
5220 set_bit(ISP_ABORT_NEEDED,
5221 &vha->dpc_flags);
5222 break;
5223 }
5224 spin_unlock_irqrestore(&ha->hardware_lock,
5225 cpu_flags);
5226 }
5227 start_dpc++;
5228 }
5229
5230 /* if the loop has been down for 4 minutes, reinit adapter */
5231 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
5232 if (!(vha->device_flags & DFLG_NO_CABLE)) {
5233 ql_log(ql_log_warn, vha, 0x6009,
5234 "Loop down - aborting ISP.\n");
5235
5236 if (IS_QLA82XX(ha))
5237 set_bit(FCOE_CTX_RESET_NEEDED,
5238 &vha->dpc_flags);
5239 else
5240 set_bit(ISP_ABORT_NEEDED,
5241 &vha->dpc_flags);
5242 }
5243 }
5244 ql_dbg(ql_dbg_timer, vha, 0x600a,
5245 "Loop down - seconds remaining %d.\n",
5246 atomic_read(&vha->loop_down_timer));
5247 }
5248 /* Check if beacon LED needs to be blinked for physical host only */
5249 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
5250 /* There is no beacon_blink function for ISP82xx */
5251 if (!IS_P3P_TYPE(ha)) {
5252 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5253 start_dpc++;
5254 }
5255 }
5256
5257 /* Process any deferred work. */
5258 if (!list_empty(&vha->work_list))
5259 start_dpc++;
5260
5261 /* Schedule the DPC routine if needed */
5262 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5263 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5264 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
5265 start_dpc ||
5266 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5267 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
5268 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5269 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
5270 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
5271 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
5272 ql_dbg(ql_dbg_timer, vha, 0x600b,
5273 "isp_abort_needed=%d loop_resync_needed=%d "
5274 "fcport_update_needed=%d start_dpc=%d "
5275 "reset_marker_needed=%d",
5276 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5277 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5278 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5279 start_dpc,
5280 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5281 ql_dbg(ql_dbg_timer, vha, 0x600c,
5282 "beacon_blink_needed=%d isp_unrecoverable=%d "
5283 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
5284 "relogin_needed=%d.\n",
5285 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5286 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5287 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5288 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
5289 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
5290 qla2xxx_wake_dpc(vha);
5291 }
5292
5293 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5294 }
5295
5296 /* Firmware interface routines. */
5297
5298 #define FW_BLOBS 11
5299 #define FW_ISP21XX 0
5300 #define FW_ISP22XX 1
5301 #define FW_ISP2300 2
5302 #define FW_ISP2322 3
5303 #define FW_ISP24XX 4
5304 #define FW_ISP25XX 5
5305 #define FW_ISP81XX 6
5306 #define FW_ISP82XX 7
5307 #define FW_ISP2031 8
5308 #define FW_ISP8031 9
5309 #define FW_ISP27XX 10
5310
5311 #define FW_FILE_ISP21XX "ql2100_fw.bin"
5312 #define FW_FILE_ISP22XX "ql2200_fw.bin"
5313 #define FW_FILE_ISP2300 "ql2300_fw.bin"
5314 #define FW_FILE_ISP2322 "ql2322_fw.bin"
5315 #define FW_FILE_ISP24XX "ql2400_fw.bin"
5316 #define FW_FILE_ISP25XX "ql2500_fw.bin"
5317 #define FW_FILE_ISP81XX "ql8100_fw.bin"
5318 #define FW_FILE_ISP82XX "ql8200_fw.bin"
5319 #define FW_FILE_ISP2031 "ql2600_fw.bin"
5320 #define FW_FILE_ISP8031 "ql8300_fw.bin"
5321 #define FW_FILE_ISP27XX "ql2700_fw.bin"
5322
5323
5324 static DEFINE_MUTEX(qla_fw_lock);
5325
5326 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
5327 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5328 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5329 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5330 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5331 { .name = FW_FILE_ISP24XX, },
5332 { .name = FW_FILE_ISP25XX, },
5333 { .name = FW_FILE_ISP81XX, },
5334 { .name = FW_FILE_ISP82XX, },
5335 { .name = FW_FILE_ISP2031, },
5336 { .name = FW_FILE_ISP8031, },
5337 { .name = FW_FILE_ISP27XX, },
5338 };
5339
5340 struct fw_blob *
qla2x00_request_firmware(scsi_qla_host_t * vha)5341 qla2x00_request_firmware(scsi_qla_host_t *vha)
5342 {
5343 struct qla_hw_data *ha = vha->hw;
5344 struct fw_blob *blob;
5345
5346 if (IS_QLA2100(ha)) {
5347 blob = &qla_fw_blobs[FW_ISP21XX];
5348 } else if (IS_QLA2200(ha)) {
5349 blob = &qla_fw_blobs[FW_ISP22XX];
5350 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5351 blob = &qla_fw_blobs[FW_ISP2300];
5352 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5353 blob = &qla_fw_blobs[FW_ISP2322];
5354 } else if (IS_QLA24XX_TYPE(ha)) {
5355 blob = &qla_fw_blobs[FW_ISP24XX];
5356 } else if (IS_QLA25XX(ha)) {
5357 blob = &qla_fw_blobs[FW_ISP25XX];
5358 } else if (IS_QLA81XX(ha)) {
5359 blob = &qla_fw_blobs[FW_ISP81XX];
5360 } else if (IS_QLA82XX(ha)) {
5361 blob = &qla_fw_blobs[FW_ISP82XX];
5362 } else if (IS_QLA2031(ha)) {
5363 blob = &qla_fw_blobs[FW_ISP2031];
5364 } else if (IS_QLA8031(ha)) {
5365 blob = &qla_fw_blobs[FW_ISP8031];
5366 } else if (IS_QLA27XX(ha)) {
5367 blob = &qla_fw_blobs[FW_ISP27XX];
5368 } else {
5369 return NULL;
5370 }
5371
5372 mutex_lock(&qla_fw_lock);
5373 if (blob->fw)
5374 goto out;
5375
5376 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
5377 ql_log(ql_log_warn, vha, 0x0063,
5378 "Failed to load firmware image (%s).\n", blob->name);
5379 blob->fw = NULL;
5380 blob = NULL;
5381 goto out;
5382 }
5383
5384 out:
5385 mutex_unlock(&qla_fw_lock);
5386 return blob;
5387 }
5388
5389 static void
qla2x00_release_firmware(void)5390 qla2x00_release_firmware(void)
5391 {
5392 int idx;
5393
5394 mutex_lock(&qla_fw_lock);
5395 for (idx = 0; idx < FW_BLOBS; idx++)
5396 release_firmware(qla_fw_blobs[idx].fw);
5397 mutex_unlock(&qla_fw_lock);
5398 }
5399
5400 static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)5401 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5402 {
5403 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5404 struct qla_hw_data *ha = vha->hw;
5405
5406 ql_dbg(ql_dbg_aer, vha, 0x9000,
5407 "PCI error detected, state %x.\n", state);
5408
5409 switch (state) {
5410 case pci_channel_io_normal:
5411 ha->flags.eeh_busy = 0;
5412 return PCI_ERS_RESULT_CAN_RECOVER;
5413 case pci_channel_io_frozen:
5414 ha->flags.eeh_busy = 1;
5415 /* For ISP82XX complete any pending mailbox cmd */
5416 if (IS_QLA82XX(ha)) {
5417 ha->flags.isp82xx_fw_hung = 1;
5418 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5419 qla82xx_clear_pending_mbx(vha);
5420 }
5421 qla2x00_free_irqs(vha);
5422 pci_disable_device(pdev);
5423 /* Return back all IOs */
5424 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5425 return PCI_ERS_RESULT_NEED_RESET;
5426 case pci_channel_io_perm_failure:
5427 ha->flags.pci_channel_io_perm_failure = 1;
5428 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
5429 return PCI_ERS_RESULT_DISCONNECT;
5430 }
5431 return PCI_ERS_RESULT_NEED_RESET;
5432 }
5433
5434 static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)5435 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5436 {
5437 int risc_paused = 0;
5438 uint32_t stat;
5439 unsigned long flags;
5440 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5441 struct qla_hw_data *ha = base_vha->hw;
5442 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5443 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5444
5445 if (IS_QLA82XX(ha))
5446 return PCI_ERS_RESULT_RECOVERED;
5447
5448 spin_lock_irqsave(&ha->hardware_lock, flags);
5449 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5450 stat = RD_REG_DWORD(®->hccr);
5451 if (stat & HCCR_RISC_PAUSE)
5452 risc_paused = 1;
5453 } else if (IS_QLA23XX(ha)) {
5454 stat = RD_REG_DWORD(®->u.isp2300.host_status);
5455 if (stat & HSR_RISC_PAUSED)
5456 risc_paused = 1;
5457 } else if (IS_FWI2_CAPABLE(ha)) {
5458 stat = RD_REG_DWORD(®24->host_status);
5459 if (stat & HSRX_RISC_PAUSED)
5460 risc_paused = 1;
5461 }
5462 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5463
5464 if (risc_paused) {
5465 ql_log(ql_log_info, base_vha, 0x9003,
5466 "RISC paused -- mmio_enabled, Dumping firmware.\n");
5467 ha->isp_ops->fw_dump(base_vha, 0);
5468
5469 return PCI_ERS_RESULT_NEED_RESET;
5470 } else
5471 return PCI_ERS_RESULT_RECOVERED;
5472 }
5473
5474 static uint32_t
qla82xx_error_recovery(scsi_qla_host_t * base_vha)5475 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
5476 {
5477 uint32_t rval = QLA_FUNCTION_FAILED;
5478 uint32_t drv_active = 0;
5479 struct qla_hw_data *ha = base_vha->hw;
5480 int fn;
5481 struct pci_dev *other_pdev = NULL;
5482
5483 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5484 "Entered %s.\n", __func__);
5485
5486 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5487
5488 if (base_vha->flags.online) {
5489 /* Abort all outstanding commands,
5490 * so as to be requeued later */
5491 qla2x00_abort_isp_cleanup(base_vha);
5492 }
5493
5494
5495 fn = PCI_FUNC(ha->pdev->devfn);
5496 while (fn > 0) {
5497 fn--;
5498 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5499 "Finding pci device at function = 0x%x.\n", fn);
5500 other_pdev =
5501 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5502 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5503 fn));
5504
5505 if (!other_pdev)
5506 continue;
5507 if (atomic_read(&other_pdev->enable_cnt)) {
5508 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5509 "Found PCI func available and enable at 0x%x.\n",
5510 fn);
5511 pci_dev_put(other_pdev);
5512 break;
5513 }
5514 pci_dev_put(other_pdev);
5515 }
5516
5517 if (!fn) {
5518 /* Reset owner */
5519 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5520 "This devfn is reset owner = 0x%x.\n",
5521 ha->pdev->devfn);
5522 qla82xx_idc_lock(ha);
5523
5524 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5525 QLA8XXX_DEV_INITIALIZING);
5526
5527 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5528 QLA82XX_IDC_VERSION);
5529
5530 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
5531 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5532 "drv_active = 0x%x.\n", drv_active);
5533
5534 qla82xx_idc_unlock(ha);
5535 /* Reset if device is not already reset
5536 * drv_active would be 0 if a reset has already been done
5537 */
5538 if (drv_active)
5539 rval = qla82xx_start_firmware(base_vha);
5540 else
5541 rval = QLA_SUCCESS;
5542 qla82xx_idc_lock(ha);
5543
5544 if (rval != QLA_SUCCESS) {
5545 ql_log(ql_log_info, base_vha, 0x900b,
5546 "HW State: FAILED.\n");
5547 qla82xx_clear_drv_active(ha);
5548 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5549 QLA8XXX_DEV_FAILED);
5550 } else {
5551 ql_log(ql_log_info, base_vha, 0x900c,
5552 "HW State: READY.\n");
5553 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5554 QLA8XXX_DEV_READY);
5555 qla82xx_idc_unlock(ha);
5556 ha->flags.isp82xx_fw_hung = 0;
5557 rval = qla82xx_restart_isp(base_vha);
5558 qla82xx_idc_lock(ha);
5559 /* Clear driver state register */
5560 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5561 qla82xx_set_drv_active(base_vha);
5562 }
5563 qla82xx_idc_unlock(ha);
5564 } else {
5565 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5566 "This devfn is not reset owner = 0x%x.\n",
5567 ha->pdev->devfn);
5568 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
5569 QLA8XXX_DEV_READY)) {
5570 ha->flags.isp82xx_fw_hung = 0;
5571 rval = qla82xx_restart_isp(base_vha);
5572 qla82xx_idc_lock(ha);
5573 qla82xx_set_drv_active(base_vha);
5574 qla82xx_idc_unlock(ha);
5575 }
5576 }
5577 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5578
5579 return rval;
5580 }
5581
5582 static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev * pdev)5583 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5584 {
5585 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
5586 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5587 struct qla_hw_data *ha = base_vha->hw;
5588 struct rsp_que *rsp;
5589 int rc, retries = 10;
5590
5591 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5592 "Slot Reset.\n");
5593
5594 /* Workaround: qla2xxx driver which access hardware earlier
5595 * needs error state to be pci_channel_io_online.
5596 * Otherwise mailbox command timesout.
5597 */
5598 pdev->error_state = pci_channel_io_normal;
5599
5600 pci_restore_state(pdev);
5601
5602 /* pci_restore_state() clears the saved_state flag of the device
5603 * save restored state which resets saved_state flag
5604 */
5605 pci_save_state(pdev);
5606
5607 if (ha->mem_only)
5608 rc = pci_enable_device_mem(pdev);
5609 else
5610 rc = pci_enable_device(pdev);
5611
5612 if (rc) {
5613 ql_log(ql_log_warn, base_vha, 0x9005,
5614 "Can't re-enable PCI device after reset.\n");
5615 goto exit_slot_reset;
5616 }
5617
5618 rsp = ha->rsp_q_map[0];
5619 if (qla2x00_request_irqs(ha, rsp))
5620 goto exit_slot_reset;
5621
5622 if (ha->isp_ops->pci_config(base_vha))
5623 goto exit_slot_reset;
5624
5625 if (IS_QLA82XX(ha)) {
5626 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5627 ret = PCI_ERS_RESULT_RECOVERED;
5628 goto exit_slot_reset;
5629 } else
5630 goto exit_slot_reset;
5631 }
5632
5633 while (ha->flags.mbox_busy && retries--)
5634 msleep(1000);
5635
5636 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5637 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
5638 ret = PCI_ERS_RESULT_RECOVERED;
5639 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5640
5641
5642 exit_slot_reset:
5643 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5644 "slot_reset return %x.\n", ret);
5645
5646 return ret;
5647 }
5648
5649 static void
qla2xxx_pci_resume(struct pci_dev * pdev)5650 qla2xxx_pci_resume(struct pci_dev *pdev)
5651 {
5652 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5653 struct qla_hw_data *ha = base_vha->hw;
5654 int ret;
5655
5656 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5657 "pci_resume.\n");
5658
5659 ret = qla2x00_wait_for_hba_online(base_vha);
5660 if (ret != QLA_SUCCESS) {
5661 ql_log(ql_log_fatal, base_vha, 0x9002,
5662 "The device failed to resume I/O from slot/link_reset.\n");
5663 }
5664
5665 pci_cleanup_aer_uncorrect_error_status(pdev);
5666
5667 ha->flags.eeh_busy = 0;
5668 }
5669
5670 static void
qla83xx_disable_laser(scsi_qla_host_t * vha)5671 qla83xx_disable_laser(scsi_qla_host_t *vha)
5672 {
5673 uint32_t reg, data, fn;
5674 struct qla_hw_data *ha = vha->hw;
5675 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5676
5677 /* pci func #/port # */
5678 ql_dbg(ql_dbg_init, vha, 0x004b,
5679 "Disabling Laser for hba: %p\n", vha);
5680
5681 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5682 (BIT_15|BIT_14|BIT_13|BIT_12));
5683
5684 fn = (fn >> 12);
5685
5686 if (fn & 1)
5687 reg = PORT_1_2031;
5688 else
5689 reg = PORT_0_2031;
5690
5691 data = LASER_OFF_2031;
5692
5693 qla83xx_wr_reg(vha, reg, data);
5694 }
5695
5696 static const struct pci_error_handlers qla2xxx_err_handler = {
5697 .error_detected = qla2xxx_pci_error_detected,
5698 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5699 .slot_reset = qla2xxx_pci_slot_reset,
5700 .resume = qla2xxx_pci_resume,
5701 };
5702
5703 static struct pci_device_id qla2xxx_pci_tbl[] = {
5704 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5705 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5707 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5708 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
5713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
5714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
5716 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
5717 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
5718 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
5719 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5720 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5721 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
5722 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5723 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
5724 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5725 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5726 { 0 },
5727 };
5728 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5729
5730 static struct pci_driver qla2xxx_pci_driver = {
5731 .name = QLA2XXX_DRIVER_NAME,
5732 .driver = {
5733 .owner = THIS_MODULE,
5734 },
5735 .id_table = qla2xxx_pci_tbl,
5736 .probe = qla2x00_probe_one,
5737 .remove = qla2x00_remove_one,
5738 .shutdown = qla2x00_shutdown,
5739 .err_handler = &qla2xxx_err_handler,
5740 };
5741
5742 static const struct file_operations apidev_fops = {
5743 .owner = THIS_MODULE,
5744 .llseek = noop_llseek,
5745 };
5746
5747 /**
5748 * qla2x00_module_init - Module initialization.
5749 **/
5750 static int __init
qla2x00_module_init(void)5751 qla2x00_module_init(void)
5752 {
5753 int ret = 0;
5754
5755 /* Allocate cache for SRBs. */
5756 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
5757 SLAB_HWCACHE_ALIGN, NULL);
5758 if (srb_cachep == NULL) {
5759 ql_log(ql_log_fatal, NULL, 0x0001,
5760 "Unable to allocate SRB cache...Failing load!.\n");
5761 return -ENOMEM;
5762 }
5763
5764 /* Initialize target kmem_cache and mem_pools */
5765 ret = qlt_init();
5766 if (ret < 0) {
5767 goto destroy_cache;
5768 } else if (ret > 0) {
5769 /*
5770 * If initiator mode is explictly disabled by qlt_init(),
5771 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5772 * performing scsi_scan_target() during LOOP UP event.
5773 */
5774 qla2xxx_transport_functions.disable_target_scan = 1;
5775 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5776 }
5777
5778 /* Derive version string. */
5779 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
5780 if (ql2xextended_error_logging)
5781 strcat(qla2x00_version_str, "-debug");
5782
5783 qla2xxx_transport_template =
5784 fc_attach_transport(&qla2xxx_transport_functions);
5785 if (!qla2xxx_transport_template) {
5786 ql_log(ql_log_fatal, NULL, 0x0002,
5787 "fc_attach_transport failed...Failing load!.\n");
5788 ret = -ENODEV;
5789 goto qlt_exit;
5790 }
5791
5792 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5793 if (apidev_major < 0) {
5794 ql_log(ql_log_fatal, NULL, 0x0003,
5795 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
5796 }
5797
5798 qla2xxx_transport_vport_template =
5799 fc_attach_transport(&qla2xxx_transport_vport_functions);
5800 if (!qla2xxx_transport_vport_template) {
5801 ql_log(ql_log_fatal, NULL, 0x0004,
5802 "fc_attach_transport vport failed...Failing load!.\n");
5803 ret = -ENODEV;
5804 goto unreg_chrdev;
5805 }
5806 ql_log(ql_log_info, NULL, 0x0005,
5807 "QLogic Fibre Channel HBA Driver: %s.\n",
5808 qla2x00_version_str);
5809 ret = pci_register_driver(&qla2xxx_pci_driver);
5810 if (ret) {
5811 ql_log(ql_log_fatal, NULL, 0x0006,
5812 "pci_register_driver failed...ret=%d Failing load!.\n",
5813 ret);
5814 goto release_vport_transport;
5815 }
5816 return ret;
5817
5818 release_vport_transport:
5819 fc_release_transport(qla2xxx_transport_vport_template);
5820
5821 unreg_chrdev:
5822 if (apidev_major >= 0)
5823 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
5824 fc_release_transport(qla2xxx_transport_template);
5825
5826 qlt_exit:
5827 qlt_exit();
5828
5829 destroy_cache:
5830 kmem_cache_destroy(srb_cachep);
5831 return ret;
5832 }
5833
5834 /**
5835 * qla2x00_module_exit - Module cleanup.
5836 **/
5837 static void __exit
qla2x00_module_exit(void)5838 qla2x00_module_exit(void)
5839 {
5840 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
5841 pci_unregister_driver(&qla2xxx_pci_driver);
5842 qla2x00_release_firmware();
5843 kmem_cache_destroy(srb_cachep);
5844 qlt_exit();
5845 if (ctx_cachep)
5846 kmem_cache_destroy(ctx_cachep);
5847 fc_release_transport(qla2xxx_transport_template);
5848 fc_release_transport(qla2xxx_transport_vport_template);
5849 }
5850
5851 module_init(qla2x00_module_init);
5852 module_exit(qla2x00_module_exit);
5853
5854 MODULE_AUTHOR("QLogic Corporation");
5855 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5856 MODULE_LICENSE("GPL");
5857 MODULE_VERSION(QLA2XXX_VERSION);
5858 MODULE_FIRMWARE(FW_FILE_ISP21XX);
5859 MODULE_FIRMWARE(FW_FILE_ISP22XX);
5860 MODULE_FIRMWARE(FW_FILE_ISP2300);
5861 MODULE_FIRMWARE(FW_FILE_ISP2322);
5862 MODULE_FIRMWARE(FW_FILE_ISP24XX);
5863 MODULE_FIRMWARE(FW_FILE_ISP25XX);
5864 MODULE_FIRMWARE(FW_FILE_ISP2031);
5865 MODULE_FIRMWARE(FW_FILE_ISP8031);
5866 MODULE_FIRMWARE(FW_FILE_ISP27XX);
5867