1 /*
2 * Driver for Broadcom BCM2835 auxiliary SPI Controllers
3 *
4 * the driver does not rely on the native chipselects at all
5 * but only uses the gpio type chipselects
6 *
7 * Based on: spi-bcm2835.c
8 *
9 * Copyright (C) 2015 Martin Sperl
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22 #include <linux/clk.h>
23 #include <linux/completion.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/of.h>
31 #include <linux/of_address.h>
32 #include <linux/of_device.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_irq.h>
35 #include <linux/regmap.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spinlock.h>
38
39 /*
40 * spi register defines
41 *
42 * note there is garbage in the "official" documentation,
43 * so some data is taken from the file:
44 * brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
45 * inside of:
46 * http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
47 */
48
49 /* SPI register offsets */
50 #define BCM2835_AUX_SPI_CNTL0 0x00
51 #define BCM2835_AUX_SPI_CNTL1 0x04
52 #define BCM2835_AUX_SPI_STAT 0x08
53 #define BCM2835_AUX_SPI_PEEK 0x0C
54 #define BCM2835_AUX_SPI_IO 0x20
55 #define BCM2835_AUX_SPI_TXHOLD 0x30
56
57 /* Bitfields in CNTL0 */
58 #define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000
59 #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF
60 #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20
61 #define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000
62 #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000
63 #define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000
64 #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
65 #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000
66 #define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800
67 #define BCM2835_AUX_SPI_CNTL0_CPHA_IN 0x00000400
68 #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
69 #define BCM2835_AUX_SPI_CNTL0_CPHA_OUT 0x00000100
70 #define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080
71 #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040
72 #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F
73
74 /* Bitfields in CNTL1 */
75 #define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700
76 #define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000080
77 #define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000040
78 #define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002
79 #define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001
80
81 /* Bitfields in STAT */
82 #define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000
83 #define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000
84 #define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400
85 #define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200
86 #define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100
87 #define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080
88 #define BCM2835_AUX_SPI_STAT_BUSY 0x00000040
89 #define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F
90
91 /* timeout values */
92 #define BCM2835_AUX_SPI_POLLING_LIMIT_US 30
93 #define BCM2835_AUX_SPI_POLLING_JIFFIES 2
94
95 #define BCM2835_AUX_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
96 | SPI_NO_CS)
97
98 struct bcm2835aux_spi {
99 void __iomem *regs;
100 struct clk *clk;
101 int irq;
102 u32 cntl[2];
103 const u8 *tx_buf;
104 u8 *rx_buf;
105 int tx_len;
106 int rx_len;
107 int pending;
108 };
109
bcm2835aux_rd(struct bcm2835aux_spi * bs,unsigned reg)110 static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg)
111 {
112 return readl(bs->regs + reg);
113 }
114
bcm2835aux_wr(struct bcm2835aux_spi * bs,unsigned reg,u32 val)115 static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg,
116 u32 val)
117 {
118 writel(val, bs->regs + reg);
119 }
120
bcm2835aux_rd_fifo(struct bcm2835aux_spi * bs)121 static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
122 {
123 u32 data;
124 int count = min(bs->rx_len, 3);
125
126 data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
127 if (bs->rx_buf) {
128 switch (count) {
129 case 4:
130 *bs->rx_buf++ = (data >> 24) & 0xff;
131 /* fallthrough */
132 case 3:
133 *bs->rx_buf++ = (data >> 16) & 0xff;
134 /* fallthrough */
135 case 2:
136 *bs->rx_buf++ = (data >> 8) & 0xff;
137 /* fallthrough */
138 case 1:
139 *bs->rx_buf++ = (data >> 0) & 0xff;
140 /* fallthrough - no default */
141 }
142 }
143 bs->rx_len -= count;
144 bs->pending -= count;
145 }
146
bcm2835aux_wr_fifo(struct bcm2835aux_spi * bs)147 static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
148 {
149 u32 data;
150 u8 byte;
151 int count;
152 int i;
153
154 /* gather up to 3 bytes to write to the FIFO */
155 count = min(bs->tx_len, 3);
156 data = 0;
157 for (i = 0; i < count; i++) {
158 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
159 data |= byte << (8 * (2 - i));
160 }
161
162 /* and set the variable bit-length */
163 data |= (count * 8) << 24;
164
165 /* and decrement length */
166 bs->tx_len -= count;
167 bs->pending += count;
168
169 /* write to the correct TX-register */
170 if (bs->tx_len)
171 bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
172 else
173 bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
174 }
175
bcm2835aux_spi_reset_hw(struct bcm2835aux_spi * bs)176 static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
177 {
178 /* disable spi clearing fifo and interrupts */
179 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
180 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
181 BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
182 }
183
bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi * bs)184 static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
185 {
186 u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);
187
188 /* check if we have data to read */
189 for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);
190 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))
191 bcm2835aux_rd_fifo(bs);
192
193 /* check if we have data to write */
194 while (bs->tx_len &&
195 (bs->pending < 12) &&
196 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
197 BCM2835_AUX_SPI_STAT_TX_FULL))) {
198 bcm2835aux_wr_fifo(bs);
199 }
200 }
201
bcm2835aux_spi_interrupt(int irq,void * dev_id)202 static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
203 {
204 struct spi_master *master = dev_id;
205 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
206
207 /* IRQ may be shared, so return if our interrupts are disabled */
208 if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
209 (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
210 return IRQ_NONE;
211
212 /* do common fifo handling */
213 bcm2835aux_spi_transfer_helper(bs);
214
215 /* and if rx_len is 0 then wake up completion and disable spi */
216 if (!bs->rx_len) {
217 bcm2835aux_spi_reset_hw(bs);
218 complete(&master->xfer_completion);
219 }
220
221 return IRQ_HANDLED;
222 }
223
__bcm2835aux_spi_transfer_one_irq(struct spi_master * master,struct spi_device * spi,struct spi_transfer * tfr)224 static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
225 struct spi_device *spi,
226 struct spi_transfer *tfr)
227 {
228 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
229
230 /* enable interrupts */
231 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
232 BCM2835_AUX_SPI_CNTL1_TXEMPTY |
233 BCM2835_AUX_SPI_CNTL1_IDLE);
234
235 /* and wait for finish... */
236 return 1;
237 }
238
bcm2835aux_spi_transfer_one_irq(struct spi_master * master,struct spi_device * spi,struct spi_transfer * tfr)239 static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
240 struct spi_device *spi,
241 struct spi_transfer *tfr)
242 {
243 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
244
245 /* fill in registers and fifos before enabling interrupts */
246 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
247 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
248
249 /* fill in tx fifo with data before enabling interrupts */
250 while ((bs->tx_len) &&
251 (bs->pending < 12) &&
252 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
253 BCM2835_AUX_SPI_STAT_TX_FULL))) {
254 bcm2835aux_wr_fifo(bs);
255 }
256
257 /* now run the interrupt mode */
258 return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
259 }
260
bcm2835aux_spi_transfer_one_poll(struct spi_master * master,struct spi_device * spi,struct spi_transfer * tfr)261 static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
262 struct spi_device *spi,
263 struct spi_transfer *tfr)
264 {
265 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
266 unsigned long timeout;
267
268 /* configure spi */
269 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
270 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
271
272 /* set the timeout */
273 timeout = jiffies + BCM2835_AUX_SPI_POLLING_JIFFIES;
274
275 /* loop until finished the transfer */
276 while (bs->rx_len) {
277
278 /* do common fifo handling */
279 bcm2835aux_spi_transfer_helper(bs);
280
281 /* there is still data pending to read check the timeout */
282 if (bs->rx_len && time_after(jiffies, timeout)) {
283 dev_dbg_ratelimited(&spi->dev,
284 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
285 jiffies - timeout,
286 bs->tx_len, bs->rx_len);
287 /* forward to interrupt handler */
288 return __bcm2835aux_spi_transfer_one_irq(master,
289 spi, tfr);
290 }
291 }
292
293 /* Transfer complete - reset SPI HW */
294 bcm2835aux_spi_reset_hw(bs);
295
296 /* and return without waiting for completion */
297 return 0;
298 }
299
bcm2835aux_spi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * tfr)300 static int bcm2835aux_spi_transfer_one(struct spi_master *master,
301 struct spi_device *spi,
302 struct spi_transfer *tfr)
303 {
304 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
305 unsigned long spi_hz, clk_hz, speed;
306 unsigned long spi_used_hz;
307 unsigned long long xfer_time_us;
308
309 /* calculate the registers to handle
310 *
311 * note that we use the variable data mode, which
312 * is not optimal for longer transfers as we waste registers
313 * resulting (potentially) in more interrupts when transferring
314 * more than 12 bytes
315 */
316 bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
317 BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
318 BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
319 bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
320
321 /* set clock */
322 spi_hz = tfr->speed_hz;
323 clk_hz = clk_get_rate(bs->clk);
324
325 if (spi_hz >= clk_hz / 2) {
326 speed = 0;
327 } else if (spi_hz) {
328 speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
329 if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
330 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
331 } else { /* the slowest we can go */
332 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
333 }
334 bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
335
336 spi_used_hz = clk_hz / (2 * (speed + 1));
337
338 /* handle all the modes */
339 if (spi->mode & SPI_CPOL)
340 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
341 if (spi->mode & SPI_CPHA)
342 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT |
343 BCM2835_AUX_SPI_CNTL0_CPHA_IN;
344
345 /* set transmit buffers and length */
346 bs->tx_buf = tfr->tx_buf;
347 bs->rx_buf = tfr->rx_buf;
348 bs->tx_len = tfr->len;
349 bs->rx_len = tfr->len;
350 bs->pending = 0;
351
352 /* calculate the estimated time in us the transfer runs
353 * note that there are are 2 idle clocks after each
354 * chunk getting transferred - in our case the chunk size
355 * is 3 bytes, so we approximate this by 9 bits/byte
356 */
357 xfer_time_us = tfr->len * 9 * 1000000;
358 do_div(xfer_time_us, spi_used_hz);
359
360 /* run in polling mode for short transfers */
361 if (xfer_time_us < BCM2835_AUX_SPI_POLLING_LIMIT_US)
362 return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);
363
364 /* run in interrupt mode for all others */
365 return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
366 }
367
bcm2835aux_spi_handle_err(struct spi_master * master,struct spi_message * msg)368 static void bcm2835aux_spi_handle_err(struct spi_master *master,
369 struct spi_message *msg)
370 {
371 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
372
373 bcm2835aux_spi_reset_hw(bs);
374 }
375
bcm2835aux_spi_probe(struct platform_device * pdev)376 static int bcm2835aux_spi_probe(struct platform_device *pdev)
377 {
378 struct spi_master *master;
379 struct bcm2835aux_spi *bs;
380 struct resource *res;
381 unsigned long clk_hz;
382 int err;
383
384 master = devm_spi_alloc_master(&pdev->dev, sizeof(*bs));
385 if (!master) {
386 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
387 return -ENOMEM;
388 }
389
390 platform_set_drvdata(pdev, master);
391 master->mode_bits = BCM2835_AUX_SPI_MODE_BITS;
392 master->bits_per_word_mask = SPI_BPW_MASK(8);
393 /* even though the driver never officially supported native CS
394 * allow a single native CS for legacy DT support purposes when
395 * no cs-gpio is configured.
396 * Known limitations for native cs are:
397 * * multiple chip-selects: cs0-cs2 are all simultaniously asserted
398 * whenever there is a transfer - this even includes SPI_NO_CS
399 * * SPI_CS_HIGH: is ignores - cs are always asserted low
400 * * cs_change: cs is deasserted after each spi_transfer
401 * * cs_delay_usec: cs is always deasserted one SCK cycle after
402 * a spi_transfer
403 */
404 master->num_chipselect = 1;
405 master->transfer_one = bcm2835aux_spi_transfer_one;
406 master->handle_err = bcm2835aux_spi_handle_err;
407 master->dev.of_node = pdev->dev.of_node;
408
409 bs = spi_master_get_devdata(master);
410
411 /* the main area */
412 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
413 bs->regs = devm_ioremap_resource(&pdev->dev, res);
414 if (IS_ERR(bs->regs))
415 return PTR_ERR(bs->regs);
416
417 bs->clk = devm_clk_get(&pdev->dev, NULL);
418 if ((!bs->clk) || (IS_ERR(bs->clk))) {
419 err = PTR_ERR(bs->clk);
420 dev_err(&pdev->dev, "could not get clk: %d\n", err);
421 return err;
422 }
423
424 bs->irq = platform_get_irq(pdev, 0);
425 if (bs->irq <= 0) {
426 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
427 return bs->irq ? bs->irq : -ENODEV;
428 }
429
430 /* this also enables the HW block */
431 err = clk_prepare_enable(bs->clk);
432 if (err) {
433 dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
434 return err;
435 }
436
437 /* just checking if the clock returns a sane value */
438 clk_hz = clk_get_rate(bs->clk);
439 if (!clk_hz) {
440 dev_err(&pdev->dev, "clock returns 0 Hz\n");
441 err = -ENODEV;
442 goto out_clk_disable;
443 }
444
445 /* reset SPI-HW block */
446 bcm2835aux_spi_reset_hw(bs);
447
448 err = devm_request_irq(&pdev->dev, bs->irq,
449 bcm2835aux_spi_interrupt,
450 IRQF_SHARED,
451 dev_name(&pdev->dev), master);
452 if (err) {
453 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
454 goto out_clk_disable;
455 }
456
457 err = spi_register_master(master);
458 if (err) {
459 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
460 goto out_clk_disable;
461 }
462
463 return 0;
464
465 out_clk_disable:
466 clk_disable_unprepare(bs->clk);
467 return err;
468 }
469
bcm2835aux_spi_remove(struct platform_device * pdev)470 static int bcm2835aux_spi_remove(struct platform_device *pdev)
471 {
472 struct spi_master *master = platform_get_drvdata(pdev);
473 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
474
475 spi_unregister_master(master);
476
477 bcm2835aux_spi_reset_hw(bs);
478
479 /* disable the HW block by releasing the clock */
480 clk_disable_unprepare(bs->clk);
481
482 return 0;
483 }
484
485 static const struct of_device_id bcm2835aux_spi_match[] = {
486 { .compatible = "brcm,bcm2835-aux-spi", },
487 {}
488 };
489 MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);
490
491 static struct platform_driver bcm2835aux_spi_driver = {
492 .driver = {
493 .name = "spi-bcm2835aux",
494 .of_match_table = bcm2835aux_spi_match,
495 },
496 .probe = bcm2835aux_spi_probe,
497 .remove = bcm2835aux_spi_remove,
498 };
499 module_platform_driver(bcm2835aux_spi_driver);
500
501 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
502 MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
503 MODULE_LICENSE("GPL v2");
504