1 /*
2 * SH RSPI driver
3 *
4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
6 *
7 * Based on spi-sh.c:
8 * Copyright (C) 2011 Renesas Solutions Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/of_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/sh_dma.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/rspi.h>
35
36 #define RSPI_SPCR 0x00 /* Control Register */
37 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
38 #define RSPI_SPPCR 0x02 /* Pin Control Register */
39 #define RSPI_SPSR 0x03 /* Status Register */
40 #define RSPI_SPDR 0x04 /* Data Register */
41 #define RSPI_SPSCR 0x08 /* Sequence Control Register */
42 #define RSPI_SPSSR 0x09 /* Sequence Status Register */
43 #define RSPI_SPBR 0x0a /* Bit Rate Register */
44 #define RSPI_SPDCR 0x0b /* Data Control Register */
45 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
46 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
47 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
48 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
49 #define RSPI_SPCMD0 0x10 /* Command Register 0 */
50 #define RSPI_SPCMD1 0x12 /* Command Register 1 */
51 #define RSPI_SPCMD2 0x14 /* Command Register 2 */
52 #define RSPI_SPCMD3 0x16 /* Command Register 3 */
53 #define RSPI_SPCMD4 0x18 /* Command Register 4 */
54 #define RSPI_SPCMD5 0x1a /* Command Register 5 */
55 #define RSPI_SPCMD6 0x1c /* Command Register 6 */
56 #define RSPI_SPCMD7 0x1e /* Command Register 7 */
57 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
58 #define RSPI_NUM_SPCMD 8
59 #define RSPI_RZ_NUM_SPCMD 4
60 #define QSPI_NUM_SPCMD 4
61
62 /* RSPI on RZ only */
63 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
64 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
65
66 /* QSPI only */
67 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
68 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
69 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
70 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
71 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
72 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
73 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
74
75 /* SPCR - Control Register */
76 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
77 #define SPCR_SPE 0x40 /* Function Enable */
78 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
79 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
80 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
81 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
82 /* RSPI on SH only */
83 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
84 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
85 /* QSPI on R-Car Gen2 only */
86 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
87 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
88
89 /* SSLP - Slave Select Polarity Register */
90 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
91 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
92
93 /* SPPCR - Pin Control Register */
94 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
95 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
96 #define SPPCR_SPOM 0x04
97 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
98 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
99
100 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
101 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
102
103 /* SPSR - Status Register */
104 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
105 #define SPSR_TEND 0x40 /* Transmit End */
106 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
107 #define SPSR_PERF 0x08 /* Parity Error Flag */
108 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
109 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
110 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
111
112 /* SPSCR - Sequence Control Register */
113 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
114
115 /* SPSSR - Sequence Status Register */
116 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
117 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
118
119 /* SPDCR - Data Control Register */
120 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
121 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
122 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
123 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
124 #define SPDCR_SPLWORD SPDCR_SPLW1
125 #define SPDCR_SPLBYTE SPDCR_SPLW0
126 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
127 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
128 #define SPDCR_SLSEL1 0x08
129 #define SPDCR_SLSEL0 0x04
130 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
131 #define SPDCR_SPFC1 0x02
132 #define SPDCR_SPFC0 0x01
133 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
134
135 /* SPCKD - Clock Delay Register */
136 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
137
138 /* SSLND - Slave Select Negation Delay Register */
139 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
140
141 /* SPND - Next-Access Delay Register */
142 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
143
144 /* SPCR2 - Control Register 2 */
145 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
146 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
147 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
148 #define SPCR2_SPPE 0x01 /* Parity Enable */
149
150 /* SPCMDn - Command Registers */
151 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
152 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
153 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
154 #define SPCMD_LSBF 0x1000 /* LSB First */
155 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
156 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
157 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
158 #define SPCMD_SPB_16BIT 0x0100
159 #define SPCMD_SPB_20BIT 0x0000
160 #define SPCMD_SPB_24BIT 0x0100
161 #define SPCMD_SPB_32BIT 0x0200
162 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
163 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
164 #define SPCMD_SPIMOD1 0x0040
165 #define SPCMD_SPIMOD0 0x0020
166 #define SPCMD_SPIMOD_SINGLE 0
167 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
168 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
169 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
170 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
171 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
172 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
173 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
174
175 /* SPBFCR - Buffer Control Register */
176 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
177 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
178 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
179 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
180 /* QSPI on R-Car Gen2 */
181 #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */
182 #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */
183 #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */
184 #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */
185
186 #define QSPI_BUFFER_SIZE 32u
187
188 struct rspi_data {
189 void __iomem *addr;
190 u32 max_speed_hz;
191 struct spi_master *master;
192 wait_queue_head_t wait;
193 struct clk *clk;
194 u16 spcmd;
195 u8 spsr;
196 u8 sppcr;
197 int rx_irq, tx_irq;
198 const struct spi_ops *ops;
199
200 unsigned dma_callbacked:1;
201 unsigned byte_access:1;
202 };
203
rspi_write8(const struct rspi_data * rspi,u8 data,u16 offset)204 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
205 {
206 iowrite8(data, rspi->addr + offset);
207 }
208
rspi_write16(const struct rspi_data * rspi,u16 data,u16 offset)209 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
210 {
211 iowrite16(data, rspi->addr + offset);
212 }
213
rspi_write32(const struct rspi_data * rspi,u32 data,u16 offset)214 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
215 {
216 iowrite32(data, rspi->addr + offset);
217 }
218
rspi_read8(const struct rspi_data * rspi,u16 offset)219 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
220 {
221 return ioread8(rspi->addr + offset);
222 }
223
rspi_read16(const struct rspi_data * rspi,u16 offset)224 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
225 {
226 return ioread16(rspi->addr + offset);
227 }
228
rspi_write_data(const struct rspi_data * rspi,u16 data)229 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
230 {
231 if (rspi->byte_access)
232 rspi_write8(rspi, data, RSPI_SPDR);
233 else /* 16 bit */
234 rspi_write16(rspi, data, RSPI_SPDR);
235 }
236
rspi_read_data(const struct rspi_data * rspi)237 static u16 rspi_read_data(const struct rspi_data *rspi)
238 {
239 if (rspi->byte_access)
240 return rspi_read8(rspi, RSPI_SPDR);
241 else /* 16 bit */
242 return rspi_read16(rspi, RSPI_SPDR);
243 }
244
245 /* optional functions */
246 struct spi_ops {
247 int (*set_config_register)(struct rspi_data *rspi, int access_size);
248 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
249 struct spi_transfer *xfer);
250 u16 mode_bits;
251 u16 flags;
252 u16 fifo_size;
253 };
254
255 /*
256 * functions for RSPI on legacy SH
257 */
rspi_set_config_register(struct rspi_data * rspi,int access_size)258 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
259 {
260 int spbr;
261
262 /* Sets output mode, MOSI signal, and (optionally) loopback */
263 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
264
265 /* Sets transfer bit rate */
266 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
267 2 * rspi->max_speed_hz) - 1;
268 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
269
270 /* Disable dummy transmission, set 16-bit word access, 1 frame */
271 rspi_write8(rspi, 0, RSPI_SPDCR);
272 rspi->byte_access = 0;
273
274 /* Sets RSPCK, SSL, next-access delay value */
275 rspi_write8(rspi, 0x00, RSPI_SPCKD);
276 rspi_write8(rspi, 0x00, RSPI_SSLND);
277 rspi_write8(rspi, 0x00, RSPI_SPND);
278
279 /* Sets parity, interrupt mask */
280 rspi_write8(rspi, 0x00, RSPI_SPCR2);
281
282 /* Resets sequencer */
283 rspi_write8(rspi, 0, RSPI_SPSCR);
284 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
285 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
286
287 /* Sets RSPI mode */
288 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
289
290 return 0;
291 }
292
293 /*
294 * functions for RSPI on RZ
295 */
rspi_rz_set_config_register(struct rspi_data * rspi,int access_size)296 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
297 {
298 int spbr;
299
300 /* Sets output mode, MOSI signal, and (optionally) loopback */
301 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
302
303 /* Sets transfer bit rate */
304 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
305 2 * rspi->max_speed_hz) - 1;
306 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
307
308 /* Disable dummy transmission, set byte access */
309 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
310 rspi->byte_access = 1;
311
312 /* Sets RSPCK, SSL, next-access delay value */
313 rspi_write8(rspi, 0x00, RSPI_SPCKD);
314 rspi_write8(rspi, 0x00, RSPI_SSLND);
315 rspi_write8(rspi, 0x00, RSPI_SPND);
316
317 /* Resets sequencer */
318 rspi_write8(rspi, 0, RSPI_SPSCR);
319 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
320 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
321
322 /* Sets RSPI mode */
323 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
324
325 return 0;
326 }
327
328 /*
329 * functions for QSPI
330 */
qspi_set_config_register(struct rspi_data * rspi,int access_size)331 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
332 {
333 int spbr;
334
335 /* Sets output mode, MOSI signal, and (optionally) loopback */
336 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
337
338 /* Sets transfer bit rate */
339 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
340 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
341
342 /* Disable dummy transmission, set byte access */
343 rspi_write8(rspi, 0, RSPI_SPDCR);
344 rspi->byte_access = 1;
345
346 /* Sets RSPCK, SSL, next-access delay value */
347 rspi_write8(rspi, 0x00, RSPI_SPCKD);
348 rspi_write8(rspi, 0x00, RSPI_SSLND);
349 rspi_write8(rspi, 0x00, RSPI_SPND);
350
351 /* Data Length Setting */
352 if (access_size == 8)
353 rspi->spcmd |= SPCMD_SPB_8BIT;
354 else if (access_size == 16)
355 rspi->spcmd |= SPCMD_SPB_16BIT;
356 else
357 rspi->spcmd |= SPCMD_SPB_32BIT;
358
359 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
360
361 /* Resets transfer data length */
362 rspi_write32(rspi, 0, QSPI_SPBMUL0);
363
364 /* Resets transmit and receive buffer */
365 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
366 /* Sets buffer to allow normal operation */
367 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
368
369 /* Resets sequencer */
370 rspi_write8(rspi, 0, RSPI_SPSCR);
371 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
372
373 /* Enables SPI function in master mode */
374 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
375
376 return 0;
377 }
378
qspi_update(const struct rspi_data * rspi,u8 mask,u8 val,u8 reg)379 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
380 {
381 u8 data;
382
383 data = rspi_read8(rspi, reg);
384 data &= ~mask;
385 data |= (val & mask);
386 rspi_write8(rspi, data, reg);
387 }
388
qspi_set_send_trigger(struct rspi_data * rspi,unsigned int len)389 static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
390 unsigned int len)
391 {
392 unsigned int n;
393
394 n = min(len, QSPI_BUFFER_SIZE);
395
396 if (len >= QSPI_BUFFER_SIZE) {
397 /* sets triggering number to 32 bytes */
398 qspi_update(rspi, SPBFCR_TXTRG_MASK,
399 SPBFCR_TXTRG_32B, QSPI_SPBFCR);
400 } else {
401 /* sets triggering number to 1 byte */
402 qspi_update(rspi, SPBFCR_TXTRG_MASK,
403 SPBFCR_TXTRG_1B, QSPI_SPBFCR);
404 }
405
406 return n;
407 }
408
qspi_set_receive_trigger(struct rspi_data * rspi,unsigned int len)409 static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
410 {
411 unsigned int n;
412
413 n = min(len, QSPI_BUFFER_SIZE);
414
415 if (len >= QSPI_BUFFER_SIZE) {
416 /* sets triggering number to 32 bytes */
417 qspi_update(rspi, SPBFCR_RXTRG_MASK,
418 SPBFCR_RXTRG_32B, QSPI_SPBFCR);
419 } else {
420 /* sets triggering number to 1 byte */
421 qspi_update(rspi, SPBFCR_RXTRG_MASK,
422 SPBFCR_RXTRG_1B, QSPI_SPBFCR);
423 }
424 }
425
426 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
427
rspi_enable_irq(const struct rspi_data * rspi,u8 enable)428 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
429 {
430 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
431 }
432
rspi_disable_irq(const struct rspi_data * rspi,u8 disable)433 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
434 {
435 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
436 }
437
rspi_wait_for_interrupt(struct rspi_data * rspi,u8 wait_mask,u8 enable_bit)438 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
439 u8 enable_bit)
440 {
441 int ret;
442
443 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
444 if (rspi->spsr & wait_mask)
445 return 0;
446
447 rspi_enable_irq(rspi, enable_bit);
448 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
449 if (ret == 0 && !(rspi->spsr & wait_mask))
450 return -ETIMEDOUT;
451
452 return 0;
453 }
454
rspi_wait_for_tx_empty(struct rspi_data * rspi)455 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
456 {
457 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
458 }
459
rspi_wait_for_rx_full(struct rspi_data * rspi)460 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
461 {
462 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
463 }
464
rspi_data_out(struct rspi_data * rspi,u8 data)465 static int rspi_data_out(struct rspi_data *rspi, u8 data)
466 {
467 int error = rspi_wait_for_tx_empty(rspi);
468 if (error < 0) {
469 dev_err(&rspi->master->dev, "transmit timeout\n");
470 return error;
471 }
472 rspi_write_data(rspi, data);
473 return 0;
474 }
475
rspi_data_in(struct rspi_data * rspi)476 static int rspi_data_in(struct rspi_data *rspi)
477 {
478 int error;
479 u8 data;
480
481 error = rspi_wait_for_rx_full(rspi);
482 if (error < 0) {
483 dev_err(&rspi->master->dev, "receive timeout\n");
484 return error;
485 }
486 data = rspi_read_data(rspi);
487 return data;
488 }
489
rspi_pio_transfer(struct rspi_data * rspi,const u8 * tx,u8 * rx,unsigned int n)490 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
491 unsigned int n)
492 {
493 while (n-- > 0) {
494 if (tx) {
495 int ret = rspi_data_out(rspi, *tx++);
496 if (ret < 0)
497 return ret;
498 }
499 if (rx) {
500 int ret = rspi_data_in(rspi);
501 if (ret < 0)
502 return ret;
503 *rx++ = ret;
504 }
505 }
506
507 return 0;
508 }
509
rspi_dma_complete(void * arg)510 static void rspi_dma_complete(void *arg)
511 {
512 struct rspi_data *rspi = arg;
513
514 rspi->dma_callbacked = 1;
515 wake_up_interruptible(&rspi->wait);
516 }
517
rspi_dma_transfer(struct rspi_data * rspi,struct sg_table * tx,struct sg_table * rx)518 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
519 struct sg_table *rx)
520 {
521 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
522 u8 irq_mask = 0;
523 unsigned int other_irq = 0;
524 dma_cookie_t cookie;
525 int ret;
526
527 /* First prepare and submit the DMA request(s), as this may fail */
528 if (rx) {
529 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx,
530 rx->sgl, rx->nents, DMA_FROM_DEVICE,
531 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
532 if (!desc_rx) {
533 ret = -EAGAIN;
534 goto no_dma_rx;
535 }
536
537 desc_rx->callback = rspi_dma_complete;
538 desc_rx->callback_param = rspi;
539 cookie = dmaengine_submit(desc_rx);
540 if (dma_submit_error(cookie)) {
541 ret = cookie;
542 goto no_dma_rx;
543 }
544
545 irq_mask |= SPCR_SPRIE;
546 }
547
548 if (tx) {
549 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
550 tx->sgl, tx->nents, DMA_TO_DEVICE,
551 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
552 if (!desc_tx) {
553 ret = -EAGAIN;
554 goto no_dma_tx;
555 }
556
557 if (rx) {
558 /* No callback */
559 desc_tx->callback = NULL;
560 } else {
561 desc_tx->callback = rspi_dma_complete;
562 desc_tx->callback_param = rspi;
563 }
564 cookie = dmaengine_submit(desc_tx);
565 if (dma_submit_error(cookie)) {
566 ret = cookie;
567 goto no_dma_tx;
568 }
569
570 irq_mask |= SPCR_SPTIE;
571 }
572
573 /*
574 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
575 * called. So, this driver disables the IRQ while DMA transfer.
576 */
577 if (tx)
578 disable_irq(other_irq = rspi->tx_irq);
579 if (rx && rspi->rx_irq != other_irq)
580 disable_irq(rspi->rx_irq);
581
582 rspi_enable_irq(rspi, irq_mask);
583 rspi->dma_callbacked = 0;
584
585 /* Now start DMA */
586 if (rx)
587 dma_async_issue_pending(rspi->master->dma_rx);
588 if (tx)
589 dma_async_issue_pending(rspi->master->dma_tx);
590
591 ret = wait_event_interruptible_timeout(rspi->wait,
592 rspi->dma_callbacked, HZ);
593 if (ret > 0 && rspi->dma_callbacked) {
594 ret = 0;
595 } else {
596 if (!ret) {
597 dev_err(&rspi->master->dev, "DMA timeout\n");
598 ret = -ETIMEDOUT;
599 }
600 if (tx)
601 dmaengine_terminate_all(rspi->master->dma_tx);
602 if (rx)
603 dmaengine_terminate_all(rspi->master->dma_rx);
604 }
605
606 rspi_disable_irq(rspi, irq_mask);
607
608 if (tx)
609 enable_irq(rspi->tx_irq);
610 if (rx && rspi->rx_irq != other_irq)
611 enable_irq(rspi->rx_irq);
612
613 return ret;
614
615 no_dma_tx:
616 if (rx)
617 dmaengine_terminate_all(rspi->master->dma_rx);
618 no_dma_rx:
619 if (ret == -EAGAIN) {
620 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
621 dev_driver_string(&rspi->master->dev),
622 dev_name(&rspi->master->dev));
623 }
624 return ret;
625 }
626
rspi_receive_init(const struct rspi_data * rspi)627 static void rspi_receive_init(const struct rspi_data *rspi)
628 {
629 u8 spsr;
630
631 spsr = rspi_read8(rspi, RSPI_SPSR);
632 if (spsr & SPSR_SPRF)
633 rspi_read_data(rspi); /* dummy read */
634 if (spsr & SPSR_OVRF)
635 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
636 RSPI_SPSR);
637 }
638
rspi_rz_receive_init(const struct rspi_data * rspi)639 static void rspi_rz_receive_init(const struct rspi_data *rspi)
640 {
641 rspi_receive_init(rspi);
642 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
643 rspi_write8(rspi, 0, RSPI_SPBFCR);
644 }
645
qspi_receive_init(const struct rspi_data * rspi)646 static void qspi_receive_init(const struct rspi_data *rspi)
647 {
648 u8 spsr;
649
650 spsr = rspi_read8(rspi, RSPI_SPSR);
651 if (spsr & SPSR_SPRF)
652 rspi_read_data(rspi); /* dummy read */
653 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
654 rspi_write8(rspi, 0, QSPI_SPBFCR);
655 }
656
__rspi_can_dma(const struct rspi_data * rspi,const struct spi_transfer * xfer)657 static bool __rspi_can_dma(const struct rspi_data *rspi,
658 const struct spi_transfer *xfer)
659 {
660 return xfer->len > rspi->ops->fifo_size;
661 }
662
rspi_can_dma(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)663 static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi,
664 struct spi_transfer *xfer)
665 {
666 struct rspi_data *rspi = spi_master_get_devdata(master);
667
668 return __rspi_can_dma(rspi, xfer);
669 }
670
rspi_dma_check_then_transfer(struct rspi_data * rspi,struct spi_transfer * xfer)671 static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
672 struct spi_transfer *xfer)
673 {
674 if (!rspi->master->can_dma || !__rspi_can_dma(rspi, xfer))
675 return -EAGAIN;
676
677 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
678 return rspi_dma_transfer(rspi, &xfer->tx_sg,
679 xfer->rx_buf ? &xfer->rx_sg : NULL);
680 }
681
rspi_common_transfer(struct rspi_data * rspi,struct spi_transfer * xfer)682 static int rspi_common_transfer(struct rspi_data *rspi,
683 struct spi_transfer *xfer)
684 {
685 int ret;
686
687 ret = rspi_dma_check_then_transfer(rspi, xfer);
688 if (ret != -EAGAIN)
689 return ret;
690
691 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
692 if (ret < 0)
693 return ret;
694
695 /* Wait for the last transmission */
696 rspi_wait_for_tx_empty(rspi);
697
698 return 0;
699 }
700
rspi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)701 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
702 struct spi_transfer *xfer)
703 {
704 struct rspi_data *rspi = spi_master_get_devdata(master);
705 u8 spcr;
706
707 spcr = rspi_read8(rspi, RSPI_SPCR);
708 if (xfer->rx_buf) {
709 rspi_receive_init(rspi);
710 spcr &= ~SPCR_TXMD;
711 } else {
712 spcr |= SPCR_TXMD;
713 }
714 rspi_write8(rspi, spcr, RSPI_SPCR);
715
716 return rspi_common_transfer(rspi, xfer);
717 }
718
rspi_rz_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)719 static int rspi_rz_transfer_one(struct spi_master *master,
720 struct spi_device *spi,
721 struct spi_transfer *xfer)
722 {
723 struct rspi_data *rspi = spi_master_get_devdata(master);
724
725 rspi_rz_receive_init(rspi);
726
727 return rspi_common_transfer(rspi, xfer);
728 }
729
qspi_trigger_transfer_out_in(struct rspi_data * rspi,const u8 * tx,u8 * rx,unsigned int len)730 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
731 u8 *rx, unsigned int len)
732 {
733 unsigned int i, n;
734 int ret;
735
736 while (len > 0) {
737 n = qspi_set_send_trigger(rspi, len);
738 qspi_set_receive_trigger(rspi, len);
739 if (n == QSPI_BUFFER_SIZE) {
740 ret = rspi_wait_for_tx_empty(rspi);
741 if (ret < 0) {
742 dev_err(&rspi->master->dev, "transmit timeout\n");
743 return ret;
744 }
745 for (i = 0; i < n; i++)
746 rspi_write_data(rspi, *tx++);
747
748 ret = rspi_wait_for_rx_full(rspi);
749 if (ret < 0) {
750 dev_err(&rspi->master->dev, "receive timeout\n");
751 return ret;
752 }
753 for (i = 0; i < n; i++)
754 *rx++ = rspi_read_data(rspi);
755 } else {
756 ret = rspi_pio_transfer(rspi, tx, rx, n);
757 if (ret < 0)
758 return ret;
759 }
760 len -= n;
761 }
762
763 return 0;
764 }
765
qspi_transfer_out_in(struct rspi_data * rspi,struct spi_transfer * xfer)766 static int qspi_transfer_out_in(struct rspi_data *rspi,
767 struct spi_transfer *xfer)
768 {
769 int ret;
770
771 qspi_receive_init(rspi);
772
773 ret = rspi_dma_check_then_transfer(rspi, xfer);
774 if (ret != -EAGAIN)
775 return ret;
776
777 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
778 xfer->rx_buf, xfer->len);
779 }
780
qspi_transfer_out(struct rspi_data * rspi,struct spi_transfer * xfer)781 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
782 {
783 int ret;
784
785 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
786 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
787 if (ret != -EAGAIN)
788 return ret;
789 }
790
791 ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
792 if (ret < 0)
793 return ret;
794
795 /* Wait for the last transmission */
796 rspi_wait_for_tx_empty(rspi);
797
798 return 0;
799 }
800
qspi_transfer_in(struct rspi_data * rspi,struct spi_transfer * xfer)801 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
802 {
803 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
804 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
805 if (ret != -EAGAIN)
806 return ret;
807 }
808
809 return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
810 }
811
qspi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)812 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
813 struct spi_transfer *xfer)
814 {
815 struct rspi_data *rspi = spi_master_get_devdata(master);
816
817 if (spi->mode & SPI_LOOP) {
818 return qspi_transfer_out_in(rspi, xfer);
819 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
820 /* Quad or Dual SPI Write */
821 return qspi_transfer_out(rspi, xfer);
822 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
823 /* Quad or Dual SPI Read */
824 return qspi_transfer_in(rspi, xfer);
825 } else {
826 /* Single SPI Transfer */
827 return qspi_transfer_out_in(rspi, xfer);
828 }
829 }
830
rspi_setup(struct spi_device * spi)831 static int rspi_setup(struct spi_device *spi)
832 {
833 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
834
835 rspi->max_speed_hz = spi->max_speed_hz;
836
837 rspi->spcmd = SPCMD_SSLKP;
838 if (spi->mode & SPI_CPOL)
839 rspi->spcmd |= SPCMD_CPOL;
840 if (spi->mode & SPI_CPHA)
841 rspi->spcmd |= SPCMD_CPHA;
842
843 /* CMOS output mode and MOSI signal from previous transfer */
844 rspi->sppcr = 0;
845 if (spi->mode & SPI_LOOP)
846 rspi->sppcr |= SPPCR_SPLP;
847
848 set_config_register(rspi, 8);
849
850 return 0;
851 }
852
qspi_transfer_mode(const struct spi_transfer * xfer)853 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
854 {
855 if (xfer->tx_buf)
856 switch (xfer->tx_nbits) {
857 case SPI_NBITS_QUAD:
858 return SPCMD_SPIMOD_QUAD;
859 case SPI_NBITS_DUAL:
860 return SPCMD_SPIMOD_DUAL;
861 default:
862 return 0;
863 }
864 if (xfer->rx_buf)
865 switch (xfer->rx_nbits) {
866 case SPI_NBITS_QUAD:
867 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
868 case SPI_NBITS_DUAL:
869 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
870 default:
871 return 0;
872 }
873
874 return 0;
875 }
876
qspi_setup_sequencer(struct rspi_data * rspi,const struct spi_message * msg)877 static int qspi_setup_sequencer(struct rspi_data *rspi,
878 const struct spi_message *msg)
879 {
880 const struct spi_transfer *xfer;
881 unsigned int i = 0, len = 0;
882 u16 current_mode = 0xffff, mode;
883
884 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
885 mode = qspi_transfer_mode(xfer);
886 if (mode == current_mode) {
887 len += xfer->len;
888 continue;
889 }
890
891 /* Transfer mode change */
892 if (i) {
893 /* Set transfer data length of previous transfer */
894 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
895 }
896
897 if (i >= QSPI_NUM_SPCMD) {
898 dev_err(&msg->spi->dev,
899 "Too many different transfer modes");
900 return -EINVAL;
901 }
902
903 /* Program transfer mode for this transfer */
904 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
905 current_mode = mode;
906 len = xfer->len;
907 i++;
908 }
909 if (i) {
910 /* Set final transfer data length and sequence length */
911 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
912 rspi_write8(rspi, i - 1, RSPI_SPSCR);
913 }
914
915 return 0;
916 }
917
rspi_prepare_message(struct spi_master * master,struct spi_message * msg)918 static int rspi_prepare_message(struct spi_master *master,
919 struct spi_message *msg)
920 {
921 struct rspi_data *rspi = spi_master_get_devdata(master);
922 int ret;
923
924 if (msg->spi->mode &
925 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
926 /* Setup sequencer for messages with multiple transfer modes */
927 ret = qspi_setup_sequencer(rspi, msg);
928 if (ret < 0)
929 return ret;
930 }
931
932 /* Enable SPI function in master mode */
933 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
934 return 0;
935 }
936
rspi_unprepare_message(struct spi_master * master,struct spi_message * msg)937 static int rspi_unprepare_message(struct spi_master *master,
938 struct spi_message *msg)
939 {
940 struct rspi_data *rspi = spi_master_get_devdata(master);
941
942 /* Disable SPI function */
943 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
944
945 /* Reset sequencer for Single SPI Transfers */
946 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
947 rspi_write8(rspi, 0, RSPI_SPSCR);
948 return 0;
949 }
950
rspi_irq_mux(int irq,void * _sr)951 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
952 {
953 struct rspi_data *rspi = _sr;
954 u8 spsr;
955 irqreturn_t ret = IRQ_NONE;
956 u8 disable_irq = 0;
957
958 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
959 if (spsr & SPSR_SPRF)
960 disable_irq |= SPCR_SPRIE;
961 if (spsr & SPSR_SPTEF)
962 disable_irq |= SPCR_SPTIE;
963
964 if (disable_irq) {
965 ret = IRQ_HANDLED;
966 rspi_disable_irq(rspi, disable_irq);
967 wake_up(&rspi->wait);
968 }
969
970 return ret;
971 }
972
rspi_irq_rx(int irq,void * _sr)973 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
974 {
975 struct rspi_data *rspi = _sr;
976 u8 spsr;
977
978 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
979 if (spsr & SPSR_SPRF) {
980 rspi_disable_irq(rspi, SPCR_SPRIE);
981 wake_up(&rspi->wait);
982 return IRQ_HANDLED;
983 }
984
985 return 0;
986 }
987
rspi_irq_tx(int irq,void * _sr)988 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
989 {
990 struct rspi_data *rspi = _sr;
991 u8 spsr;
992
993 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
994 if (spsr & SPSR_SPTEF) {
995 rspi_disable_irq(rspi, SPCR_SPTIE);
996 wake_up(&rspi->wait);
997 return IRQ_HANDLED;
998 }
999
1000 return 0;
1001 }
1002
rspi_request_dma_chan(struct device * dev,enum dma_transfer_direction dir,unsigned int id,dma_addr_t port_addr)1003 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
1004 enum dma_transfer_direction dir,
1005 unsigned int id,
1006 dma_addr_t port_addr)
1007 {
1008 dma_cap_mask_t mask;
1009 struct dma_chan *chan;
1010 struct dma_slave_config cfg;
1011 int ret;
1012
1013 dma_cap_zero(mask);
1014 dma_cap_set(DMA_SLAVE, mask);
1015
1016 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1017 (void *)(unsigned long)id, dev,
1018 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1019 if (!chan) {
1020 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1021 return NULL;
1022 }
1023
1024 memset(&cfg, 0, sizeof(cfg));
1025 cfg.direction = dir;
1026 if (dir == DMA_MEM_TO_DEV) {
1027 cfg.dst_addr = port_addr;
1028 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1029 } else {
1030 cfg.src_addr = port_addr;
1031 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1032 }
1033
1034 ret = dmaengine_slave_config(chan, &cfg);
1035 if (ret) {
1036 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1037 dma_release_channel(chan);
1038 return NULL;
1039 }
1040
1041 return chan;
1042 }
1043
rspi_request_dma(struct device * dev,struct spi_master * master,const struct resource * res)1044 static int rspi_request_dma(struct device *dev, struct spi_master *master,
1045 const struct resource *res)
1046 {
1047 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
1048 unsigned int dma_tx_id, dma_rx_id;
1049
1050 if (dev->of_node) {
1051 /* In the OF case we will get the slave IDs from the DT */
1052 dma_tx_id = 0;
1053 dma_rx_id = 0;
1054 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
1055 dma_tx_id = rspi_pd->dma_tx_id;
1056 dma_rx_id = rspi_pd->dma_rx_id;
1057 } else {
1058 /* The driver assumes no error. */
1059 return 0;
1060 }
1061
1062 master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1063 res->start + RSPI_SPDR);
1064 if (!master->dma_tx)
1065 return -ENODEV;
1066
1067 master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1068 res->start + RSPI_SPDR);
1069 if (!master->dma_rx) {
1070 dma_release_channel(master->dma_tx);
1071 master->dma_tx = NULL;
1072 return -ENODEV;
1073 }
1074
1075 master->can_dma = rspi_can_dma;
1076 dev_info(dev, "DMA available");
1077 return 0;
1078 }
1079
rspi_release_dma(struct spi_master * master)1080 static void rspi_release_dma(struct spi_master *master)
1081 {
1082 if (master->dma_tx)
1083 dma_release_channel(master->dma_tx);
1084 if (master->dma_rx)
1085 dma_release_channel(master->dma_rx);
1086 }
1087
rspi_remove(struct platform_device * pdev)1088 static int rspi_remove(struct platform_device *pdev)
1089 {
1090 struct rspi_data *rspi = platform_get_drvdata(pdev);
1091
1092 rspi_release_dma(rspi->master);
1093 pm_runtime_disable(&pdev->dev);
1094
1095 return 0;
1096 }
1097
1098 static const struct spi_ops rspi_ops = {
1099 .set_config_register = rspi_set_config_register,
1100 .transfer_one = rspi_transfer_one,
1101 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1102 .flags = SPI_MASTER_MUST_TX,
1103 .fifo_size = 8,
1104 };
1105
1106 static const struct spi_ops rspi_rz_ops = {
1107 .set_config_register = rspi_rz_set_config_register,
1108 .transfer_one = rspi_rz_transfer_one,
1109 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1110 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1111 .fifo_size = 8, /* 8 for TX, 32 for RX */
1112 };
1113
1114 static const struct spi_ops qspi_ops = {
1115 .set_config_register = qspi_set_config_register,
1116 .transfer_one = qspi_transfer_one,
1117 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1118 SPI_TX_DUAL | SPI_TX_QUAD |
1119 SPI_RX_DUAL | SPI_RX_QUAD,
1120 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1121 .fifo_size = 32,
1122 };
1123
1124 #ifdef CONFIG_OF
1125 static const struct of_device_id rspi_of_match[] = {
1126 /* RSPI on legacy SH */
1127 { .compatible = "renesas,rspi", .data = &rspi_ops },
1128 /* RSPI on RZ/A1H */
1129 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1130 /* QSPI on R-Car Gen2 */
1131 { .compatible = "renesas,qspi", .data = &qspi_ops },
1132 { /* sentinel */ }
1133 };
1134
1135 MODULE_DEVICE_TABLE(of, rspi_of_match);
1136
rspi_parse_dt(struct device * dev,struct spi_master * master)1137 static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1138 {
1139 u32 num_cs;
1140 int error;
1141
1142 /* Parse DT properties */
1143 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1144 if (error) {
1145 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1146 return error;
1147 }
1148
1149 master->num_chipselect = num_cs;
1150 return 0;
1151 }
1152 #else
1153 #define rspi_of_match NULL
rspi_parse_dt(struct device * dev,struct spi_master * master)1154 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1155 {
1156 return -EINVAL;
1157 }
1158 #endif /* CONFIG_OF */
1159
rspi_request_irq(struct device * dev,unsigned int irq,irq_handler_t handler,const char * suffix,void * dev_id)1160 static int rspi_request_irq(struct device *dev, unsigned int irq,
1161 irq_handler_t handler, const char *suffix,
1162 void *dev_id)
1163 {
1164 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1165 dev_name(dev), suffix);
1166 if (!name)
1167 return -ENOMEM;
1168
1169 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1170 }
1171
rspi_probe(struct platform_device * pdev)1172 static int rspi_probe(struct platform_device *pdev)
1173 {
1174 struct resource *res;
1175 struct spi_master *master;
1176 struct rspi_data *rspi;
1177 int ret;
1178 const struct of_device_id *of_id;
1179 const struct rspi_plat_data *rspi_pd;
1180 const struct spi_ops *ops;
1181
1182 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1183 if (master == NULL) {
1184 dev_err(&pdev->dev, "spi_alloc_master error.\n");
1185 return -ENOMEM;
1186 }
1187
1188 of_id = of_match_device(rspi_of_match, &pdev->dev);
1189 if (of_id) {
1190 ops = of_id->data;
1191 ret = rspi_parse_dt(&pdev->dev, master);
1192 if (ret)
1193 goto error1;
1194 } else {
1195 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1196 rspi_pd = dev_get_platdata(&pdev->dev);
1197 if (rspi_pd && rspi_pd->num_chipselect)
1198 master->num_chipselect = rspi_pd->num_chipselect;
1199 else
1200 master->num_chipselect = 2; /* default */
1201 }
1202
1203 /* ops parameter check */
1204 if (!ops->set_config_register) {
1205 dev_err(&pdev->dev, "there is no set_config_register\n");
1206 ret = -ENODEV;
1207 goto error1;
1208 }
1209
1210 rspi = spi_master_get_devdata(master);
1211 platform_set_drvdata(pdev, rspi);
1212 rspi->ops = ops;
1213 rspi->master = master;
1214
1215 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1216 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1217 if (IS_ERR(rspi->addr)) {
1218 ret = PTR_ERR(rspi->addr);
1219 goto error1;
1220 }
1221
1222 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1223 if (IS_ERR(rspi->clk)) {
1224 dev_err(&pdev->dev, "cannot get clock\n");
1225 ret = PTR_ERR(rspi->clk);
1226 goto error1;
1227 }
1228
1229 pm_runtime_enable(&pdev->dev);
1230
1231 init_waitqueue_head(&rspi->wait);
1232
1233 master->bus_num = pdev->id;
1234 master->setup = rspi_setup;
1235 master->auto_runtime_pm = true;
1236 master->transfer_one = ops->transfer_one;
1237 master->prepare_message = rspi_prepare_message;
1238 master->unprepare_message = rspi_unprepare_message;
1239 master->mode_bits = ops->mode_bits;
1240 master->flags = ops->flags;
1241 master->dev.of_node = pdev->dev.of_node;
1242
1243 ret = platform_get_irq_byname(pdev, "rx");
1244 if (ret < 0) {
1245 ret = platform_get_irq_byname(pdev, "mux");
1246 if (ret < 0)
1247 ret = platform_get_irq(pdev, 0);
1248 if (ret >= 0)
1249 rspi->rx_irq = rspi->tx_irq = ret;
1250 } else {
1251 rspi->rx_irq = ret;
1252 ret = platform_get_irq_byname(pdev, "tx");
1253 if (ret >= 0)
1254 rspi->tx_irq = ret;
1255 }
1256 if (ret < 0) {
1257 dev_err(&pdev->dev, "platform_get_irq error\n");
1258 goto error2;
1259 }
1260
1261 if (rspi->rx_irq == rspi->tx_irq) {
1262 /* Single multiplexed interrupt */
1263 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1264 "mux", rspi);
1265 } else {
1266 /* Multi-interrupt mode, only SPRI and SPTI are used */
1267 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1268 "rx", rspi);
1269 if (!ret)
1270 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1271 rspi_irq_tx, "tx", rspi);
1272 }
1273 if (ret < 0) {
1274 dev_err(&pdev->dev, "request_irq error\n");
1275 goto error2;
1276 }
1277
1278 ret = rspi_request_dma(&pdev->dev, master, res);
1279 if (ret < 0)
1280 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1281
1282 ret = devm_spi_register_master(&pdev->dev, master);
1283 if (ret < 0) {
1284 dev_err(&pdev->dev, "spi_register_master error.\n");
1285 goto error3;
1286 }
1287
1288 dev_info(&pdev->dev, "probed\n");
1289
1290 return 0;
1291
1292 error3:
1293 rspi_release_dma(master);
1294 error2:
1295 pm_runtime_disable(&pdev->dev);
1296 error1:
1297 spi_master_put(master);
1298
1299 return ret;
1300 }
1301
1302 static const struct platform_device_id spi_driver_ids[] = {
1303 { "rspi", (kernel_ulong_t)&rspi_ops },
1304 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1305 { "qspi", (kernel_ulong_t)&qspi_ops },
1306 {},
1307 };
1308
1309 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1310
1311 #ifdef CONFIG_PM_SLEEP
rspi_suspend(struct device * dev)1312 static int rspi_suspend(struct device *dev)
1313 {
1314 struct platform_device *pdev = to_platform_device(dev);
1315 struct rspi_data *rspi = platform_get_drvdata(pdev);
1316
1317 return spi_master_suspend(rspi->master);
1318 }
1319
rspi_resume(struct device * dev)1320 static int rspi_resume(struct device *dev)
1321 {
1322 struct platform_device *pdev = to_platform_device(dev);
1323 struct rspi_data *rspi = platform_get_drvdata(pdev);
1324
1325 return spi_master_resume(rspi->master);
1326 }
1327
1328 static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
1329 #define DEV_PM_OPS &rspi_pm_ops
1330 #else
1331 #define DEV_PM_OPS NULL
1332 #endif /* CONFIG_PM_SLEEP */
1333
1334 static struct platform_driver rspi_driver = {
1335 .probe = rspi_probe,
1336 .remove = rspi_remove,
1337 .id_table = spi_driver_ids,
1338 .driver = {
1339 .name = "renesas_spi",
1340 .pm = DEV_PM_OPS,
1341 .of_match_table = of_match_ptr(rspi_of_match),
1342 },
1343 };
1344 module_platform_driver(rspi_driver);
1345
1346 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1347 MODULE_LICENSE("GPL v2");
1348 MODULE_AUTHOR("Yoshihiro Shimoda");
1349 MODULE_ALIAS("platform:rspi");
1350