1 /*
2 * SPI driver for NVIDIA's Tegra114 SPI Controller.
3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmapool.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kernel.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/reset.h>
36 #include <linux/spi/spi.h>
37
38 #define SPI_COMMAND1 0x000
39 #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
40 #define SPI_PACKED (1 << 5)
41 #define SPI_TX_EN (1 << 11)
42 #define SPI_RX_EN (1 << 12)
43 #define SPI_BOTH_EN_BYTE (1 << 13)
44 #define SPI_BOTH_EN_BIT (1 << 14)
45 #define SPI_LSBYTE_FE (1 << 15)
46 #define SPI_LSBIT_FE (1 << 16)
47 #define SPI_BIDIROE (1 << 17)
48 #define SPI_IDLE_SDA_DRIVE_LOW (0 << 18)
49 #define SPI_IDLE_SDA_DRIVE_HIGH (1 << 18)
50 #define SPI_IDLE_SDA_PULL_LOW (2 << 18)
51 #define SPI_IDLE_SDA_PULL_HIGH (3 << 18)
52 #define SPI_IDLE_SDA_MASK (3 << 18)
53 #define SPI_CS_SS_VAL (1 << 20)
54 #define SPI_CS_SW_HW (1 << 21)
55 /* SPI_CS_POL_INACTIVE bits are default high */
56 /* n from 0 to 3 */
57 #define SPI_CS_POL_INACTIVE(n) (1 << (22 + (n)))
58 #define SPI_CS_POL_INACTIVE_MASK (0xF << 22)
59
60 #define SPI_CS_SEL_0 (0 << 26)
61 #define SPI_CS_SEL_1 (1 << 26)
62 #define SPI_CS_SEL_2 (2 << 26)
63 #define SPI_CS_SEL_3 (3 << 26)
64 #define SPI_CS_SEL_MASK (3 << 26)
65 #define SPI_CS_SEL(x) (((x) & 0x3) << 26)
66 #define SPI_CONTROL_MODE_0 (0 << 28)
67 #define SPI_CONTROL_MODE_1 (1 << 28)
68 #define SPI_CONTROL_MODE_2 (2 << 28)
69 #define SPI_CONTROL_MODE_3 (3 << 28)
70 #define SPI_CONTROL_MODE_MASK (3 << 28)
71 #define SPI_MODE_SEL(x) (((x) & 0x3) << 28)
72 #define SPI_M_S (1 << 30)
73 #define SPI_PIO (1 << 31)
74
75 #define SPI_COMMAND2 0x004
76 #define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 6)
77 #define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 0)
78
79 #define SPI_CS_TIMING1 0x008
80 #define SPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold))
81 #define SPI_CS_SETUP_HOLD(reg, cs, val) \
82 ((((val) & 0xFFu) << ((cs) * 8)) | \
83 ((reg) & ~(0xFFu << ((cs) * 8))))
84
85 #define SPI_CS_TIMING2 0x00C
86 #define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1F) << 0)
87 #define CS_ACTIVE_BETWEEN_PACKETS_0 (1 << 5)
88 #define CYCLES_BETWEEN_PACKETS_1(x) (((x) & 0x1F) << 8)
89 #define CS_ACTIVE_BETWEEN_PACKETS_1 (1 << 13)
90 #define CYCLES_BETWEEN_PACKETS_2(x) (((x) & 0x1F) << 16)
91 #define CS_ACTIVE_BETWEEN_PACKETS_2 (1 << 21)
92 #define CYCLES_BETWEEN_PACKETS_3(x) (((x) & 0x1F) << 24)
93 #define CS_ACTIVE_BETWEEN_PACKETS_3 (1 << 29)
94 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
95 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
96 ((reg) & ~(1 << ((cs) * 8 + 5))))
97 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
98 (reg = (((val) & 0xF) << ((cs) * 8)) | \
99 ((reg) & ~(0xF << ((cs) * 8))))
100
101 #define SPI_TRANS_STATUS 0x010
102 #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
103 #define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF)
104 #define SPI_RDY (1 << 30)
105
106 #define SPI_FIFO_STATUS 0x014
107 #define SPI_RX_FIFO_EMPTY (1 << 0)
108 #define SPI_RX_FIFO_FULL (1 << 1)
109 #define SPI_TX_FIFO_EMPTY (1 << 2)
110 #define SPI_TX_FIFO_FULL (1 << 3)
111 #define SPI_RX_FIFO_UNF (1 << 4)
112 #define SPI_RX_FIFO_OVF (1 << 5)
113 #define SPI_TX_FIFO_UNF (1 << 6)
114 #define SPI_TX_FIFO_OVF (1 << 7)
115 #define SPI_ERR (1 << 8)
116 #define SPI_TX_FIFO_FLUSH (1 << 14)
117 #define SPI_RX_FIFO_FLUSH (1 << 15)
118 #define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F)
119 #define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F)
120 #define SPI_FRAME_END (1 << 30)
121 #define SPI_CS_INACTIVE (1 << 31)
122
123 #define SPI_FIFO_ERROR (SPI_RX_FIFO_UNF | \
124 SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
125 #define SPI_FIFO_EMPTY (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
126
127 #define SPI_TX_DATA 0x018
128 #define SPI_RX_DATA 0x01C
129
130 #define SPI_DMA_CTL 0x020
131 #define SPI_TX_TRIG_1 (0 << 15)
132 #define SPI_TX_TRIG_4 (1 << 15)
133 #define SPI_TX_TRIG_8 (2 << 15)
134 #define SPI_TX_TRIG_16 (3 << 15)
135 #define SPI_TX_TRIG_MASK (3 << 15)
136 #define SPI_RX_TRIG_1 (0 << 19)
137 #define SPI_RX_TRIG_4 (1 << 19)
138 #define SPI_RX_TRIG_8 (2 << 19)
139 #define SPI_RX_TRIG_16 (3 << 19)
140 #define SPI_RX_TRIG_MASK (3 << 19)
141 #define SPI_IE_TX (1 << 28)
142 #define SPI_IE_RX (1 << 29)
143 #define SPI_CONT (1 << 30)
144 #define SPI_DMA (1 << 31)
145 #define SPI_DMA_EN SPI_DMA
146
147 #define SPI_DMA_BLK 0x024
148 #define SPI_DMA_BLK_SET(x) (((x) & 0xFFFF) << 0)
149
150 #define SPI_TX_FIFO 0x108
151 #define SPI_RX_FIFO 0x188
152 #define MAX_CHIP_SELECT 4
153 #define SPI_FIFO_DEPTH 64
154 #define DATA_DIR_TX (1 << 0)
155 #define DATA_DIR_RX (1 << 1)
156
157 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
158 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
159 #define TX_FIFO_EMPTY_COUNT_MAX SPI_TX_FIFO_EMPTY_COUNT(0x40)
160 #define RX_FIFO_FULL_COUNT_ZERO SPI_RX_FIFO_FULL_COUNT(0)
161 #define MAX_HOLD_CYCLES 16
162 #define SPI_DEFAULT_SPEED 25000000
163
164 struct tegra_spi_data {
165 struct device *dev;
166 struct spi_master *master;
167 spinlock_t lock;
168
169 struct clk *clk;
170 struct reset_control *rst;
171 void __iomem *base;
172 phys_addr_t phys;
173 unsigned irq;
174 u32 cur_speed;
175
176 struct spi_device *cur_spi;
177 struct spi_device *cs_control;
178 unsigned cur_pos;
179 unsigned words_per_32bit;
180 unsigned bytes_per_word;
181 unsigned curr_dma_words;
182 unsigned cur_direction;
183
184 unsigned cur_rx_pos;
185 unsigned cur_tx_pos;
186
187 unsigned dma_buf_size;
188 unsigned max_buf_size;
189 bool is_curr_dma_xfer;
190
191 struct completion rx_dma_complete;
192 struct completion tx_dma_complete;
193
194 u32 tx_status;
195 u32 rx_status;
196 u32 status_reg;
197 bool is_packed;
198
199 u32 command1_reg;
200 u32 dma_control_reg;
201 u32 def_command1_reg;
202
203 struct completion xfer_completion;
204 struct spi_transfer *curr_xfer;
205 struct dma_chan *rx_dma_chan;
206 u32 *rx_dma_buf;
207 dma_addr_t rx_dma_phys;
208 struct dma_async_tx_descriptor *rx_dma_desc;
209
210 struct dma_chan *tx_dma_chan;
211 u32 *tx_dma_buf;
212 dma_addr_t tx_dma_phys;
213 struct dma_async_tx_descriptor *tx_dma_desc;
214 };
215
216 static int tegra_spi_runtime_suspend(struct device *dev);
217 static int tegra_spi_runtime_resume(struct device *dev);
218
tegra_spi_readl(struct tegra_spi_data * tspi,unsigned long reg)219 static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
220 unsigned long reg)
221 {
222 return readl(tspi->base + reg);
223 }
224
tegra_spi_writel(struct tegra_spi_data * tspi,u32 val,unsigned long reg)225 static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
226 u32 val, unsigned long reg)
227 {
228 writel(val, tspi->base + reg);
229
230 /* Read back register to make sure that register writes completed */
231 if (reg != SPI_TX_FIFO)
232 readl(tspi->base + SPI_COMMAND1);
233 }
234
tegra_spi_clear_status(struct tegra_spi_data * tspi)235 static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
236 {
237 u32 val;
238
239 /* Write 1 to clear status register */
240 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
241 tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
242
243 /* Clear fifo status error if any */
244 val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
245 if (val & SPI_ERR)
246 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
247 SPI_FIFO_STATUS);
248 }
249
tegra_spi_calculate_curr_xfer_param(struct spi_device * spi,struct tegra_spi_data * tspi,struct spi_transfer * t)250 static unsigned tegra_spi_calculate_curr_xfer_param(
251 struct spi_device *spi, struct tegra_spi_data *tspi,
252 struct spi_transfer *t)
253 {
254 unsigned remain_len = t->len - tspi->cur_pos;
255 unsigned max_word;
256 unsigned bits_per_word = t->bits_per_word;
257 unsigned max_len;
258 unsigned total_fifo_words;
259
260 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
261
262 if (bits_per_word == 8 || bits_per_word == 16) {
263 tspi->is_packed = 1;
264 tspi->words_per_32bit = 32/bits_per_word;
265 } else {
266 tspi->is_packed = 0;
267 tspi->words_per_32bit = 1;
268 }
269
270 if (tspi->is_packed) {
271 max_len = min(remain_len, tspi->max_buf_size);
272 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
273 total_fifo_words = (max_len + 3) / 4;
274 } else {
275 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
276 max_word = min(max_word, tspi->max_buf_size/4);
277 tspi->curr_dma_words = max_word;
278 total_fifo_words = max_word;
279 }
280 return total_fifo_words;
281 }
282
tegra_spi_fill_tx_fifo_from_client_txbuf(struct tegra_spi_data * tspi,struct spi_transfer * t)283 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
284 struct tegra_spi_data *tspi, struct spi_transfer *t)
285 {
286 unsigned nbytes;
287 unsigned tx_empty_count;
288 u32 fifo_status;
289 unsigned max_n_32bit;
290 unsigned i, count;
291 unsigned int written_words;
292 unsigned fifo_words_left;
293 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
294
295 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
296 tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
297
298 if (tspi->is_packed) {
299 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
300 written_words = min(fifo_words_left, tspi->curr_dma_words);
301 nbytes = written_words * tspi->bytes_per_word;
302 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
303 for (count = 0; count < max_n_32bit; count++) {
304 u32 x = 0;
305
306 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
307 x |= (u32)(*tx_buf++) << (i * 8);
308 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
309 }
310
311 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
312 } else {
313 unsigned int write_bytes;
314 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
315 written_words = max_n_32bit;
316 nbytes = written_words * tspi->bytes_per_word;
317 if (nbytes > t->len - tspi->cur_pos)
318 nbytes = t->len - tspi->cur_pos;
319 write_bytes = nbytes;
320 for (count = 0; count < max_n_32bit; count++) {
321 u32 x = 0;
322
323 for (i = 0; nbytes && (i < tspi->bytes_per_word);
324 i++, nbytes--)
325 x |= (u32)(*tx_buf++) << (i * 8);
326 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
327 }
328
329 tspi->cur_tx_pos += write_bytes;
330 }
331
332 return written_words;
333 }
334
tegra_spi_read_rx_fifo_to_client_rxbuf(struct tegra_spi_data * tspi,struct spi_transfer * t)335 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
336 struct tegra_spi_data *tspi, struct spi_transfer *t)
337 {
338 unsigned rx_full_count;
339 u32 fifo_status;
340 unsigned i, count;
341 unsigned int read_words = 0;
342 unsigned len;
343 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
344
345 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
346 rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
347 if (tspi->is_packed) {
348 len = tspi->curr_dma_words * tspi->bytes_per_word;
349 for (count = 0; count < rx_full_count; count++) {
350 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
351
352 for (i = 0; len && (i < 4); i++, len--)
353 *rx_buf++ = (x >> i*8) & 0xFF;
354 }
355 read_words += tspi->curr_dma_words;
356 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
357 } else {
358 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
359 u8 bytes_per_word = tspi->bytes_per_word;
360 unsigned int read_bytes;
361
362 len = rx_full_count * bytes_per_word;
363 if (len > t->len - tspi->cur_pos)
364 len = t->len - tspi->cur_pos;
365 read_bytes = len;
366 for (count = 0; count < rx_full_count; count++) {
367 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
368
369 for (i = 0; len && (i < bytes_per_word); i++, len--)
370 *rx_buf++ = (x >> (i*8)) & 0xFF;
371 }
372 read_words += rx_full_count;
373 tspi->cur_rx_pos += read_bytes;
374 }
375
376 return read_words;
377 }
378
tegra_spi_copy_client_txbuf_to_spi_txbuf(struct tegra_spi_data * tspi,struct spi_transfer * t)379 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
380 struct tegra_spi_data *tspi, struct spi_transfer *t)
381 {
382 /* Make the dma buffer to read by cpu */
383 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
384 tspi->dma_buf_size, DMA_TO_DEVICE);
385
386 if (tspi->is_packed) {
387 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
388
389 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
390 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
391 } else {
392 unsigned int i;
393 unsigned int count;
394 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
395 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
396 unsigned int write_bytes;
397
398 if (consume > t->len - tspi->cur_pos)
399 consume = t->len - tspi->cur_pos;
400 write_bytes = consume;
401 for (count = 0; count < tspi->curr_dma_words; count++) {
402 u32 x = 0;
403
404 for (i = 0; consume && (i < tspi->bytes_per_word);
405 i++, consume--)
406 x |= (u32)(*tx_buf++) << (i * 8);
407 tspi->tx_dma_buf[count] = x;
408 }
409
410 tspi->cur_tx_pos += write_bytes;
411 }
412
413 /* Make the dma buffer to read by dma */
414 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
415 tspi->dma_buf_size, DMA_TO_DEVICE);
416 }
417
tegra_spi_copy_spi_rxbuf_to_client_rxbuf(struct tegra_spi_data * tspi,struct spi_transfer * t)418 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
419 struct tegra_spi_data *tspi, struct spi_transfer *t)
420 {
421 /* Make the dma buffer to read by cpu */
422 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
423 tspi->dma_buf_size, DMA_FROM_DEVICE);
424
425 if (tspi->is_packed) {
426 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
427
428 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
429 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
430 } else {
431 unsigned int i;
432 unsigned int count;
433 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
434 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
435 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
436 unsigned int read_bytes;
437
438 if (consume > t->len - tspi->cur_pos)
439 consume = t->len - tspi->cur_pos;
440 read_bytes = consume;
441 for (count = 0; count < tspi->curr_dma_words; count++) {
442 u32 x = tspi->rx_dma_buf[count] & rx_mask;
443
444 for (i = 0; consume && (i < tspi->bytes_per_word);
445 i++, consume--)
446 *rx_buf++ = (x >> (i*8)) & 0xFF;
447 }
448
449 tspi->cur_rx_pos += read_bytes;
450 }
451
452 /* Make the dma buffer to read by dma */
453 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
454 tspi->dma_buf_size, DMA_FROM_DEVICE);
455 }
456
tegra_spi_dma_complete(void * args)457 static void tegra_spi_dma_complete(void *args)
458 {
459 struct completion *dma_complete = args;
460
461 complete(dma_complete);
462 }
463
tegra_spi_start_tx_dma(struct tegra_spi_data * tspi,int len)464 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
465 {
466 reinit_completion(&tspi->tx_dma_complete);
467 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
468 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
469 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
470 if (!tspi->tx_dma_desc) {
471 dev_err(tspi->dev, "Not able to get desc for Tx\n");
472 return -EIO;
473 }
474
475 tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
476 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
477
478 dmaengine_submit(tspi->tx_dma_desc);
479 dma_async_issue_pending(tspi->tx_dma_chan);
480 return 0;
481 }
482
tegra_spi_start_rx_dma(struct tegra_spi_data * tspi,int len)483 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
484 {
485 reinit_completion(&tspi->rx_dma_complete);
486 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
487 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
488 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
489 if (!tspi->rx_dma_desc) {
490 dev_err(tspi->dev, "Not able to get desc for Rx\n");
491 return -EIO;
492 }
493
494 tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
495 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
496
497 dmaengine_submit(tspi->rx_dma_desc);
498 dma_async_issue_pending(tspi->rx_dma_chan);
499 return 0;
500 }
501
tegra_spi_start_dma_based_transfer(struct tegra_spi_data * tspi,struct spi_transfer * t)502 static int tegra_spi_start_dma_based_transfer(
503 struct tegra_spi_data *tspi, struct spi_transfer *t)
504 {
505 u32 val;
506 unsigned int len;
507 int ret = 0;
508 u32 status;
509
510 /* Make sure that Rx and Tx fifo are empty */
511 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
512 if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
513 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
514 (unsigned)status);
515 return -EIO;
516 }
517
518 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
519 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
520
521 if (tspi->is_packed)
522 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
523 4) * 4;
524 else
525 len = tspi->curr_dma_words * 4;
526
527 /* Set attention level based on length of transfer */
528 if (len & 0xF)
529 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
530 else if (((len) >> 4) & 0x1)
531 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
532 else
533 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
534
535 if (tspi->cur_direction & DATA_DIR_TX)
536 val |= SPI_IE_TX;
537
538 if (tspi->cur_direction & DATA_DIR_RX)
539 val |= SPI_IE_RX;
540
541 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
542 tspi->dma_control_reg = val;
543
544 if (tspi->cur_direction & DATA_DIR_TX) {
545 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
546 ret = tegra_spi_start_tx_dma(tspi, len);
547 if (ret < 0) {
548 dev_err(tspi->dev,
549 "Starting tx dma failed, err %d\n", ret);
550 return ret;
551 }
552 }
553
554 if (tspi->cur_direction & DATA_DIR_RX) {
555 /* Make the dma buffer to read by dma */
556 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
557 tspi->dma_buf_size, DMA_FROM_DEVICE);
558
559 ret = tegra_spi_start_rx_dma(tspi, len);
560 if (ret < 0) {
561 dev_err(tspi->dev,
562 "Starting rx dma failed, err %d\n", ret);
563 if (tspi->cur_direction & DATA_DIR_TX)
564 dmaengine_terminate_all(tspi->tx_dma_chan);
565 return ret;
566 }
567 }
568 tspi->is_curr_dma_xfer = true;
569 tspi->dma_control_reg = val;
570
571 val |= SPI_DMA_EN;
572 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
573 return ret;
574 }
575
tegra_spi_start_cpu_based_transfer(struct tegra_spi_data * tspi,struct spi_transfer * t)576 static int tegra_spi_start_cpu_based_transfer(
577 struct tegra_spi_data *tspi, struct spi_transfer *t)
578 {
579 u32 val;
580 unsigned cur_words;
581
582 if (tspi->cur_direction & DATA_DIR_TX)
583 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
584 else
585 cur_words = tspi->curr_dma_words;
586
587 val = SPI_DMA_BLK_SET(cur_words - 1);
588 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
589
590 val = 0;
591 if (tspi->cur_direction & DATA_DIR_TX)
592 val |= SPI_IE_TX;
593
594 if (tspi->cur_direction & DATA_DIR_RX)
595 val |= SPI_IE_RX;
596
597 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
598 tspi->dma_control_reg = val;
599
600 tspi->is_curr_dma_xfer = false;
601
602 val |= SPI_DMA_EN;
603 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
604 return 0;
605 }
606
tegra_spi_init_dma_param(struct tegra_spi_data * tspi,bool dma_to_memory)607 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
608 bool dma_to_memory)
609 {
610 struct dma_chan *dma_chan;
611 u32 *dma_buf;
612 dma_addr_t dma_phys;
613 int ret;
614 struct dma_slave_config dma_sconfig;
615
616 dma_chan = dma_request_slave_channel_reason(tspi->dev,
617 dma_to_memory ? "rx" : "tx");
618 if (IS_ERR(dma_chan)) {
619 ret = PTR_ERR(dma_chan);
620 if (ret != -EPROBE_DEFER)
621 dev_err(tspi->dev,
622 "Dma channel is not available: %d\n", ret);
623 return ret;
624 }
625
626 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
627 &dma_phys, GFP_KERNEL);
628 if (!dma_buf) {
629 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
630 dma_release_channel(dma_chan);
631 return -ENOMEM;
632 }
633
634 if (dma_to_memory) {
635 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
636 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
637 dma_sconfig.src_maxburst = 0;
638 } else {
639 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
640 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
641 dma_sconfig.dst_maxburst = 0;
642 }
643
644 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
645 if (ret)
646 goto scrub;
647 if (dma_to_memory) {
648 tspi->rx_dma_chan = dma_chan;
649 tspi->rx_dma_buf = dma_buf;
650 tspi->rx_dma_phys = dma_phys;
651 } else {
652 tspi->tx_dma_chan = dma_chan;
653 tspi->tx_dma_buf = dma_buf;
654 tspi->tx_dma_phys = dma_phys;
655 }
656 return 0;
657
658 scrub:
659 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
660 dma_release_channel(dma_chan);
661 return ret;
662 }
663
tegra_spi_deinit_dma_param(struct tegra_spi_data * tspi,bool dma_to_memory)664 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
665 bool dma_to_memory)
666 {
667 u32 *dma_buf;
668 dma_addr_t dma_phys;
669 struct dma_chan *dma_chan;
670
671 if (dma_to_memory) {
672 dma_buf = tspi->rx_dma_buf;
673 dma_chan = tspi->rx_dma_chan;
674 dma_phys = tspi->rx_dma_phys;
675 tspi->rx_dma_chan = NULL;
676 tspi->rx_dma_buf = NULL;
677 } else {
678 dma_buf = tspi->tx_dma_buf;
679 dma_chan = tspi->tx_dma_chan;
680 dma_phys = tspi->tx_dma_phys;
681 tspi->tx_dma_buf = NULL;
682 tspi->tx_dma_chan = NULL;
683 }
684 if (!dma_chan)
685 return;
686
687 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
688 dma_release_channel(dma_chan);
689 }
690
tegra_spi_setup_transfer_one(struct spi_device * spi,struct spi_transfer * t,bool is_first_of_msg)691 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
692 struct spi_transfer *t, bool is_first_of_msg)
693 {
694 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
695 u32 speed = t->speed_hz;
696 u8 bits_per_word = t->bits_per_word;
697 u32 command1;
698 int req_mode;
699
700 if (speed != tspi->cur_speed) {
701 clk_set_rate(tspi->clk, speed);
702 tspi->cur_speed = speed;
703 }
704
705 tspi->cur_spi = spi;
706 tspi->cur_pos = 0;
707 tspi->cur_rx_pos = 0;
708 tspi->cur_tx_pos = 0;
709 tspi->curr_xfer = t;
710
711 if (is_first_of_msg) {
712 tegra_spi_clear_status(tspi);
713
714 command1 = tspi->def_command1_reg;
715 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
716
717 command1 &= ~SPI_CONTROL_MODE_MASK;
718 req_mode = spi->mode & 0x3;
719 if (req_mode == SPI_MODE_0)
720 command1 |= SPI_CONTROL_MODE_0;
721 else if (req_mode == SPI_MODE_1)
722 command1 |= SPI_CONTROL_MODE_1;
723 else if (req_mode == SPI_MODE_2)
724 command1 |= SPI_CONTROL_MODE_2;
725 else if (req_mode == SPI_MODE_3)
726 command1 |= SPI_CONTROL_MODE_3;
727
728 if (tspi->cs_control) {
729 if (tspi->cs_control != spi)
730 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
731 tspi->cs_control = NULL;
732 } else
733 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
734
735 command1 |= SPI_CS_SW_HW;
736 if (spi->mode & SPI_CS_HIGH)
737 command1 |= SPI_CS_SS_VAL;
738 else
739 command1 &= ~SPI_CS_SS_VAL;
740
741 tegra_spi_writel(tspi, 0, SPI_COMMAND2);
742 } else {
743 command1 = tspi->command1_reg;
744 command1 &= ~SPI_BIT_LENGTH(~0);
745 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
746 }
747
748 return command1;
749 }
750
tegra_spi_start_transfer_one(struct spi_device * spi,struct spi_transfer * t,u32 command1)751 static int tegra_spi_start_transfer_one(struct spi_device *spi,
752 struct spi_transfer *t, u32 command1)
753 {
754 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
755 unsigned total_fifo_words;
756 int ret;
757
758 total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
759
760 if (tspi->is_packed)
761 command1 |= SPI_PACKED;
762 else
763 command1 &= ~SPI_PACKED;
764
765 command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
766 tspi->cur_direction = 0;
767 if (t->rx_buf) {
768 command1 |= SPI_RX_EN;
769 tspi->cur_direction |= DATA_DIR_RX;
770 }
771 if (t->tx_buf) {
772 command1 |= SPI_TX_EN;
773 tspi->cur_direction |= DATA_DIR_TX;
774 }
775 command1 |= SPI_CS_SEL(spi->chip_select);
776 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
777 tspi->command1_reg = command1;
778
779 dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
780 tspi->def_command1_reg, (unsigned)command1);
781
782 if (total_fifo_words > SPI_FIFO_DEPTH)
783 ret = tegra_spi_start_dma_based_transfer(tspi, t);
784 else
785 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
786 return ret;
787 }
788
tegra_spi_setup(struct spi_device * spi)789 static int tegra_spi_setup(struct spi_device *spi)
790 {
791 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
792 u32 val;
793 unsigned long flags;
794 int ret;
795
796 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
797 spi->bits_per_word,
798 spi->mode & SPI_CPOL ? "" : "~",
799 spi->mode & SPI_CPHA ? "" : "~",
800 spi->max_speed_hz);
801
802 ret = pm_runtime_get_sync(tspi->dev);
803 if (ret < 0) {
804 pm_runtime_put_noidle(tspi->dev);
805 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
806 return ret;
807 }
808
809 spin_lock_irqsave(&tspi->lock, flags);
810 val = tspi->def_command1_reg;
811 if (spi->mode & SPI_CS_HIGH)
812 val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
813 else
814 val |= SPI_CS_POL_INACTIVE(spi->chip_select);
815 tspi->def_command1_reg = val;
816 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
817 spin_unlock_irqrestore(&tspi->lock, flags);
818
819 pm_runtime_put(tspi->dev);
820 return 0;
821 }
822
tegra_spi_transfer_delay(int delay)823 static void tegra_spi_transfer_delay(int delay)
824 {
825 if (!delay)
826 return;
827
828 if (delay >= 1000)
829 mdelay(delay / 1000);
830
831 udelay(delay % 1000);
832 }
833
tegra_spi_transfer_one_message(struct spi_master * master,struct spi_message * msg)834 static int tegra_spi_transfer_one_message(struct spi_master *master,
835 struct spi_message *msg)
836 {
837 bool is_first_msg = true;
838 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
839 struct spi_transfer *xfer;
840 struct spi_device *spi = msg->spi;
841 int ret;
842 bool skip = false;
843
844 msg->status = 0;
845 msg->actual_length = 0;
846
847 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
848 u32 cmd1;
849
850 reinit_completion(&tspi->xfer_completion);
851
852 cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg);
853
854 if (!xfer->len) {
855 ret = 0;
856 skip = true;
857 goto complete_xfer;
858 }
859
860 ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
861 if (ret < 0) {
862 dev_err(tspi->dev,
863 "spi can not start transfer, err %d\n", ret);
864 goto complete_xfer;
865 }
866
867 is_first_msg = false;
868 ret = wait_for_completion_timeout(&tspi->xfer_completion,
869 SPI_DMA_TIMEOUT);
870 if (WARN_ON(ret == 0)) {
871 dev_err(tspi->dev,
872 "spi trasfer timeout, err %d\n", ret);
873 ret = -EIO;
874 goto complete_xfer;
875 }
876
877 if (tspi->tx_status || tspi->rx_status) {
878 dev_err(tspi->dev, "Error in Transfer\n");
879 ret = -EIO;
880 goto complete_xfer;
881 }
882 msg->actual_length += xfer->len;
883
884 complete_xfer:
885 if (ret < 0 || skip) {
886 tegra_spi_writel(tspi, tspi->def_command1_reg,
887 SPI_COMMAND1);
888 tegra_spi_transfer_delay(xfer->delay_usecs);
889 goto exit;
890 } else if (list_is_last(&xfer->transfer_list,
891 &msg->transfers)) {
892 if (xfer->cs_change)
893 tspi->cs_control = spi;
894 else {
895 tegra_spi_writel(tspi, tspi->def_command1_reg,
896 SPI_COMMAND1);
897 tegra_spi_transfer_delay(xfer->delay_usecs);
898 }
899 } else if (xfer->cs_change) {
900 tegra_spi_writel(tspi, tspi->def_command1_reg,
901 SPI_COMMAND1);
902 tegra_spi_transfer_delay(xfer->delay_usecs);
903 }
904
905 }
906 ret = 0;
907 exit:
908 msg->status = ret;
909 spi_finalize_current_message(master);
910 return ret;
911 }
912
handle_cpu_based_xfer(struct tegra_spi_data * tspi)913 static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
914 {
915 struct spi_transfer *t = tspi->curr_xfer;
916 unsigned long flags;
917
918 spin_lock_irqsave(&tspi->lock, flags);
919 if (tspi->tx_status || tspi->rx_status) {
920 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
921 tspi->status_reg);
922 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
923 tspi->command1_reg, tspi->dma_control_reg);
924 reset_control_assert(tspi->rst);
925 udelay(2);
926 reset_control_deassert(tspi->rst);
927 complete(&tspi->xfer_completion);
928 goto exit;
929 }
930
931 if (tspi->cur_direction & DATA_DIR_RX)
932 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
933
934 if (tspi->cur_direction & DATA_DIR_TX)
935 tspi->cur_pos = tspi->cur_tx_pos;
936 else
937 tspi->cur_pos = tspi->cur_rx_pos;
938
939 if (tspi->cur_pos == t->len) {
940 complete(&tspi->xfer_completion);
941 goto exit;
942 }
943
944 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
945 tegra_spi_start_cpu_based_transfer(tspi, t);
946 exit:
947 spin_unlock_irqrestore(&tspi->lock, flags);
948 return IRQ_HANDLED;
949 }
950
handle_dma_based_xfer(struct tegra_spi_data * tspi)951 static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
952 {
953 struct spi_transfer *t = tspi->curr_xfer;
954 long wait_status;
955 int err = 0;
956 unsigned total_fifo_words;
957 unsigned long flags;
958
959 /* Abort dmas if any error */
960 if (tspi->cur_direction & DATA_DIR_TX) {
961 if (tspi->tx_status) {
962 dmaengine_terminate_all(tspi->tx_dma_chan);
963 err += 1;
964 } else {
965 wait_status = wait_for_completion_interruptible_timeout(
966 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
967 if (wait_status <= 0) {
968 dmaengine_terminate_all(tspi->tx_dma_chan);
969 dev_err(tspi->dev, "TxDma Xfer failed\n");
970 err += 1;
971 }
972 }
973 }
974
975 if (tspi->cur_direction & DATA_DIR_RX) {
976 if (tspi->rx_status) {
977 dmaengine_terminate_all(tspi->rx_dma_chan);
978 err += 2;
979 } else {
980 wait_status = wait_for_completion_interruptible_timeout(
981 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
982 if (wait_status <= 0) {
983 dmaengine_terminate_all(tspi->rx_dma_chan);
984 dev_err(tspi->dev, "RxDma Xfer failed\n");
985 err += 2;
986 }
987 }
988 }
989
990 spin_lock_irqsave(&tspi->lock, flags);
991 if (err) {
992 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
993 tspi->status_reg);
994 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
995 tspi->command1_reg, tspi->dma_control_reg);
996 reset_control_assert(tspi->rst);
997 udelay(2);
998 reset_control_deassert(tspi->rst);
999 complete(&tspi->xfer_completion);
1000 spin_unlock_irqrestore(&tspi->lock, flags);
1001 return IRQ_HANDLED;
1002 }
1003
1004 if (tspi->cur_direction & DATA_DIR_RX)
1005 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
1006
1007 if (tspi->cur_direction & DATA_DIR_TX)
1008 tspi->cur_pos = tspi->cur_tx_pos;
1009 else
1010 tspi->cur_pos = tspi->cur_rx_pos;
1011
1012 if (tspi->cur_pos == t->len) {
1013 complete(&tspi->xfer_completion);
1014 goto exit;
1015 }
1016
1017 /* Continue transfer in current message */
1018 total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
1019 tspi, t);
1020 if (total_fifo_words > SPI_FIFO_DEPTH)
1021 err = tegra_spi_start_dma_based_transfer(tspi, t);
1022 else
1023 err = tegra_spi_start_cpu_based_transfer(tspi, t);
1024
1025 exit:
1026 spin_unlock_irqrestore(&tspi->lock, flags);
1027 return IRQ_HANDLED;
1028 }
1029
tegra_spi_isr_thread(int irq,void * context_data)1030 static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
1031 {
1032 struct tegra_spi_data *tspi = context_data;
1033
1034 if (!tspi->is_curr_dma_xfer)
1035 return handle_cpu_based_xfer(tspi);
1036 return handle_dma_based_xfer(tspi);
1037 }
1038
tegra_spi_isr(int irq,void * context_data)1039 static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1040 {
1041 struct tegra_spi_data *tspi = context_data;
1042
1043 tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1044 if (tspi->cur_direction & DATA_DIR_TX)
1045 tspi->tx_status = tspi->status_reg &
1046 (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1047
1048 if (tspi->cur_direction & DATA_DIR_RX)
1049 tspi->rx_status = tspi->status_reg &
1050 (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1051 tegra_spi_clear_status(tspi);
1052
1053 return IRQ_WAKE_THREAD;
1054 }
1055
1056 static const struct of_device_id tegra_spi_of_match[] = {
1057 { .compatible = "nvidia,tegra114-spi", },
1058 {}
1059 };
1060 MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1061
tegra_spi_probe(struct platform_device * pdev)1062 static int tegra_spi_probe(struct platform_device *pdev)
1063 {
1064 struct spi_master *master;
1065 struct tegra_spi_data *tspi;
1066 struct resource *r;
1067 int ret, spi_irq;
1068
1069 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1070 if (!master) {
1071 dev_err(&pdev->dev, "master allocation failed\n");
1072 return -ENOMEM;
1073 }
1074 platform_set_drvdata(pdev, master);
1075 tspi = spi_master_get_devdata(master);
1076
1077 if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1078 &master->max_speed_hz))
1079 master->max_speed_hz = 25000000; /* 25MHz */
1080
1081 /* the spi->mode bits understood by this driver: */
1082 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1083 master->setup = tegra_spi_setup;
1084 master->transfer_one_message = tegra_spi_transfer_one_message;
1085 master->num_chipselect = MAX_CHIP_SELECT;
1086 master->auto_runtime_pm = true;
1087
1088 tspi->master = master;
1089 tspi->dev = &pdev->dev;
1090 spin_lock_init(&tspi->lock);
1091
1092 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1093 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1094 if (IS_ERR(tspi->base)) {
1095 ret = PTR_ERR(tspi->base);
1096 goto exit_free_master;
1097 }
1098 tspi->phys = r->start;
1099
1100 spi_irq = platform_get_irq(pdev, 0);
1101 tspi->irq = spi_irq;
1102
1103 tspi->clk = devm_clk_get(&pdev->dev, "spi");
1104 if (IS_ERR(tspi->clk)) {
1105 dev_err(&pdev->dev, "can not get clock\n");
1106 ret = PTR_ERR(tspi->clk);
1107 goto exit_free_master;
1108 }
1109
1110 tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
1111 if (IS_ERR(tspi->rst)) {
1112 dev_err(&pdev->dev, "can not get reset\n");
1113 ret = PTR_ERR(tspi->rst);
1114 goto exit_free_master;
1115 }
1116
1117 tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1118 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1119
1120 ret = tegra_spi_init_dma_param(tspi, true);
1121 if (ret < 0)
1122 goto exit_free_master;
1123 ret = tegra_spi_init_dma_param(tspi, false);
1124 if (ret < 0)
1125 goto exit_rx_dma_free;
1126 tspi->max_buf_size = tspi->dma_buf_size;
1127 init_completion(&tspi->tx_dma_complete);
1128 init_completion(&tspi->rx_dma_complete);
1129
1130 init_completion(&tspi->xfer_completion);
1131
1132 pm_runtime_enable(&pdev->dev);
1133 if (!pm_runtime_enabled(&pdev->dev)) {
1134 ret = tegra_spi_runtime_resume(&pdev->dev);
1135 if (ret)
1136 goto exit_pm_disable;
1137 }
1138
1139 ret = pm_runtime_get_sync(&pdev->dev);
1140 if (ret < 0) {
1141 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1142 goto exit_pm_disable;
1143 }
1144
1145 reset_control_assert(tspi->rst);
1146 udelay(2);
1147 reset_control_deassert(tspi->rst);
1148 tspi->def_command1_reg = SPI_M_S;
1149 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1150 pm_runtime_put(&pdev->dev);
1151 ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1152 tegra_spi_isr_thread, IRQF_ONESHOT,
1153 dev_name(&pdev->dev), tspi);
1154 if (ret < 0) {
1155 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1156 tspi->irq);
1157 goto exit_pm_disable;
1158 }
1159
1160 master->dev.of_node = pdev->dev.of_node;
1161 ret = devm_spi_register_master(&pdev->dev, master);
1162 if (ret < 0) {
1163 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1164 goto exit_free_irq;
1165 }
1166 return ret;
1167
1168 exit_free_irq:
1169 free_irq(spi_irq, tspi);
1170 exit_pm_disable:
1171 pm_runtime_disable(&pdev->dev);
1172 if (!pm_runtime_status_suspended(&pdev->dev))
1173 tegra_spi_runtime_suspend(&pdev->dev);
1174 tegra_spi_deinit_dma_param(tspi, false);
1175 exit_rx_dma_free:
1176 tegra_spi_deinit_dma_param(tspi, true);
1177 exit_free_master:
1178 spi_master_put(master);
1179 return ret;
1180 }
1181
tegra_spi_remove(struct platform_device * pdev)1182 static int tegra_spi_remove(struct platform_device *pdev)
1183 {
1184 struct spi_master *master = platform_get_drvdata(pdev);
1185 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1186
1187 free_irq(tspi->irq, tspi);
1188
1189 if (tspi->tx_dma_chan)
1190 tegra_spi_deinit_dma_param(tspi, false);
1191
1192 if (tspi->rx_dma_chan)
1193 tegra_spi_deinit_dma_param(tspi, true);
1194
1195 pm_runtime_disable(&pdev->dev);
1196 if (!pm_runtime_status_suspended(&pdev->dev))
1197 tegra_spi_runtime_suspend(&pdev->dev);
1198
1199 return 0;
1200 }
1201
1202 #ifdef CONFIG_PM_SLEEP
tegra_spi_suspend(struct device * dev)1203 static int tegra_spi_suspend(struct device *dev)
1204 {
1205 struct spi_master *master = dev_get_drvdata(dev);
1206
1207 return spi_master_suspend(master);
1208 }
1209
tegra_spi_resume(struct device * dev)1210 static int tegra_spi_resume(struct device *dev)
1211 {
1212 struct spi_master *master = dev_get_drvdata(dev);
1213 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1214 int ret;
1215
1216 ret = pm_runtime_get_sync(dev);
1217 if (ret < 0) {
1218 pm_runtime_put_noidle(dev);
1219 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1220 return ret;
1221 }
1222 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1223 pm_runtime_put(dev);
1224
1225 return spi_master_resume(master);
1226 }
1227 #endif
1228
tegra_spi_runtime_suspend(struct device * dev)1229 static int tegra_spi_runtime_suspend(struct device *dev)
1230 {
1231 struct spi_master *master = dev_get_drvdata(dev);
1232 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1233
1234 /* Flush all write which are in PPSB queue by reading back */
1235 tegra_spi_readl(tspi, SPI_COMMAND1);
1236
1237 clk_disable_unprepare(tspi->clk);
1238 return 0;
1239 }
1240
tegra_spi_runtime_resume(struct device * dev)1241 static int tegra_spi_runtime_resume(struct device *dev)
1242 {
1243 struct spi_master *master = dev_get_drvdata(dev);
1244 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1245 int ret;
1246
1247 ret = clk_prepare_enable(tspi->clk);
1248 if (ret < 0) {
1249 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1250 return ret;
1251 }
1252 return 0;
1253 }
1254
1255 static const struct dev_pm_ops tegra_spi_pm_ops = {
1256 SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1257 tegra_spi_runtime_resume, NULL)
1258 SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1259 };
1260 static struct platform_driver tegra_spi_driver = {
1261 .driver = {
1262 .name = "spi-tegra114",
1263 .pm = &tegra_spi_pm_ops,
1264 .of_match_table = tegra_spi_of_match,
1265 },
1266 .probe = tegra_spi_probe,
1267 .remove = tegra_spi_remove,
1268 };
1269 module_platform_driver(tegra_spi_driver);
1270
1271 MODULE_ALIAS("platform:spi-tegra114");
1272 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1273 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1274 MODULE_LICENSE("GPL v2");
1275