1 /*
2 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
3 * (master mode only)
4 *
5 * Copyright (C) 2009 - 2015 Xilinx, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_address.h>
22 #include <linux/platform_device.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spinlock.h>
25 #include <linux/workqueue.h>
26
27 /* Generic QSPI register offsets */
28 #define GQSPI_CONFIG_OFST 0x00000100
29 #define GQSPI_ISR_OFST 0x00000104
30 #define GQSPI_IDR_OFST 0x0000010C
31 #define GQSPI_IER_OFST 0x00000108
32 #define GQSPI_IMASK_OFST 0x00000110
33 #define GQSPI_EN_OFST 0x00000114
34 #define GQSPI_TXD_OFST 0x0000011C
35 #define GQSPI_RXD_OFST 0x00000120
36 #define GQSPI_TX_THRESHOLD_OFST 0x00000128
37 #define GQSPI_RX_THRESHOLD_OFST 0x0000012C
38 #define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
39 #define GQSPI_GEN_FIFO_OFST 0x00000140
40 #define GQSPI_SEL_OFST 0x00000144
41 #define GQSPI_GF_THRESHOLD_OFST 0x00000150
42 #define GQSPI_FIFO_CTRL_OFST 0x0000014C
43 #define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
44 #define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
45 #define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808
46 #define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814
47 #define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
48 #define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C
49 #define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
50 #define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
51 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
52
53 /* GQSPI register bit masks */
54 #define GQSPI_SEL_MASK 0x00000001
55 #define GQSPI_EN_MASK 0x00000001
56 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
57 #define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002
58 #define GQSPI_IDR_ALL_MASK 0x00000FBE
59 #define GQSPI_CFG_MODE_EN_MASK 0xC0000000
60 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000
61 #define GQSPI_CFG_ENDIAN_MASK 0x04000000
62 #define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000
63 #define GQSPI_CFG_WP_HOLD_MASK 0x00080000
64 #define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038
65 #define GQSPI_CFG_CLK_PHA_MASK 0x00000004
66 #define GQSPI_CFG_CLK_POL_MASK 0x00000002
67 #define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000
68 #define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF
69 #define GQSPI_GENFIFO_DATA_XFER 0x00000100
70 #define GQSPI_GENFIFO_EXP 0x00000200
71 #define GQSPI_GENFIFO_MODE_SPI 0x00000400
72 #define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800
73 #define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00
74 #define GQSPI_GENFIFO_MODE_MASK 0x00000C00
75 #define GQSPI_GENFIFO_CS_LOWER 0x00001000
76 #define GQSPI_GENFIFO_CS_UPPER 0x00002000
77 #define GQSPI_GENFIFO_BUS_LOWER 0x00004000
78 #define GQSPI_GENFIFO_BUS_UPPER 0x00008000
79 #define GQSPI_GENFIFO_BUS_BOTH 0x0000C000
80 #define GQSPI_GENFIFO_BUS_MASK 0x0000C000
81 #define GQSPI_GENFIFO_TX 0x00010000
82 #define GQSPI_GENFIFO_RX 0x00020000
83 #define GQSPI_GENFIFO_STRIPE 0x00040000
84 #define GQSPI_GENFIFO_POLL 0x00080000
85 #define GQSPI_GENFIFO_EXP_START 0x00000100
86 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
87 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
88 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
89 #define GQSPI_ISR_RXEMPTY_MASK 0x00000800
90 #define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400
91 #define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200
92 #define GQSPI_ISR_TXEMPTY_MASK 0x00000100
93 #define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080
94 #define GQSPI_ISR_RXFULL_MASK 0x00000020
95 #define GQSPI_ISR_RXNEMPTY_MASK 0x00000010
96 #define GQSPI_ISR_TXFULL_MASK 0x00000008
97 #define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004
98 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002
99 #define GQSPI_IER_TXNOT_FULL_MASK 0x00000004
100 #define GQSPI_IER_RXEMPTY_MASK 0x00000800
101 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002
102 #define GQSPI_IER_RXNEMPTY_MASK 0x00000010
103 #define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080
104 #define GQSPI_IER_TXEMPTY_MASK 0x00000100
105 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE
106 #define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000
107 #define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000
108 #define GQSPI_ISR_IDR_MASK 0x00000994
109 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002
110 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002
111 #define GQSPI_IRQ_MASK 0x00000980
112
113 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3
114 #define GQSPI_GENFIFO_CS_SETUP 0x4
115 #define GQSPI_GENFIFO_CS_HOLD 0x3
116 #define GQSPI_TXD_DEPTH 64
117 #define GQSPI_RX_FIFO_THRESHOLD 32
118 #define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)
119 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32
120 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
121 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
122 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
123 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
124 #define GQSPI_SELECT_FLASH_CS_LOWER 0x1
125 #define GQSPI_SELECT_FLASH_CS_UPPER 0x2
126 #define GQSPI_SELECT_FLASH_CS_BOTH 0x3
127 #define GQSPI_SELECT_FLASH_BUS_LOWER 0x1
128 #define GQSPI_SELECT_FLASH_BUS_UPPER 0x2
129 #define GQSPI_SELECT_FLASH_BUS_BOTH 0x3
130 #define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
131 #define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */
132 #define GQSPI_SELECT_MODE_SPI 0x1
133 #define GQSPI_SELECT_MODE_DUALSPI 0x2
134 #define GQSPI_SELECT_MODE_QUADSPI 0x4
135 #define GQSPI_DMA_UNALIGN 0x3
136 #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
137
138 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
139
140 /**
141 * struct zynqmp_qspi - Defines qspi driver instance
142 * @regs: Virtual address of the QSPI controller registers
143 * @refclk: Pointer to the peripheral clock
144 * @pclk: Pointer to the APB clock
145 * @irq: IRQ number
146 * @dev: Pointer to struct device
147 * @txbuf: Pointer to the TX buffer
148 * @rxbuf: Pointer to the RX buffer
149 * @bytes_to_transfer: Number of bytes left to transfer
150 * @bytes_to_receive: Number of bytes left to receive
151 * @genfifocs: Used for chip select
152 * @genfifobus: Used to select the upper or lower bus
153 * @dma_rx_bytes: Remaining bytes to receive by DMA mode
154 * @dma_addr: DMA address after mapping the kernel buffer
155 * @genfifoentry: Used for storing the genfifoentry instruction.
156 * @mode: Defines the mode in which QSPI is operating
157 */
158 struct zynqmp_qspi {
159 void __iomem *regs;
160 struct clk *refclk;
161 struct clk *pclk;
162 int irq;
163 struct device *dev;
164 const void *txbuf;
165 void *rxbuf;
166 int bytes_to_transfer;
167 int bytes_to_receive;
168 u32 genfifocs;
169 u32 genfifobus;
170 u32 dma_rx_bytes;
171 dma_addr_t dma_addr;
172 u32 genfifoentry;
173 enum mode_type mode;
174 };
175
176 /**
177 * zynqmp_gqspi_read: For GQSPI controller read operation
178 * @xqspi: Pointer to the zynqmp_qspi structure
179 * @offset: Offset from where to read
180 */
zynqmp_gqspi_read(struct zynqmp_qspi * xqspi,u32 offset)181 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
182 {
183 return readl_relaxed(xqspi->regs + offset);
184 }
185
186 /**
187 * zynqmp_gqspi_write: For GQSPI controller write operation
188 * @xqspi: Pointer to the zynqmp_qspi structure
189 * @offset: Offset where to write
190 * @val: Value to be written
191 */
zynqmp_gqspi_write(struct zynqmp_qspi * xqspi,u32 offset,u32 val)192 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
193 u32 val)
194 {
195 writel_relaxed(val, (xqspi->regs + offset));
196 }
197
198 /**
199 * zynqmp_gqspi_selectslave: For selection of slave device
200 * @instanceptr: Pointer to the zynqmp_qspi structure
201 * @flashcs: For chip select
202 * @flashbus: To check which bus is selected- upper or lower
203 */
zynqmp_gqspi_selectslave(struct zynqmp_qspi * instanceptr,u8 slavecs,u8 slavebus)204 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
205 u8 slavecs, u8 slavebus)
206 {
207 /*
208 * Bus and CS lines selected here will be updated in the instance and
209 * used for subsequent GENFIFO entries during transfer.
210 */
211
212 /* Choose slave select line */
213 switch (slavecs) {
214 case GQSPI_SELECT_FLASH_CS_BOTH:
215 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
216 GQSPI_GENFIFO_CS_UPPER;
217 break;
218 case GQSPI_SELECT_FLASH_CS_UPPER:
219 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
220 break;
221 case GQSPI_SELECT_FLASH_CS_LOWER:
222 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
223 break;
224 default:
225 dev_warn(instanceptr->dev, "Invalid slave select\n");
226 }
227
228 /* Choose the bus */
229 switch (slavebus) {
230 case GQSPI_SELECT_FLASH_BUS_BOTH:
231 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
232 GQSPI_GENFIFO_BUS_UPPER;
233 break;
234 case GQSPI_SELECT_FLASH_BUS_UPPER:
235 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
236 break;
237 case GQSPI_SELECT_FLASH_BUS_LOWER:
238 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
239 break;
240 default:
241 dev_warn(instanceptr->dev, "Invalid slave bus\n");
242 }
243 }
244
245 /**
246 * zynqmp_qspi_init_hw: Initialize the hardware
247 * @xqspi: Pointer to the zynqmp_qspi structure
248 *
249 * The default settings of the QSPI controller's configurable parameters on
250 * reset are
251 * - Master mode
252 * - TX threshold set to 1
253 * - RX threshold set to 1
254 * - Flash memory interface mode enabled
255 * This function performs the following actions
256 * - Disable and clear all the interrupts
257 * - Enable manual slave select
258 * - Enable manual start
259 * - Deselect all the chip select lines
260 * - Set the little endian mode of TX FIFO and
261 * - Enable the QSPI controller
262 */
zynqmp_qspi_init_hw(struct zynqmp_qspi * xqspi)263 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
264 {
265 u32 config_reg;
266
267 /* Select the GQSPI mode */
268 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
269 /* Clear and disable interrupts */
270 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
271 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
272 GQSPI_ISR_WR_TO_CLR_MASK);
273 /* Clear the DMA STS */
274 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
275 zynqmp_gqspi_read(xqspi,
276 GQSPI_QSPIDMA_DST_I_STS_OFST));
277 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
278 zynqmp_gqspi_read(xqspi,
279 GQSPI_QSPIDMA_DST_STS_OFST) |
280 GQSPI_QSPIDMA_DST_STS_WTC);
281 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
282 zynqmp_gqspi_write(xqspi,
283 GQSPI_QSPIDMA_DST_I_DIS_OFST,
284 GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
285 /* Disable the GQSPI */
286 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
287 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
288 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
289 /* Manual start */
290 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
291 /* Little endian by default */
292 config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
293 /* Disable poll time out */
294 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
295 /* Set hold bit */
296 config_reg |= GQSPI_CFG_WP_HOLD_MASK;
297 /* Clear pre-scalar by default */
298 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
299 /* CPHA 0 */
300 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
301 /* CPOL 0 */
302 config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
303 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
304
305 /* Clear the TX and RX FIFO */
306 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
307 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
308 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
309 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
310 /* Set by default to allow for high frequencies */
311 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
312 zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
313 GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
314 /* Reset thresholds */
315 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
316 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
317 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
318 GQSPI_RX_FIFO_THRESHOLD);
319 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
320 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
321 zynqmp_gqspi_selectslave(xqspi,
322 GQSPI_SELECT_FLASH_CS_LOWER,
323 GQSPI_SELECT_FLASH_BUS_LOWER);
324 /* Initialize DMA */
325 zynqmp_gqspi_write(xqspi,
326 GQSPI_QSPIDMA_DST_CTRL_OFST,
327 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
328
329 /* Enable the GQSPI */
330 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
331 }
332
333 /**
334 * zynqmp_qspi_copy_read_data: Copy data to RX buffer
335 * @xqspi: Pointer to the zynqmp_qspi structure
336 * @data: The variable where data is stored
337 * @size: Number of bytes to be copied from data to RX buffer
338 */
zynqmp_qspi_copy_read_data(struct zynqmp_qspi * xqspi,ulong data,u8 size)339 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
340 ulong data, u8 size)
341 {
342 memcpy(xqspi->rxbuf, &data, size);
343 xqspi->rxbuf += size;
344 xqspi->bytes_to_receive -= size;
345 }
346
347 /**
348 * zynqmp_prepare_transfer_hardware: Prepares hardware for transfer.
349 * @master: Pointer to the spi_master structure which provides
350 * information about the controller.
351 *
352 * This function enables SPI master controller.
353 *
354 * Return: 0 on success; error value otherwise
355 */
zynqmp_prepare_transfer_hardware(struct spi_master * master)356 static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
357 {
358 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
359 int ret;
360
361 ret = clk_enable(xqspi->refclk);
362 if (ret)
363 goto clk_err;
364
365 ret = clk_enable(xqspi->pclk);
366 if (ret)
367 goto clk_err;
368
369 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
370 return 0;
371 clk_err:
372 return ret;
373 }
374
375 /**
376 * zynqmp_unprepare_transfer_hardware: Relaxes hardware after transfer
377 * @master: Pointer to the spi_master structure which provides
378 * information about the controller.
379 *
380 * This function disables the SPI master controller.
381 *
382 * Return: Always 0
383 */
zynqmp_unprepare_transfer_hardware(struct spi_master * master)384 static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
385 {
386 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
387
388 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
389 clk_disable(xqspi->refclk);
390 clk_disable(xqspi->pclk);
391 return 0;
392 }
393
394 /**
395 * zynqmp_qspi_chipselect: Select or deselect the chip select line
396 * @qspi: Pointer to the spi_device structure
397 * @is_high: Select(0) or deselect (1) the chip select line
398 */
zynqmp_qspi_chipselect(struct spi_device * qspi,bool is_high)399 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
400 {
401 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
402 ulong timeout;
403 u32 genfifoentry = 0x0, statusreg;
404
405 genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
406 genfifoentry |= xqspi->genfifobus;
407
408 if (!is_high) {
409 genfifoentry |= xqspi->genfifocs;
410 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
411 } else {
412 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
413 }
414
415 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
416
417 /* Manually start the generic FIFO command */
418 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
419 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
420 GQSPI_CFG_START_GEN_FIFO_MASK);
421
422 timeout = jiffies + msecs_to_jiffies(1000);
423
424 /* Wait until the generic FIFO command is empty */
425 do {
426 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
427
428 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
429 (statusreg & GQSPI_ISR_TXEMPTY_MASK))
430 break;
431 else
432 cpu_relax();
433 } while (!time_after_eq(jiffies, timeout));
434
435 if (time_after_eq(jiffies, timeout))
436 dev_err(xqspi->dev, "Chip select timed out\n");
437 }
438
439 /**
440 * zynqmp_qspi_setup_transfer: Configure QSPI controller for specified
441 * transfer
442 * @qspi: Pointer to the spi_device structure
443 * @transfer: Pointer to the spi_transfer structure which provides
444 * information about next transfer setup parameters
445 *
446 * Sets the operational mode of QSPI controller for the next QSPI transfer and
447 * sets the requested clock frequency.
448 *
449 * Return: Always 0
450 *
451 * Note:
452 * If the requested frequency is not an exact match with what can be
453 * obtained using the pre-scalar value, the driver sets the clock
454 * frequency which is lower than the requested frequency (maximum lower)
455 * for the transfer.
456 *
457 * If the requested frequency is higher or lower than that is supported
458 * by the QSPI controller the driver will set the highest or lowest
459 * frequency supported by controller.
460 */
zynqmp_qspi_setup_transfer(struct spi_device * qspi,struct spi_transfer * transfer)461 static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
462 struct spi_transfer *transfer)
463 {
464 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
465 ulong clk_rate;
466 u32 config_reg, req_hz, baud_rate_val = 0;
467
468 if (transfer)
469 req_hz = transfer->speed_hz;
470 else
471 req_hz = qspi->max_speed_hz;
472
473 /* Set the clock frequency */
474 /* If req_hz == 0, default to lowest speed */
475 clk_rate = clk_get_rate(xqspi->refclk);
476
477 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
478 (clk_rate /
479 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
480 baud_rate_val++;
481
482 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
483
484 /* Set the QSPI clock phase and clock polarity */
485 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
486
487 if (qspi->mode & SPI_CPHA)
488 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
489 if (qspi->mode & SPI_CPOL)
490 config_reg |= GQSPI_CFG_CLK_POL_MASK;
491
492 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
493 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
494 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
495 return 0;
496 }
497
498 /**
499 * zynqmp_qspi_setup: Configure the QSPI controller
500 * @qspi: Pointer to the spi_device structure
501 *
502 * Sets the operational mode of QSPI controller for the next QSPI transfer,
503 * baud rate and divisor value to setup the requested qspi clock.
504 *
505 * Return: 0 on success; error value otherwise.
506 */
zynqmp_qspi_setup(struct spi_device * qspi)507 static int zynqmp_qspi_setup(struct spi_device *qspi)
508 {
509 if (qspi->master->busy)
510 return -EBUSY;
511 return 0;
512 }
513
514 /**
515 * zynqmp_qspi_filltxfifo: Fills the TX FIFO as long as there is room in
516 * the FIFO or the bytes required to be
517 * transmitted.
518 * @xqspi: Pointer to the zynqmp_qspi structure
519 * @size: Number of bytes to be copied from TX buffer to TX FIFO
520 */
zynqmp_qspi_filltxfifo(struct zynqmp_qspi * xqspi,int size)521 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
522 {
523 u32 count = 0, intermediate;
524
525 while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
526 memcpy(&intermediate, xqspi->txbuf, 4);
527 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
528
529 if (xqspi->bytes_to_transfer >= 4) {
530 xqspi->txbuf += 4;
531 xqspi->bytes_to_transfer -= 4;
532 } else {
533 xqspi->txbuf += xqspi->bytes_to_transfer;
534 xqspi->bytes_to_transfer = 0;
535 }
536 count++;
537 }
538 }
539
540 /**
541 * zynqmp_qspi_readrxfifo: Fills the RX FIFO as long as there is room in
542 * the FIFO.
543 * @xqspi: Pointer to the zynqmp_qspi structure
544 * @size: Number of bytes to be copied from RX buffer to RX FIFO
545 */
zynqmp_qspi_readrxfifo(struct zynqmp_qspi * xqspi,u32 size)546 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
547 {
548 ulong data;
549 int count = 0;
550
551 while ((count < size) && (xqspi->bytes_to_receive > 0)) {
552 if (xqspi->bytes_to_receive >= 4) {
553 (*(u32 *) xqspi->rxbuf) =
554 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
555 xqspi->rxbuf += 4;
556 xqspi->bytes_to_receive -= 4;
557 count += 4;
558 } else {
559 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
560 count += xqspi->bytes_to_receive;
561 zynqmp_qspi_copy_read_data(xqspi, data,
562 xqspi->bytes_to_receive);
563 xqspi->bytes_to_receive = 0;
564 }
565 }
566 }
567
568 /**
569 * zynqmp_process_dma_irq: Handler for DMA done interrupt of QSPI
570 * controller
571 * @xqspi: zynqmp_qspi instance pointer
572 *
573 * This function handles DMA interrupt only.
574 */
zynqmp_process_dma_irq(struct zynqmp_qspi * xqspi)575 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
576 {
577 u32 config_reg, genfifoentry;
578
579 dma_unmap_single(xqspi->dev, xqspi->dma_addr,
580 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
581 xqspi->rxbuf += xqspi->dma_rx_bytes;
582 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
583 xqspi->dma_rx_bytes = 0;
584
585 /* Disabling the DMA interrupts */
586 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
587 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
588
589 if (xqspi->bytes_to_receive > 0) {
590 /* Switch to IO mode,for remaining bytes to receive */
591 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
592 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
593 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
594
595 /* Initiate the transfer of remaining bytes */
596 genfifoentry = xqspi->genfifoentry;
597 genfifoentry |= xqspi->bytes_to_receive;
598 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
599
600 /* Dummy generic FIFO entry */
601 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
602
603 /* Manual start */
604 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
605 (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
606 GQSPI_CFG_START_GEN_FIFO_MASK));
607
608 /* Enable the RX interrupts for IO mode */
609 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
610 GQSPI_IER_GENFIFOEMPTY_MASK |
611 GQSPI_IER_RXNEMPTY_MASK |
612 GQSPI_IER_RXEMPTY_MASK);
613 }
614 }
615
616 /**
617 * zynqmp_qspi_irq: Interrupt service routine of the QSPI controller
618 * @irq: IRQ number
619 * @dev_id: Pointer to the xqspi structure
620 *
621 * This function handles TX empty only.
622 * On TX empty interrupt this function reads the received data from RX FIFO
623 * and fills the TX FIFO if there is any data remaining to be transferred.
624 *
625 * Return: IRQ_HANDLED when interrupt is handled
626 * IRQ_NONE otherwise.
627 */
zynqmp_qspi_irq(int irq,void * dev_id)628 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
629 {
630 struct spi_master *master = dev_id;
631 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
632 int ret = IRQ_NONE;
633 u32 status, mask, dma_status = 0;
634
635 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
636 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
637 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
638
639 /* Read and clear DMA status */
640 if (xqspi->mode == GQSPI_MODE_DMA) {
641 dma_status =
642 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
643 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
644 dma_status);
645 }
646
647 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
648 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
649 ret = IRQ_HANDLED;
650 }
651
652 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
653 zynqmp_process_dma_irq(xqspi);
654 ret = IRQ_HANDLED;
655 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
656 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
657 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
658 ret = IRQ_HANDLED;
659 }
660
661 if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
662 && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
663 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
664 spi_finalize_current_transfer(master);
665 ret = IRQ_HANDLED;
666 }
667 return ret;
668 }
669
670 /**
671 * zynqmp_qspi_selectspimode: Selects SPI mode - x1 or x2 or x4.
672 * @xqspi: xqspi is a pointer to the GQSPI instance
673 * @spimode: spimode - SPI or DUAL or QUAD.
674 * Return: Mask to set desired SPI mode in GENFIFO entry.
675 */
zynqmp_qspi_selectspimode(struct zynqmp_qspi * xqspi,u8 spimode)676 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
677 u8 spimode)
678 {
679 u32 mask = 0;
680
681 switch (spimode) {
682 case GQSPI_SELECT_MODE_DUALSPI:
683 mask = GQSPI_GENFIFO_MODE_DUALSPI;
684 break;
685 case GQSPI_SELECT_MODE_QUADSPI:
686 mask = GQSPI_GENFIFO_MODE_QUADSPI;
687 break;
688 case GQSPI_SELECT_MODE_SPI:
689 mask = GQSPI_GENFIFO_MODE_SPI;
690 break;
691 default:
692 dev_warn(xqspi->dev, "Invalid SPI mode\n");
693 }
694
695 return mask;
696 }
697
698 /**
699 * zynq_qspi_setuprxdma: This function sets up the RX DMA operation
700 * @xqspi: xqspi is a pointer to the GQSPI instance.
701 */
zynq_qspi_setuprxdma(struct zynqmp_qspi * xqspi)702 static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
703 {
704 u32 rx_bytes, rx_rem, config_reg;
705 dma_addr_t addr;
706 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
707
708 if ((xqspi->bytes_to_receive < 8) ||
709 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
710 /* Setting to IO mode */
711 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
712 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
713 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
714 xqspi->mode = GQSPI_MODE_IO;
715 xqspi->dma_rx_bytes = 0;
716 return;
717 }
718
719 rx_rem = xqspi->bytes_to_receive % 4;
720 rx_bytes = (xqspi->bytes_to_receive - rx_rem);
721
722 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
723 rx_bytes, DMA_FROM_DEVICE);
724 if (dma_mapping_error(xqspi->dev, addr))
725 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
726
727 xqspi->dma_rx_bytes = rx_bytes;
728 xqspi->dma_addr = addr;
729 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
730 (u32)(addr & 0xffffffff));
731 addr = ((addr >> 16) >> 16);
732 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
733 ((u32)addr) & 0xfff);
734
735 /* Enabling the DMA mode */
736 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
737 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
738 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
739 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
740
741 /* Switch to DMA mode */
742 xqspi->mode = GQSPI_MODE_DMA;
743
744 /* Write the number of bytes to transfer */
745 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
746 }
747
748 /**
749 * zynqmp_qspi_txrxsetup: This function checks the TX/RX buffers in
750 * the transfer and sets up the GENFIFO entries,
751 * TX FIFO as required.
752 * @xqspi: xqspi is a pointer to the GQSPI instance.
753 * @transfer: It is a pointer to the structure containing transfer data.
754 * @genfifoentry: genfifoentry is pointer to the variable in which
755 * GENFIFO mask is returned to calling function
756 */
zynqmp_qspi_txrxsetup(struct zynqmp_qspi * xqspi,struct spi_transfer * transfer,u32 * genfifoentry)757 static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
758 struct spi_transfer *transfer,
759 u32 *genfifoentry)
760 {
761 u32 config_reg;
762
763 /* Transmit */
764 if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
765 /* Setup data to be TXed */
766 *genfifoentry &= ~GQSPI_GENFIFO_RX;
767 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
768 *genfifoentry |= GQSPI_GENFIFO_TX;
769 *genfifoentry |=
770 zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
771 xqspi->bytes_to_transfer = transfer->len;
772 if (xqspi->mode == GQSPI_MODE_DMA) {
773 config_reg = zynqmp_gqspi_read(xqspi,
774 GQSPI_CONFIG_OFST);
775 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
776 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
777 config_reg);
778 xqspi->mode = GQSPI_MODE_IO;
779 }
780 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
781 /* Discard RX data */
782 xqspi->bytes_to_receive = 0;
783 } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
784 /* Receive */
785
786 /* TX auto fill */
787 *genfifoentry &= ~GQSPI_GENFIFO_TX;
788 /* Setup RX */
789 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
790 *genfifoentry |= GQSPI_GENFIFO_RX;
791 *genfifoentry |=
792 zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
793 xqspi->bytes_to_transfer = 0;
794 xqspi->bytes_to_receive = transfer->len;
795 zynq_qspi_setuprxdma(xqspi);
796 }
797 }
798
799 /**
800 * zynqmp_qspi_start_transfer: Initiates the QSPI transfer
801 * @master: Pointer to the spi_master structure which provides
802 * information about the controller.
803 * @qspi: Pointer to the spi_device structure
804 * @transfer: Pointer to the spi_transfer structure which provide information
805 * about next transfer parameters
806 *
807 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
808 * transfer to be completed.
809 *
810 * Return: Number of bytes transferred in the last transfer
811 */
zynqmp_qspi_start_transfer(struct spi_master * master,struct spi_device * qspi,struct spi_transfer * transfer)812 static int zynqmp_qspi_start_transfer(struct spi_master *master,
813 struct spi_device *qspi,
814 struct spi_transfer *transfer)
815 {
816 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
817 u32 genfifoentry = 0x0, transfer_len;
818
819 xqspi->txbuf = transfer->tx_buf;
820 xqspi->rxbuf = transfer->rx_buf;
821
822 zynqmp_qspi_setup_transfer(qspi, transfer);
823
824 genfifoentry |= xqspi->genfifocs;
825 genfifoentry |= xqspi->genfifobus;
826
827 zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
828
829 if (xqspi->mode == GQSPI_MODE_DMA)
830 transfer_len = xqspi->dma_rx_bytes;
831 else
832 transfer_len = transfer->len;
833
834 xqspi->genfifoentry = genfifoentry;
835 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
836 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
837 genfifoentry |= transfer_len;
838 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
839 } else {
840 int tempcount = transfer_len;
841 u32 exponent = 8; /* 2^8 = 256 */
842 u8 imm_data = tempcount & 0xFF;
843
844 tempcount &= ~(tempcount & 0xFF);
845 /* Immediate entry */
846 if (tempcount != 0) {
847 /* Exponent entries */
848 genfifoentry |= GQSPI_GENFIFO_EXP;
849 while (tempcount != 0) {
850 if (tempcount & GQSPI_GENFIFO_EXP_START) {
851 genfifoentry &=
852 ~GQSPI_GENFIFO_IMM_DATA_MASK;
853 genfifoentry |= exponent;
854 zynqmp_gqspi_write(xqspi,
855 GQSPI_GEN_FIFO_OFST,
856 genfifoentry);
857 }
858 tempcount = tempcount >> 1;
859 exponent++;
860 }
861 }
862 if (imm_data != 0) {
863 genfifoentry &= ~GQSPI_GENFIFO_EXP;
864 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
865 genfifoentry |= (u8) (imm_data & 0xFF);
866 zynqmp_gqspi_write(xqspi,
867 GQSPI_GEN_FIFO_OFST, genfifoentry);
868 }
869 }
870
871 if ((xqspi->mode == GQSPI_MODE_IO) &&
872 (xqspi->rxbuf != NULL)) {
873 /* Dummy generic FIFO entry */
874 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
875 }
876
877 /* Since we are using manual mode */
878 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
879 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
880 GQSPI_CFG_START_GEN_FIFO_MASK);
881
882 if (xqspi->txbuf != NULL)
883 /* Enable interrupts for TX */
884 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
885 GQSPI_IER_TXEMPTY_MASK |
886 GQSPI_IER_GENFIFOEMPTY_MASK |
887 GQSPI_IER_TXNOT_FULL_MASK);
888
889 if (xqspi->rxbuf != NULL) {
890 /* Enable interrupts for RX */
891 if (xqspi->mode == GQSPI_MODE_DMA) {
892 /* Enable DMA interrupts */
893 zynqmp_gqspi_write(xqspi,
894 GQSPI_QSPIDMA_DST_I_EN_OFST,
895 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
896 } else {
897 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
898 GQSPI_IER_GENFIFOEMPTY_MASK |
899 GQSPI_IER_RXNEMPTY_MASK |
900 GQSPI_IER_RXEMPTY_MASK);
901 }
902 }
903
904 return transfer->len;
905 }
906
907 /**
908 * zynqmp_qspi_suspend: Suspend method for the QSPI driver
909 * @_dev: Address of the platform_device structure
910 *
911 * This function stops the QSPI driver queue and disables the QSPI controller
912 *
913 * Return: Always 0
914 */
zynqmp_qspi_suspend(struct device * dev)915 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
916 {
917 struct platform_device *pdev = container_of(dev,
918 struct platform_device,
919 dev);
920 struct spi_master *master = platform_get_drvdata(pdev);
921
922 spi_master_suspend(master);
923
924 zynqmp_unprepare_transfer_hardware(master);
925
926 return 0;
927 }
928
929 /**
930 * zynqmp_qspi_resume: Resume method for the QSPI driver
931 * @dev: Address of the platform_device structure
932 *
933 * The function starts the QSPI driver queue and initializes the QSPI
934 * controller
935 *
936 * Return: 0 on success; error value otherwise
937 */
zynqmp_qspi_resume(struct device * dev)938 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
939 {
940 struct platform_device *pdev = container_of(dev,
941 struct platform_device,
942 dev);
943 struct spi_master *master = platform_get_drvdata(pdev);
944 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
945 int ret = 0;
946
947 ret = clk_enable(xqspi->pclk);
948 if (ret) {
949 dev_err(dev, "Cannot enable APB clock.\n");
950 return ret;
951 }
952
953 ret = clk_enable(xqspi->refclk);
954 if (ret) {
955 dev_err(dev, "Cannot enable device clock.\n");
956 clk_disable(xqspi->pclk);
957 return ret;
958 }
959
960 spi_master_resume(master);
961
962 return 0;
963 }
964
965 static SIMPLE_DEV_PM_OPS(zynqmp_qspi_dev_pm_ops, zynqmp_qspi_suspend,
966 zynqmp_qspi_resume);
967
968 /**
969 * zynqmp_qspi_probe: Probe method for the QSPI driver
970 * @pdev: Pointer to the platform_device structure
971 *
972 * This function initializes the driver data structures and the hardware.
973 *
974 * Return: 0 on success; error value otherwise
975 */
zynqmp_qspi_probe(struct platform_device * pdev)976 static int zynqmp_qspi_probe(struct platform_device *pdev)
977 {
978 int ret = 0;
979 struct spi_master *master;
980 struct zynqmp_qspi *xqspi;
981 struct resource *res;
982 struct device *dev = &pdev->dev;
983
984 master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
985 if (!master)
986 return -ENOMEM;
987
988 xqspi = spi_master_get_devdata(master);
989 master->dev.of_node = pdev->dev.of_node;
990 platform_set_drvdata(pdev, master);
991
992 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
993 xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
994 if (IS_ERR(xqspi->regs)) {
995 ret = PTR_ERR(xqspi->regs);
996 goto remove_master;
997 }
998
999 xqspi->dev = dev;
1000 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1001 if (IS_ERR(xqspi->pclk)) {
1002 dev_err(dev, "pclk clock not found.\n");
1003 ret = PTR_ERR(xqspi->pclk);
1004 goto remove_master;
1005 }
1006
1007 ret = clk_prepare_enable(xqspi->pclk);
1008 if (ret) {
1009 dev_err(dev, "Unable to enable APB clock.\n");
1010 goto remove_master;
1011 }
1012
1013 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1014 if (IS_ERR(xqspi->refclk)) {
1015 dev_err(dev, "ref_clk clock not found.\n");
1016 ret = PTR_ERR(xqspi->refclk);
1017 goto clk_dis_pclk;
1018 }
1019
1020 ret = clk_prepare_enable(xqspi->refclk);
1021 if (ret) {
1022 dev_err(dev, "Unable to enable device clock.\n");
1023 goto clk_dis_pclk;
1024 }
1025
1026 /* QSPI controller initializations */
1027 zynqmp_qspi_init_hw(xqspi);
1028
1029 xqspi->irq = platform_get_irq(pdev, 0);
1030 if (xqspi->irq <= 0) {
1031 ret = -ENXIO;
1032 dev_err(dev, "irq resource not found\n");
1033 goto clk_dis_all;
1034 }
1035 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1036 0, pdev->name, master);
1037 if (ret != 0) {
1038 ret = -ENXIO;
1039 dev_err(dev, "request_irq failed\n");
1040 goto clk_dis_all;
1041 }
1042
1043 master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1044
1045 master->setup = zynqmp_qspi_setup;
1046 master->set_cs = zynqmp_qspi_chipselect;
1047 master->transfer_one = zynqmp_qspi_start_transfer;
1048 master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
1049 master->unprepare_transfer_hardware =
1050 zynqmp_unprepare_transfer_hardware;
1051 master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1052 master->bits_per_word_mask = SPI_BPW_MASK(8);
1053 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1054 SPI_TX_DUAL | SPI_TX_QUAD;
1055
1056 if (master->dev.parent == NULL)
1057 master->dev.parent = &master->dev;
1058
1059 ret = spi_register_master(master);
1060 if (ret)
1061 goto clk_dis_all;
1062
1063 return 0;
1064
1065 clk_dis_all:
1066 clk_disable_unprepare(xqspi->refclk);
1067 clk_dis_pclk:
1068 clk_disable_unprepare(xqspi->pclk);
1069 remove_master:
1070 spi_master_put(master);
1071
1072 return ret;
1073 }
1074
1075 /**
1076 * zynqmp_qspi_remove: Remove method for the QSPI driver
1077 * @pdev: Pointer to the platform_device structure
1078 *
1079 * This function is called if a device is physically removed from the system or
1080 * if the driver module is being unloaded. It frees all resources allocated to
1081 * the device.
1082 *
1083 * Return: 0 Always
1084 */
zynqmp_qspi_remove(struct platform_device * pdev)1085 static int zynqmp_qspi_remove(struct platform_device *pdev)
1086 {
1087 struct spi_master *master = platform_get_drvdata(pdev);
1088 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1089
1090 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1091 clk_disable_unprepare(xqspi->refclk);
1092 clk_disable_unprepare(xqspi->pclk);
1093
1094 spi_unregister_master(master);
1095
1096 return 0;
1097 }
1098
1099 static const struct of_device_id zynqmp_qspi_of_match[] = {
1100 { .compatible = "xlnx,zynqmp-qspi-1.0", },
1101 { /* End of table */ }
1102 };
1103
1104 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1105
1106 static struct platform_driver zynqmp_qspi_driver = {
1107 .probe = zynqmp_qspi_probe,
1108 .remove = zynqmp_qspi_remove,
1109 .driver = {
1110 .name = "zynqmp-qspi",
1111 .of_match_table = zynqmp_qspi_of_match,
1112 .pm = &zynqmp_qspi_dev_pm_ops,
1113 },
1114 };
1115
1116 module_platform_driver(zynqmp_qspi_driver);
1117
1118 MODULE_AUTHOR("Xilinx, Inc.");
1119 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1120 MODULE_LICENSE("GPL");
1121