1 /*
2 * AD7190 AD7192 AD7195 SPI ADC driver
3 *
4 * Copyright 2011-2012 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26 #include <linux/iio/adc/ad_sigma_delta.h>
27
28 #include "ad7192.h"
29
30 /* Registers */
31 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
32 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
33 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
34 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
35 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
36 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
37 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
38 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit
39 * (AD7792)/24-bit (AD7192)) */
40 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register
41 * (RW, 16-bit (AD7792)/24-bit (AD7192)) */
42
43 /* Communications Register Bit Designations (AD7192_REG_COMM) */
44 #define AD7192_COMM_WEN BIT(7) /* Write Enable */
45 #define AD7192_COMM_WRITE 0 /* Write Operation */
46 #define AD7192_COMM_READ BIT(6) /* Read Operation */
47 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
48 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
49
50 /* Status Register Bit Designations (AD7192_REG_STAT) */
51 #define AD7192_STAT_RDY BIT(7) /* Ready */
52 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
53 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
54 #define AD7192_STAT_PARITY BIT(4) /* Parity */
55 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
56 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
57 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
58
59 /* Mode Register Bit Designations (AD7192_REG_MODE) */
60 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
61 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
62 #define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */
63 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
64 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
65 #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
66 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
67 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
68 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
69 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
70 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
71
72 /* Mode Register: AD7192_MODE_SEL options */
73 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
74 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
75 #define AD7192_MODE_IDLE 2 /* Idle Mode */
76 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
77 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
78 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
79 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
80 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
81
82 /* Mode Register: AD7192_MODE_CLKSRC options */
83 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected
84 * from MCLK1 to MCLK2 */
85 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
86 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not
87 * available at the MCLK2 pin */
88 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available
89 * at the MCLK2 pin */
90
91 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
92
93 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
94 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
95 #define AD7192_CONF_CHAN(x) (((1 << (x)) & 0xFF) << 8) /* Channel select */
96 #define AD7192_CONF_CHAN_MASK (0xFF << 8) /* Channel select mask */
97 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
98 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
99 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
100 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
101 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
102
103 #define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */
104 #define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */
105 #define AD7192_CH_TEMP 2 /* Temp Sensor */
106 #define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */
107 #define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */
108 #define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */
109 #define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */
110 #define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */
111
112 /* ID Register Bit Designations (AD7192_REG_ID) */
113 #define ID_AD7190 0x4
114 #define ID_AD7192 0x0
115 #define ID_AD7195 0x6
116 #define AD7192_ID_MASK 0x0F
117
118 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
119 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
120 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
121 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
122 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
123 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
124 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
125 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
126
127 #define AD7192_EXT_FREQ_MHZ_MIN 2457600
128 #define AD7192_EXT_FREQ_MHZ_MAX 5120000
129 #define AD7192_INT_FREQ_MHZ 4915200
130
131 /* NOTE:
132 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
133 * In order to avoid contentions on the SPI bus, it's therefore necessary
134 * to use spi bus locking.
135 *
136 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
137 */
138
139 struct ad7192_state {
140 struct regulator *reg;
141 u16 int_vref_mv;
142 u32 mclk;
143 u32 f_order;
144 u32 mode;
145 u32 conf;
146 u32 scale_avail[8][2];
147 u8 gpocon;
148 u8 devid;
149
150 struct ad_sigma_delta sd;
151 };
152
ad_sigma_delta_to_ad7192(struct ad_sigma_delta * sd)153 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
154 {
155 return container_of(sd, struct ad7192_state, sd);
156 }
157
ad7192_set_channel(struct ad_sigma_delta * sd,unsigned int channel)158 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
159 {
160 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
161
162 st->conf &= ~AD7192_CONF_CHAN_MASK;
163 st->conf |= AD7192_CONF_CHAN(channel);
164
165 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
166 }
167
ad7192_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)168 static int ad7192_set_mode(struct ad_sigma_delta *sd,
169 enum ad_sigma_delta_mode mode)
170 {
171 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
172
173 st->mode &= ~AD7192_MODE_SEL_MASK;
174 st->mode |= AD7192_MODE_SEL(mode);
175
176 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
177 }
178
179 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
180 .set_channel = ad7192_set_channel,
181 .set_mode = ad7192_set_mode,
182 .has_registers = true,
183 .addr_shift = 3,
184 .read_mask = BIT(6),
185 };
186
187 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
188 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
189 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
190 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
191 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
192 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
193 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
194 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
195 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
196 };
197
ad7192_calibrate_all(struct ad7192_state * st)198 static int ad7192_calibrate_all(struct ad7192_state *st)
199 {
200 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
201 ARRAY_SIZE(ad7192_calib_arr));
202 }
203
ad7192_valid_external_frequency(u32 freq)204 static inline bool ad7192_valid_external_frequency(u32 freq)
205 {
206 return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
207 freq <= AD7192_EXT_FREQ_MHZ_MAX);
208 }
209
ad7192_setup(struct ad7192_state * st,const struct ad7192_platform_data * pdata)210 static int ad7192_setup(struct ad7192_state *st,
211 const struct ad7192_platform_data *pdata)
212 {
213 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
214 unsigned long long scale_uv;
215 int i, ret, id;
216
217 /* reset the serial interface */
218 ret = ad_sd_reset(&st->sd, 48);
219 if (ret < 0)
220 goto out;
221 usleep_range(500, 1000); /* Wait for at least 500us */
222
223 /* write/read test for device presence */
224 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
225 if (ret)
226 goto out;
227
228 id &= AD7192_ID_MASK;
229
230 if (id != st->devid)
231 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
232 id);
233
234 switch (pdata->clock_source_sel) {
235 case AD7192_CLK_INT:
236 case AD7192_CLK_INT_CO:
237 st->mclk = AD7192_INT_FREQ_MHZ;
238 break;
239 case AD7192_CLK_EXT_MCLK1_2:
240 case AD7192_CLK_EXT_MCLK2:
241 if (ad7192_valid_external_frequency(pdata->ext_clk_hz)) {
242 st->mclk = pdata->ext_clk_hz;
243 break;
244 }
245 dev_err(&st->sd.spi->dev, "Invalid frequency setting %u\n",
246 pdata->ext_clk_hz);
247 ret = -EINVAL;
248 goto out;
249 default:
250 ret = -EINVAL;
251 goto out;
252 }
253
254 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
255 AD7192_MODE_CLKSRC(pdata->clock_source_sel) |
256 AD7192_MODE_RATE(480);
257
258 st->conf = AD7192_CONF_GAIN(0);
259
260 if (pdata->rej60_en)
261 st->mode |= AD7192_MODE_REJ60;
262
263 if (pdata->sinc3_en)
264 st->mode |= AD7192_MODE_SINC3;
265
266 if (pdata->refin2_en && (st->devid != ID_AD7195))
267 st->conf |= AD7192_CONF_REFSEL;
268
269 if (pdata->chop_en) {
270 st->conf |= AD7192_CONF_CHOP;
271 if (pdata->sinc3_en)
272 st->f_order = 3; /* SINC 3rd order */
273 else
274 st->f_order = 4; /* SINC 4th order */
275 } else {
276 st->f_order = 1;
277 }
278
279 if (pdata->buf_en)
280 st->conf |= AD7192_CONF_BUF;
281
282 if (pdata->unipolar_en)
283 st->conf |= AD7192_CONF_UNIPOLAR;
284
285 if (pdata->burnout_curr_en)
286 st->conf |= AD7192_CONF_BURN;
287
288 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
289 if (ret)
290 goto out;
291
292 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
293 if (ret)
294 goto out;
295
296 ret = ad7192_calibrate_all(st);
297 if (ret)
298 goto out;
299
300 /* Populate available ADC input ranges */
301 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
302 scale_uv = ((u64)st->int_vref_mv * 100000000)
303 >> (indio_dev->channels[0].scan_type.realbits -
304 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
305 scale_uv >>= i;
306
307 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
308 st->scale_avail[i][0] = scale_uv;
309 }
310
311 return 0;
312 out:
313 dev_err(&st->sd.spi->dev, "setup failed\n");
314 return ret;
315 }
316
ad7192_read_frequency(struct device * dev,struct device_attribute * attr,char * buf)317 static ssize_t ad7192_read_frequency(struct device *dev,
318 struct device_attribute *attr,
319 char *buf)
320 {
321 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
322 struct ad7192_state *st = iio_priv(indio_dev);
323
324 return sprintf(buf, "%d\n", st->mclk /
325 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)));
326 }
327
ad7192_write_frequency(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)328 static ssize_t ad7192_write_frequency(struct device *dev,
329 struct device_attribute *attr,
330 const char *buf,
331 size_t len)
332 {
333 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
334 struct ad7192_state *st = iio_priv(indio_dev);
335 unsigned long lval;
336 int div, ret;
337
338 ret = kstrtoul(buf, 10, &lval);
339 if (ret)
340 return ret;
341 if (lval == 0)
342 return -EINVAL;
343
344 mutex_lock(&indio_dev->mlock);
345 if (iio_buffer_enabled(indio_dev)) {
346 mutex_unlock(&indio_dev->mlock);
347 return -EBUSY;
348 }
349
350 div = st->mclk / (lval * st->f_order * 1024);
351 if (div < 1 || div > 1023) {
352 ret = -EINVAL;
353 goto out;
354 }
355
356 st->mode &= ~AD7192_MODE_RATE(-1);
357 st->mode |= AD7192_MODE_RATE(div);
358 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
359
360 out:
361 mutex_unlock(&indio_dev->mlock);
362
363 return ret ? ret : len;
364 }
365
366 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
367 ad7192_read_frequency,
368 ad7192_write_frequency);
369
370 static ssize_t
ad7192_show_scale_available(struct device * dev,struct device_attribute * attr,char * buf)371 ad7192_show_scale_available(struct device *dev,
372 struct device_attribute *attr, char *buf)
373 {
374 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
375 struct ad7192_state *st = iio_priv(indio_dev);
376 int i, len = 0;
377
378 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
379 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
380 st->scale_avail[i][1]);
381
382 len += sprintf(buf + len, "\n");
383
384 return len;
385 }
386
387 static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available,
388 in_voltage-voltage_scale_available,
389 S_IRUGO, ad7192_show_scale_available, NULL, 0);
390
391 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
392 ad7192_show_scale_available, NULL, 0);
393
ad7192_show_ac_excitation(struct device * dev,struct device_attribute * attr,char * buf)394 static ssize_t ad7192_show_ac_excitation(struct device *dev,
395 struct device_attribute *attr,
396 char *buf)
397 {
398 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
399 struct ad7192_state *st = iio_priv(indio_dev);
400
401 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
402 }
403
ad7192_show_bridge_switch(struct device * dev,struct device_attribute * attr,char * buf)404 static ssize_t ad7192_show_bridge_switch(struct device *dev,
405 struct device_attribute *attr,
406 char *buf)
407 {
408 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
409 struct ad7192_state *st = iio_priv(indio_dev);
410
411 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
412 }
413
ad7192_set(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)414 static ssize_t ad7192_set(struct device *dev,
415 struct device_attribute *attr,
416 const char *buf,
417 size_t len)
418 {
419 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
420 struct ad7192_state *st = iio_priv(indio_dev);
421 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
422 int ret;
423 bool val;
424
425 ret = strtobool(buf, &val);
426 if (ret < 0)
427 return ret;
428
429 mutex_lock(&indio_dev->mlock);
430 if (iio_buffer_enabled(indio_dev)) {
431 mutex_unlock(&indio_dev->mlock);
432 return -EBUSY;
433 }
434
435 switch ((u32)this_attr->address) {
436 case AD7192_REG_GPOCON:
437 if (val)
438 st->gpocon |= AD7192_GPOCON_BPDSW;
439 else
440 st->gpocon &= ~AD7192_GPOCON_BPDSW;
441
442 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
443 break;
444 case AD7192_REG_MODE:
445 if (val)
446 st->mode |= AD7192_MODE_ACX;
447 else
448 st->mode &= ~AD7192_MODE_ACX;
449
450 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
451 break;
452 default:
453 ret = -EINVAL;
454 }
455
456 mutex_unlock(&indio_dev->mlock);
457
458 return ret ? ret : len;
459 }
460
461 static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR,
462 ad7192_show_bridge_switch, ad7192_set,
463 AD7192_REG_GPOCON);
464
465 static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR,
466 ad7192_show_ac_excitation, ad7192_set,
467 AD7192_REG_MODE);
468
469 static struct attribute *ad7192_attributes[] = {
470 &iio_dev_attr_sampling_frequency.dev_attr.attr,
471 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
472 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
473 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
474 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
475 NULL
476 };
477
478 static const struct attribute_group ad7192_attribute_group = {
479 .attrs = ad7192_attributes,
480 };
481
482 static struct attribute *ad7195_attributes[] = {
483 &iio_dev_attr_sampling_frequency.dev_attr.attr,
484 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
485 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
486 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
487 NULL
488 };
489
490 static const struct attribute_group ad7195_attribute_group = {
491 .attrs = ad7195_attributes,
492 };
493
ad7192_get_temp_scale(bool unipolar)494 static unsigned int ad7192_get_temp_scale(bool unipolar)
495 {
496 return unipolar ? 2815 * 2 : 2815;
497 }
498
ad7192_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)499 static int ad7192_read_raw(struct iio_dev *indio_dev,
500 struct iio_chan_spec const *chan,
501 int *val,
502 int *val2,
503 long m)
504 {
505 struct ad7192_state *st = iio_priv(indio_dev);
506 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
507
508 switch (m) {
509 case IIO_CHAN_INFO_RAW:
510 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
511 case IIO_CHAN_INFO_SCALE:
512 switch (chan->type) {
513 case IIO_VOLTAGE:
514 mutex_lock(&indio_dev->mlock);
515 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
516 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
517 mutex_unlock(&indio_dev->mlock);
518 return IIO_VAL_INT_PLUS_NANO;
519 case IIO_TEMP:
520 *val = 0;
521 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
522 return IIO_VAL_INT_PLUS_NANO;
523 default:
524 return -EINVAL;
525 }
526 case IIO_CHAN_INFO_OFFSET:
527 if (!unipolar)
528 *val = -(1 << (chan->scan_type.realbits - 1));
529 else
530 *val = 0;
531 /* Kelvin to Celsius */
532 if (chan->type == IIO_TEMP)
533 *val -= 273 * ad7192_get_temp_scale(unipolar);
534 return IIO_VAL_INT;
535 }
536
537 return -EINVAL;
538 }
539
ad7192_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)540 static int ad7192_write_raw(struct iio_dev *indio_dev,
541 struct iio_chan_spec const *chan,
542 int val,
543 int val2,
544 long mask)
545 {
546 struct ad7192_state *st = iio_priv(indio_dev);
547 int ret, i;
548 unsigned int tmp;
549
550 mutex_lock(&indio_dev->mlock);
551 if (iio_buffer_enabled(indio_dev)) {
552 mutex_unlock(&indio_dev->mlock);
553 return -EBUSY;
554 }
555
556 switch (mask) {
557 case IIO_CHAN_INFO_SCALE:
558 ret = -EINVAL;
559 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
560 if (val2 == st->scale_avail[i][1]) {
561 ret = 0;
562 tmp = st->conf;
563 st->conf &= ~AD7192_CONF_GAIN(-1);
564 st->conf |= AD7192_CONF_GAIN(i);
565 if (tmp == st->conf)
566 break;
567 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
568 3, st->conf);
569 ad7192_calibrate_all(st);
570 break;
571 }
572 break;
573 default:
574 ret = -EINVAL;
575 }
576
577 mutex_unlock(&indio_dev->mlock);
578
579 return ret;
580 }
581
ad7192_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)582 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
583 struct iio_chan_spec const *chan,
584 long mask)
585 {
586 return IIO_VAL_INT_PLUS_NANO;
587 }
588
589 static const struct iio_info ad7192_info = {
590 .read_raw = &ad7192_read_raw,
591 .write_raw = &ad7192_write_raw,
592 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
593 .attrs = &ad7192_attribute_group,
594 .validate_trigger = ad_sd_validate_trigger,
595 .driver_module = THIS_MODULE,
596 };
597
598 static const struct iio_info ad7195_info = {
599 .read_raw = &ad7192_read_raw,
600 .write_raw = &ad7192_write_raw,
601 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
602 .attrs = &ad7195_attribute_group,
603 .validate_trigger = ad_sd_validate_trigger,
604 .driver_module = THIS_MODULE,
605 };
606
607 static const struct iio_chan_spec ad7192_channels[] = {
608 AD_SD_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M, 24, 32, 0),
609 AD_SD_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M, 24, 32, 0),
610 AD_SD_TEMP_CHANNEL(2, AD7192_CH_TEMP, 24, 32, 0),
611 AD_SD_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M, 24, 32, 0),
612 AD_SD_CHANNEL(4, 1, AD7192_CH_AIN1, 24, 32, 0),
613 AD_SD_CHANNEL(5, 2, AD7192_CH_AIN2, 24, 32, 0),
614 AD_SD_CHANNEL(6, 3, AD7192_CH_AIN3, 24, 32, 0),
615 AD_SD_CHANNEL(7, 4, AD7192_CH_AIN4, 24, 32, 0),
616 IIO_CHAN_SOFT_TIMESTAMP(8),
617 };
618
ad7192_probe(struct spi_device * spi)619 static int ad7192_probe(struct spi_device *spi)
620 {
621 const struct ad7192_platform_data *pdata = spi->dev.platform_data;
622 struct ad7192_state *st;
623 struct iio_dev *indio_dev;
624 int ret, voltage_uv = 0;
625
626 if (!pdata) {
627 dev_err(&spi->dev, "no platform data?\n");
628 return -ENODEV;
629 }
630
631 if (!spi->irq) {
632 dev_err(&spi->dev, "no IRQ?\n");
633 return -ENODEV;
634 }
635
636 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
637 if (!indio_dev)
638 return -ENOMEM;
639
640 st = iio_priv(indio_dev);
641
642 st->reg = devm_regulator_get(&spi->dev, "vcc");
643 if (!IS_ERR(st->reg)) {
644 ret = regulator_enable(st->reg);
645 if (ret)
646 return ret;
647
648 voltage_uv = regulator_get_voltage(st->reg);
649 }
650
651 if (pdata->vref_mv)
652 st->int_vref_mv = pdata->vref_mv;
653 else if (voltage_uv)
654 st->int_vref_mv = voltage_uv / 1000;
655 else
656 dev_warn(&spi->dev, "reference voltage undefined\n");
657
658 spi_set_drvdata(spi, indio_dev);
659 st->devid = spi_get_device_id(spi)->driver_data;
660 indio_dev->dev.parent = &spi->dev;
661 indio_dev->name = spi_get_device_id(spi)->name;
662 indio_dev->modes = INDIO_DIRECT_MODE;
663 indio_dev->channels = ad7192_channels;
664 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
665 if (st->devid == ID_AD7195)
666 indio_dev->info = &ad7195_info;
667 else
668 indio_dev->info = &ad7192_info;
669
670 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
671
672 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
673 if (ret)
674 goto error_disable_reg;
675
676 ret = ad7192_setup(st, pdata);
677 if (ret)
678 goto error_remove_trigger;
679
680 ret = iio_device_register(indio_dev);
681 if (ret < 0)
682 goto error_remove_trigger;
683 return 0;
684
685 error_remove_trigger:
686 ad_sd_cleanup_buffer_and_trigger(indio_dev);
687 error_disable_reg:
688 if (!IS_ERR(st->reg))
689 regulator_disable(st->reg);
690
691 return ret;
692 }
693
ad7192_remove(struct spi_device * spi)694 static int ad7192_remove(struct spi_device *spi)
695 {
696 struct iio_dev *indio_dev = spi_get_drvdata(spi);
697 struct ad7192_state *st = iio_priv(indio_dev);
698
699 iio_device_unregister(indio_dev);
700 ad_sd_cleanup_buffer_and_trigger(indio_dev);
701
702 if (!IS_ERR(st->reg))
703 regulator_disable(st->reg);
704
705 return 0;
706 }
707
708 static const struct spi_device_id ad7192_id[] = {
709 {"ad7190", ID_AD7190},
710 {"ad7192", ID_AD7192},
711 {"ad7195", ID_AD7195},
712 {}
713 };
714 MODULE_DEVICE_TABLE(spi, ad7192_id);
715
716 static struct spi_driver ad7192_driver = {
717 .driver = {
718 .name = "ad7192",
719 },
720 .probe = ad7192_probe,
721 .remove = ad7192_remove,
722 .id_table = ad7192_id,
723 };
724 module_spi_driver(ad7192_driver);
725
726 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
727 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7195 ADC");
728 MODULE_LICENSE("GPL v2");
729