1 /*
2 * AD7280A Lithium Ion Battery Monitoring System
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9 #include <linux/device.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sysfs.h>
13 #include <linux/spi/spi.h>
14 #include <linux/err.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18
19 #include <linux/iio/iio.h>
20 #include <linux/iio/sysfs.h>
21 #include <linux/iio/events.h>
22
23 #include "ad7280a.h"
24
25 /* Registers */
26 #define AD7280A_CELL_VOLTAGE_1 0x0 /* D11 to D0, Read only */
27 #define AD7280A_CELL_VOLTAGE_2 0x1 /* D11 to D0, Read only */
28 #define AD7280A_CELL_VOLTAGE_3 0x2 /* D11 to D0, Read only */
29 #define AD7280A_CELL_VOLTAGE_4 0x3 /* D11 to D0, Read only */
30 #define AD7280A_CELL_VOLTAGE_5 0x4 /* D11 to D0, Read only */
31 #define AD7280A_CELL_VOLTAGE_6 0x5 /* D11 to D0, Read only */
32 #define AD7280A_AUX_ADC_1 0x6 /* D11 to D0, Read only */
33 #define AD7280A_AUX_ADC_2 0x7 /* D11 to D0, Read only */
34 #define AD7280A_AUX_ADC_3 0x8 /* D11 to D0, Read only */
35 #define AD7280A_AUX_ADC_4 0x9 /* D11 to D0, Read only */
36 #define AD7280A_AUX_ADC_5 0xA /* D11 to D0, Read only */
37 #define AD7280A_AUX_ADC_6 0xB /* D11 to D0, Read only */
38 #define AD7280A_SELF_TEST 0xC /* D11 to D0, Read only */
39 #define AD7280A_CONTROL_HB 0xD /* D15 to D8, Read/write */
40 #define AD7280A_CONTROL_LB 0xE /* D7 to D0, Read/write */
41 #define AD7280A_CELL_OVERVOLTAGE 0xF /* D7 to D0, Read/write */
42 #define AD7280A_CELL_UNDERVOLTAGE 0x10 /* D7 to D0, Read/write */
43 #define AD7280A_AUX_ADC_OVERVOLTAGE 0x11 /* D7 to D0, Read/write */
44 #define AD7280A_AUX_ADC_UNDERVOLTAGE 0x12 /* D7 to D0, Read/write */
45 #define AD7280A_ALERT 0x13 /* D7 to D0, Read/write */
46 #define AD7280A_CELL_BALANCE 0x14 /* D7 to D0, Read/write */
47 #define AD7280A_CB1_TIMER 0x15 /* D7 to D0, Read/write */
48 #define AD7280A_CB2_TIMER 0x16 /* D7 to D0, Read/write */
49 #define AD7280A_CB3_TIMER 0x17 /* D7 to D0, Read/write */
50 #define AD7280A_CB4_TIMER 0x18 /* D7 to D0, Read/write */
51 #define AD7280A_CB5_TIMER 0x19 /* D7 to D0, Read/write */
52 #define AD7280A_CB6_TIMER 0x1A /* D7 to D0, Read/write */
53 #define AD7280A_PD_TIMER 0x1B /* D7 to D0, Read/write */
54 #define AD7280A_READ 0x1C /* D7 to D0, Read/write */
55 #define AD7280A_CNVST_CONTROL 0x1D /* D7 to D0, Read/write */
56
57 /* Bits and Masks */
58 #define AD7280A_CTRL_HB_CONV_INPUT_ALL 0
59 #define AD7280A_CTRL_HB_CONV_INPUT_6CELL_AUX1_3_4 BIT(6)
60 #define AD7280A_CTRL_HB_CONV_INPUT_6CELL BIT(7)
61 #define AD7280A_CTRL_HB_CONV_INPUT_SELF_TEST (BIT(7) | BIT(6))
62 #define AD7280A_CTRL_HB_CONV_RES_READ_ALL 0
63 #define AD7280A_CTRL_HB_CONV_RES_READ_6CELL_AUX1_3_4 BIT(4)
64 #define AD7280A_CTRL_HB_CONV_RES_READ_6CELL BIT(5)
65 #define AD7280A_CTRL_HB_CONV_RES_READ_NO (BIT(5) | BIT(4))
66 #define AD7280A_CTRL_HB_CONV_START_CNVST 0
67 #define AD7280A_CTRL_HB_CONV_START_CS BIT(3)
68 #define AD7280A_CTRL_HB_CONV_AVG_DIS 0
69 #define AD7280A_CTRL_HB_CONV_AVG_2 BIT(1)
70 #define AD7280A_CTRL_HB_CONV_AVG_4 BIT(2)
71 #define AD7280A_CTRL_HB_CONV_AVG_8 (BIT(2) | BIT(1))
72 #define AD7280A_CTRL_HB_CONV_AVG(x) ((x) << 1)
73 #define AD7280A_CTRL_HB_PWRDN_SW BIT(0)
74
75 #define AD7280A_CTRL_LB_SWRST BIT(7)
76 #define AD7280A_CTRL_LB_ACQ_TIME_400ns 0
77 #define AD7280A_CTRL_LB_ACQ_TIME_800ns BIT(5)
78 #define AD7280A_CTRL_LB_ACQ_TIME_1200ns BIT(6)
79 #define AD7280A_CTRL_LB_ACQ_TIME_1600ns (BIT(6) | BIT(5))
80 #define AD7280A_CTRL_LB_ACQ_TIME(x) ((x) << 5)
81 #define AD7280A_CTRL_LB_MUST_SET BIT(4)
82 #define AD7280A_CTRL_LB_THERMISTOR_EN BIT(3)
83 #define AD7280A_CTRL_LB_LOCK_DEV_ADDR BIT(2)
84 #define AD7280A_CTRL_LB_INC_DEV_ADDR BIT(1)
85 #define AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN BIT(0)
86
87 #define AD7280A_ALERT_GEN_STATIC_HIGH BIT(6)
88 #define AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN (BIT(7) | BIT(6))
89
90 #define AD7280A_ALL_CELLS (0xAD << 16)
91
92 #define AD7280A_MAX_SPI_CLK_HZ 700000 /* < 1MHz */
93 #define AD7280A_MAX_CHAIN 8
94 #define AD7280A_CELLS_PER_DEV 6
95 #define AD7280A_BITS 12
96 #define AD7280A_NUM_CH (AD7280A_AUX_ADC_6 - \
97 AD7280A_CELL_VOLTAGE_1 + 1)
98
99 #define AD7280A_DEVADDR_MASTER 0
100 #define AD7280A_DEVADDR_ALL 0x1F
101 /* 5-bit device address is sent LSB first */
102 #define AD7280A_DEVADDR(addr) (((addr & 0x1) << 4) | ((addr & 0x2) << 3) | \
103 (addr & 0x4) | ((addr & 0x8) >> 3) | \
104 ((addr & 0x10) >> 4))
105
106 /* During a read a valid write is mandatory.
107 * So writing to the highest available address (Address 0x1F)
108 * and setting the address all parts bit to 0 is recommended
109 * So the TXVAL is AD7280A_DEVADDR_ALL + CRC
110 */
111 #define AD7280A_READ_TXVAL 0xF800030A
112
113 /*
114 * AD7280 CRC
115 *
116 * P(x) = x^8 + x^5 + x^3 + x^2 + x^1 + x^0 = 0b100101111 => 0x2F
117 */
118 #define POLYNOM 0x2F
119 #define POLYNOM_ORDER 8
120 #define HIGHBIT (1 << (POLYNOM_ORDER - 1))
121
122 struct ad7280_state {
123 struct spi_device *spi;
124 struct iio_chan_spec *channels;
125 struct iio_dev_attr *iio_attr;
126 int slave_num;
127 int scan_cnt;
128 int readback_delay_us;
129 unsigned char crc_tab[256];
130 unsigned char ctrl_hb;
131 unsigned char ctrl_lb;
132 unsigned char cell_threshhigh;
133 unsigned char cell_threshlow;
134 unsigned char aux_threshhigh;
135 unsigned char aux_threshlow;
136 unsigned char cb_mask[AD7280A_MAX_CHAIN];
137
138 __be32 buf[2] ____cacheline_aligned;
139 };
140
ad7280_crc8_build_table(unsigned char * crc_tab)141 static void ad7280_crc8_build_table(unsigned char *crc_tab)
142 {
143 unsigned char bit, crc;
144 int cnt, i;
145
146 for (cnt = 0; cnt < 256; cnt++) {
147 crc = cnt;
148 for (i = 0; i < 8; i++) {
149 bit = crc & HIGHBIT;
150 crc <<= 1;
151 if (bit)
152 crc ^= POLYNOM;
153 }
154 crc_tab[cnt] = crc;
155 }
156 }
157
ad7280_calc_crc8(unsigned char * crc_tab,unsigned val)158 static unsigned char ad7280_calc_crc8(unsigned char *crc_tab, unsigned val)
159 {
160 unsigned char crc;
161
162 crc = crc_tab[val >> 16 & 0xFF];
163 crc = crc_tab[crc ^ (val >> 8 & 0xFF)];
164
165 return crc ^ (val & 0xFF);
166 }
167
ad7280_check_crc(struct ad7280_state * st,unsigned val)168 static int ad7280_check_crc(struct ad7280_state *st, unsigned val)
169 {
170 unsigned char crc = ad7280_calc_crc8(st->crc_tab, val >> 10);
171
172 if (crc != ((val >> 2) & 0xFF))
173 return -EIO;
174
175 return 0;
176 }
177
178 /* After initiating a conversion sequence we need to wait until the
179 * conversion is done. The delay is typically in the range of 15..30 us
180 * however depending an the number of devices in the daisy chain and the
181 * number of averages taken, conversion delays and acquisition time options
182 * it may take up to 250us, in this case we better sleep instead of busy
183 * wait.
184 */
185
ad7280_delay(struct ad7280_state * st)186 static void ad7280_delay(struct ad7280_state *st)
187 {
188 if (st->readback_delay_us < 50)
189 udelay(st->readback_delay_us);
190 else
191 usleep_range(250, 500);
192 }
193
__ad7280_read32(struct ad7280_state * st,unsigned * val)194 static int __ad7280_read32(struct ad7280_state *st, unsigned *val)
195 {
196 int ret;
197 struct spi_transfer t = {
198 .tx_buf = &st->buf[0],
199 .rx_buf = &st->buf[1],
200 .len = 4,
201 };
202
203 st->buf[0] = cpu_to_be32(AD7280A_READ_TXVAL);
204
205 ret = spi_sync_transfer(st->spi, &t, 1);
206 if (ret)
207 return ret;
208
209 *val = be32_to_cpu(st->buf[1]);
210
211 return 0;
212 }
213
ad7280_write(struct ad7280_state * st,unsigned devaddr,unsigned addr,bool all,unsigned val)214 static int ad7280_write(struct ad7280_state *st, unsigned devaddr,
215 unsigned addr, bool all, unsigned val)
216 {
217 unsigned reg = (devaddr << 27 | addr << 21 |
218 (val & 0xFF) << 13 | all << 12);
219
220 reg |= ad7280_calc_crc8(st->crc_tab, reg >> 11) << 3 | 0x2;
221 st->buf[0] = cpu_to_be32(reg);
222
223 return spi_write(st->spi, &st->buf[0], 4);
224 }
225
ad7280_read(struct ad7280_state * st,unsigned devaddr,unsigned addr)226 static int ad7280_read(struct ad7280_state *st, unsigned devaddr,
227 unsigned addr)
228 {
229 int ret;
230 unsigned tmp;
231
232 /* turns off the read operation on all parts */
233 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1,
234 AD7280A_CTRL_HB_CONV_INPUT_ALL |
235 AD7280A_CTRL_HB_CONV_RES_READ_NO |
236 st->ctrl_hb);
237 if (ret)
238 return ret;
239
240 /* turns on the read operation on the addressed part */
241 ret = ad7280_write(st, devaddr, AD7280A_CONTROL_HB, 0,
242 AD7280A_CTRL_HB_CONV_INPUT_ALL |
243 AD7280A_CTRL_HB_CONV_RES_READ_ALL |
244 st->ctrl_hb);
245 if (ret)
246 return ret;
247
248 /* Set register address on the part to be read from */
249 ret = ad7280_write(st, devaddr, AD7280A_READ, 0, addr << 2);
250 if (ret)
251 return ret;
252
253 ret = __ad7280_read32(st, &tmp);
254 if (ret)
255 return ret;
256
257 if (ad7280_check_crc(st, tmp))
258 return -EIO;
259
260 if (((tmp >> 27) != devaddr) || (((tmp >> 21) & 0x3F) != addr))
261 return -EFAULT;
262
263 return (tmp >> 13) & 0xFF;
264 }
265
ad7280_read_channel(struct ad7280_state * st,unsigned devaddr,unsigned addr)266 static int ad7280_read_channel(struct ad7280_state *st, unsigned devaddr,
267 unsigned addr)
268 {
269 int ret;
270 unsigned tmp;
271
272 ret = ad7280_write(st, devaddr, AD7280A_READ, 0, addr << 2);
273 if (ret)
274 return ret;
275
276 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1,
277 AD7280A_CTRL_HB_CONV_INPUT_ALL |
278 AD7280A_CTRL_HB_CONV_RES_READ_NO |
279 st->ctrl_hb);
280 if (ret)
281 return ret;
282
283 ret = ad7280_write(st, devaddr, AD7280A_CONTROL_HB, 0,
284 AD7280A_CTRL_HB_CONV_INPUT_ALL |
285 AD7280A_CTRL_HB_CONV_RES_READ_ALL |
286 AD7280A_CTRL_HB_CONV_START_CS |
287 st->ctrl_hb);
288 if (ret)
289 return ret;
290
291 ad7280_delay(st);
292
293 ret = __ad7280_read32(st, &tmp);
294 if (ret)
295 return ret;
296
297 if (ad7280_check_crc(st, tmp))
298 return -EIO;
299
300 if (((tmp >> 27) != devaddr) || (((tmp >> 23) & 0xF) != addr))
301 return -EFAULT;
302
303 return (tmp >> 11) & 0xFFF;
304 }
305
ad7280_read_all_channels(struct ad7280_state * st,unsigned cnt,unsigned * array)306 static int ad7280_read_all_channels(struct ad7280_state *st, unsigned cnt,
307 unsigned *array)
308 {
309 int i, ret;
310 unsigned tmp, sum = 0;
311
312 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_READ, 1,
313 AD7280A_CELL_VOLTAGE_1 << 2);
314 if (ret)
315 return ret;
316
317 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1,
318 AD7280A_CTRL_HB_CONV_INPUT_ALL |
319 AD7280A_CTRL_HB_CONV_RES_READ_ALL |
320 AD7280A_CTRL_HB_CONV_START_CS |
321 st->ctrl_hb);
322 if (ret)
323 return ret;
324
325 ad7280_delay(st);
326
327 for (i = 0; i < cnt; i++) {
328 ret = __ad7280_read32(st, &tmp);
329 if (ret)
330 return ret;
331
332 if (ad7280_check_crc(st, tmp))
333 return -EIO;
334
335 if (array)
336 array[i] = tmp;
337 /* only sum cell voltages */
338 if (((tmp >> 23) & 0xF) <= AD7280A_CELL_VOLTAGE_6)
339 sum += ((tmp >> 11) & 0xFFF);
340 }
341
342 return sum;
343 }
344
ad7280_chain_setup(struct ad7280_state * st)345 static int ad7280_chain_setup(struct ad7280_state *st)
346 {
347 unsigned val, n;
348 int ret;
349
350 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_LB, 1,
351 AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN |
352 AD7280A_CTRL_LB_LOCK_DEV_ADDR |
353 AD7280A_CTRL_LB_MUST_SET |
354 AD7280A_CTRL_LB_SWRST |
355 st->ctrl_lb);
356 if (ret)
357 return ret;
358
359 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_LB, 1,
360 AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN |
361 AD7280A_CTRL_LB_LOCK_DEV_ADDR |
362 AD7280A_CTRL_LB_MUST_SET |
363 st->ctrl_lb);
364 if (ret)
365 return ret;
366
367 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_READ, 1,
368 AD7280A_CONTROL_LB << 2);
369 if (ret)
370 return ret;
371
372 for (n = 0; n <= AD7280A_MAX_CHAIN; n++) {
373 ret = __ad7280_read32(st, &val);
374 if (ret)
375 return ret;
376
377 if (val == 0)
378 return n - 1;
379
380 if (ad7280_check_crc(st, val))
381 return -EIO;
382
383 if (n != AD7280A_DEVADDR(val >> 27))
384 return -EIO;
385 }
386
387 return -EFAULT;
388 }
389
ad7280_show_balance_sw(struct device * dev,struct device_attribute * attr,char * buf)390 static ssize_t ad7280_show_balance_sw(struct device *dev,
391 struct device_attribute *attr,
392 char *buf)
393 {
394 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
395 struct ad7280_state *st = iio_priv(indio_dev);
396 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
397
398 return sprintf(buf, "%d\n",
399 !!(st->cb_mask[this_attr->address >> 8] &
400 (1 << ((this_attr->address & 0xFF) + 2))));
401 }
402
ad7280_store_balance_sw(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)403 static ssize_t ad7280_store_balance_sw(struct device *dev,
404 struct device_attribute *attr,
405 const char *buf,
406 size_t len)
407 {
408 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
409 struct ad7280_state *st = iio_priv(indio_dev);
410 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
411 bool readin;
412 int ret;
413 unsigned devaddr, ch;
414
415 ret = strtobool(buf, &readin);
416 if (ret)
417 return ret;
418
419 devaddr = this_attr->address >> 8;
420 ch = this_attr->address & 0xFF;
421
422 mutex_lock(&indio_dev->mlock);
423 if (readin)
424 st->cb_mask[devaddr] |= 1 << (ch + 2);
425 else
426 st->cb_mask[devaddr] &= ~(1 << (ch + 2));
427
428 ret = ad7280_write(st, devaddr, AD7280A_CELL_BALANCE,
429 0, st->cb_mask[devaddr]);
430 mutex_unlock(&indio_dev->mlock);
431
432 return ret ? ret : len;
433 }
434
ad7280_show_balance_timer(struct device * dev,struct device_attribute * attr,char * buf)435 static ssize_t ad7280_show_balance_timer(struct device *dev,
436 struct device_attribute *attr,
437 char *buf)
438 {
439 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
440 struct ad7280_state *st = iio_priv(indio_dev);
441 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
442 int ret;
443 unsigned msecs;
444
445 mutex_lock(&indio_dev->mlock);
446 ret = ad7280_read(st, this_attr->address >> 8,
447 this_attr->address & 0xFF);
448 mutex_unlock(&indio_dev->mlock);
449
450 if (ret < 0)
451 return ret;
452
453 msecs = (ret >> 3) * 71500;
454
455 return sprintf(buf, "%u\n", msecs);
456 }
457
ad7280_store_balance_timer(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)458 static ssize_t ad7280_store_balance_timer(struct device *dev,
459 struct device_attribute *attr,
460 const char *buf,
461 size_t len)
462 {
463 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
464 struct ad7280_state *st = iio_priv(indio_dev);
465 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
466 unsigned long val;
467 int ret;
468
469 ret = kstrtoul(buf, 10, &val);
470 if (ret)
471 return ret;
472
473 val /= 71500;
474
475 if (val > 31)
476 return -EINVAL;
477
478 mutex_lock(&indio_dev->mlock);
479 ret = ad7280_write(st, this_attr->address >> 8,
480 this_attr->address & 0xFF,
481 0, (val & 0x1F) << 3);
482 mutex_unlock(&indio_dev->mlock);
483
484 return ret ? ret : len;
485 }
486
487 static struct attribute *ad7280_attributes[AD7280A_MAX_CHAIN *
488 AD7280A_CELLS_PER_DEV * 2 + 1];
489
490 static struct attribute_group ad7280_attrs_group = {
491 .attrs = ad7280_attributes,
492 };
493
ad7280_channel_init(struct ad7280_state * st)494 static int ad7280_channel_init(struct ad7280_state *st)
495 {
496 int dev, ch, cnt;
497
498 st->channels = kcalloc((st->slave_num + 1) * 12 + 2,
499 sizeof(*st->channels), GFP_KERNEL);
500 if (!st->channels)
501 return -ENOMEM;
502
503 for (dev = 0, cnt = 0; dev <= st->slave_num; dev++)
504 for (ch = AD7280A_CELL_VOLTAGE_1; ch <= AD7280A_AUX_ADC_6;
505 ch++, cnt++) {
506 if (ch < AD7280A_AUX_ADC_1) {
507 st->channels[cnt].type = IIO_VOLTAGE;
508 st->channels[cnt].differential = 1;
509 st->channels[cnt].channel = (dev * 6) + ch;
510 st->channels[cnt].channel2 =
511 st->channels[cnt].channel + 1;
512 } else {
513 st->channels[cnt].type = IIO_TEMP;
514 st->channels[cnt].channel = (dev * 6) + ch - 6;
515 }
516 st->channels[cnt].indexed = 1;
517 st->channels[cnt].info_mask_separate =
518 BIT(IIO_CHAN_INFO_RAW);
519 st->channels[cnt].info_mask_shared_by_type =
520 BIT(IIO_CHAN_INFO_SCALE);
521 st->channels[cnt].address =
522 AD7280A_DEVADDR(dev) << 8 | ch;
523 st->channels[cnt].scan_index = cnt;
524 st->channels[cnt].scan_type.sign = 'u';
525 st->channels[cnt].scan_type.realbits = 12;
526 st->channels[cnt].scan_type.storagebits = 32;
527 st->channels[cnt].scan_type.shift = 0;
528 }
529
530 st->channels[cnt].type = IIO_VOLTAGE;
531 st->channels[cnt].differential = 1;
532 st->channels[cnt].channel = 0;
533 st->channels[cnt].channel2 = dev * 6;
534 st->channels[cnt].address = AD7280A_ALL_CELLS;
535 st->channels[cnt].indexed = 1;
536 st->channels[cnt].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
537 st->channels[cnt].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
538 st->channels[cnt].scan_index = cnt;
539 st->channels[cnt].scan_type.sign = 'u';
540 st->channels[cnt].scan_type.realbits = 32;
541 st->channels[cnt].scan_type.storagebits = 32;
542 st->channels[cnt].scan_type.shift = 0;
543 cnt++;
544 st->channels[cnt].type = IIO_TIMESTAMP;
545 st->channels[cnt].channel = -1;
546 st->channels[cnt].scan_index = cnt;
547 st->channels[cnt].scan_type.sign = 's';
548 st->channels[cnt].scan_type.realbits = 64;
549 st->channels[cnt].scan_type.storagebits = 64;
550 st->channels[cnt].scan_type.shift = 0;
551
552 return cnt + 1;
553 }
554
ad7280_attr_init(struct ad7280_state * st)555 static int ad7280_attr_init(struct ad7280_state *st)
556 {
557 int dev, ch, cnt;
558
559 st->iio_attr = kcalloc(2, sizeof(*st->iio_attr) *
560 (st->slave_num + 1) * AD7280A_CELLS_PER_DEV,
561 GFP_KERNEL);
562 if (!st->iio_attr)
563 return -ENOMEM;
564
565 for (dev = 0, cnt = 0; dev <= st->slave_num; dev++)
566 for (ch = AD7280A_CELL_VOLTAGE_1; ch <= AD7280A_CELL_VOLTAGE_6;
567 ch++, cnt++) {
568 st->iio_attr[cnt].address =
569 AD7280A_DEVADDR(dev) << 8 | ch;
570 st->iio_attr[cnt].dev_attr.attr.mode =
571 S_IWUSR | S_IRUGO;
572 st->iio_attr[cnt].dev_attr.show =
573 ad7280_show_balance_sw;
574 st->iio_attr[cnt].dev_attr.store =
575 ad7280_store_balance_sw;
576 st->iio_attr[cnt].dev_attr.attr.name =
577 kasprintf(GFP_KERNEL,
578 "in%d-in%d_balance_switch_en",
579 dev * AD7280A_CELLS_PER_DEV + ch,
580 dev * AD7280A_CELLS_PER_DEV + ch + 1);
581 ad7280_attributes[cnt] =
582 &st->iio_attr[cnt].dev_attr.attr;
583 cnt++;
584 st->iio_attr[cnt].address =
585 AD7280A_DEVADDR(dev) << 8 |
586 (AD7280A_CB1_TIMER + ch);
587 st->iio_attr[cnt].dev_attr.attr.mode =
588 S_IWUSR | S_IRUGO;
589 st->iio_attr[cnt].dev_attr.show =
590 ad7280_show_balance_timer;
591 st->iio_attr[cnt].dev_attr.store =
592 ad7280_store_balance_timer;
593 st->iio_attr[cnt].dev_attr.attr.name =
594 kasprintf(GFP_KERNEL,
595 "in%d-in%d_balance_timer",
596 dev * AD7280A_CELLS_PER_DEV + ch,
597 dev * AD7280A_CELLS_PER_DEV + ch + 1);
598 ad7280_attributes[cnt] =
599 &st->iio_attr[cnt].dev_attr.attr;
600 }
601
602 ad7280_attributes[cnt] = NULL;
603
604 return 0;
605 }
606
ad7280_read_channel_config(struct device * dev,struct device_attribute * attr,char * buf)607 static ssize_t ad7280_read_channel_config(struct device *dev,
608 struct device_attribute *attr,
609 char *buf)
610 {
611 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
612 struct ad7280_state *st = iio_priv(indio_dev);
613 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
614 unsigned val;
615
616 switch ((u32)this_attr->address) {
617 case AD7280A_CELL_OVERVOLTAGE:
618 val = 1000 + (st->cell_threshhigh * 1568) / 100;
619 break;
620 case AD7280A_CELL_UNDERVOLTAGE:
621 val = 1000 + (st->cell_threshlow * 1568) / 100;
622 break;
623 case AD7280A_AUX_ADC_OVERVOLTAGE:
624 val = (st->aux_threshhigh * 196) / 10;
625 break;
626 case AD7280A_AUX_ADC_UNDERVOLTAGE:
627 val = (st->aux_threshlow * 196) / 10;
628 break;
629 default:
630 return -EINVAL;
631 }
632
633 return sprintf(buf, "%u\n", val);
634 }
635
ad7280_write_channel_config(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)636 static ssize_t ad7280_write_channel_config(struct device *dev,
637 struct device_attribute *attr,
638 const char *buf,
639 size_t len)
640 {
641 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
642 struct ad7280_state *st = iio_priv(indio_dev);
643 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
644
645 long val;
646 int ret;
647
648 ret = kstrtol(buf, 10, &val);
649 if (ret)
650 return ret;
651
652 switch ((u32)this_attr->address) {
653 case AD7280A_CELL_OVERVOLTAGE:
654 case AD7280A_CELL_UNDERVOLTAGE:
655 val = ((val - 1000) * 100) / 1568; /* LSB 15.68mV */
656 break;
657 case AD7280A_AUX_ADC_OVERVOLTAGE:
658 case AD7280A_AUX_ADC_UNDERVOLTAGE:
659 val = (val * 10) / 196; /* LSB 19.6mV */
660 break;
661 default:
662 return -EFAULT;
663 }
664
665 val = clamp(val, 0L, 0xFFL);
666
667 mutex_lock(&indio_dev->mlock);
668 switch ((u32)this_attr->address) {
669 case AD7280A_CELL_OVERVOLTAGE:
670 st->cell_threshhigh = val;
671 break;
672 case AD7280A_CELL_UNDERVOLTAGE:
673 st->cell_threshlow = val;
674 break;
675 case AD7280A_AUX_ADC_OVERVOLTAGE:
676 st->aux_threshhigh = val;
677 break;
678 case AD7280A_AUX_ADC_UNDERVOLTAGE:
679 st->aux_threshlow = val;
680 break;
681 }
682
683 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER,
684 this_attr->address, 1, val);
685
686 mutex_unlock(&indio_dev->mlock);
687
688 return ret ? ret : len;
689 }
690
ad7280_event_handler(int irq,void * private)691 static irqreturn_t ad7280_event_handler(int irq, void *private)
692 {
693 struct iio_dev *indio_dev = private;
694 struct ad7280_state *st = iio_priv(indio_dev);
695 unsigned *channels;
696 int i, ret;
697
698 channels = kcalloc(st->scan_cnt, sizeof(*channels), GFP_KERNEL);
699 if (!channels)
700 return IRQ_HANDLED;
701
702 ret = ad7280_read_all_channels(st, st->scan_cnt, channels);
703 if (ret < 0)
704 goto out;
705
706 for (i = 0; i < st->scan_cnt; i++) {
707 if (((channels[i] >> 23) & 0xF) <= AD7280A_CELL_VOLTAGE_6) {
708 if (((channels[i] >> 11) & 0xFFF) >=
709 st->cell_threshhigh)
710 iio_push_event(indio_dev,
711 IIO_EVENT_CODE(IIO_VOLTAGE,
712 1,
713 0,
714 IIO_EV_DIR_RISING,
715 IIO_EV_TYPE_THRESH,
716 0, 0, 0),
717 iio_get_time_ns());
718 else if (((channels[i] >> 11) & 0xFFF) <=
719 st->cell_threshlow)
720 iio_push_event(indio_dev,
721 IIO_EVENT_CODE(IIO_VOLTAGE,
722 1,
723 0,
724 IIO_EV_DIR_FALLING,
725 IIO_EV_TYPE_THRESH,
726 0, 0, 0),
727 iio_get_time_ns());
728 } else {
729 if (((channels[i] >> 11) & 0xFFF) >= st->aux_threshhigh)
730 iio_push_event(indio_dev,
731 IIO_UNMOD_EVENT_CODE(
732 IIO_TEMP,
733 0,
734 IIO_EV_TYPE_THRESH,
735 IIO_EV_DIR_RISING),
736 iio_get_time_ns());
737 else if (((channels[i] >> 11) & 0xFFF) <=
738 st->aux_threshlow)
739 iio_push_event(indio_dev,
740 IIO_UNMOD_EVENT_CODE(
741 IIO_TEMP,
742 0,
743 IIO_EV_TYPE_THRESH,
744 IIO_EV_DIR_FALLING),
745 iio_get_time_ns());
746 }
747 }
748
749 out:
750 kfree(channels);
751
752 return IRQ_HANDLED;
753 }
754
755 static IIO_DEVICE_ATTR_NAMED(in_thresh_low_value,
756 in_voltage-voltage_thresh_low_value,
757 S_IRUGO | S_IWUSR,
758 ad7280_read_channel_config,
759 ad7280_write_channel_config,
760 AD7280A_CELL_UNDERVOLTAGE);
761
762 static IIO_DEVICE_ATTR_NAMED(in_thresh_high_value,
763 in_voltage-voltage_thresh_high_value,
764 S_IRUGO | S_IWUSR,
765 ad7280_read_channel_config,
766 ad7280_write_channel_config,
767 AD7280A_CELL_OVERVOLTAGE);
768
769 static IIO_DEVICE_ATTR(in_temp_thresh_low_value,
770 S_IRUGO | S_IWUSR,
771 ad7280_read_channel_config,
772 ad7280_write_channel_config,
773 AD7280A_AUX_ADC_UNDERVOLTAGE);
774
775 static IIO_DEVICE_ATTR(in_temp_thresh_high_value,
776 S_IRUGO | S_IWUSR,
777 ad7280_read_channel_config,
778 ad7280_write_channel_config,
779 AD7280A_AUX_ADC_OVERVOLTAGE);
780
781 static struct attribute *ad7280_event_attributes[] = {
782 &iio_dev_attr_in_thresh_low_value.dev_attr.attr,
783 &iio_dev_attr_in_thresh_high_value.dev_attr.attr,
784 &iio_dev_attr_in_temp_thresh_low_value.dev_attr.attr,
785 &iio_dev_attr_in_temp_thresh_high_value.dev_attr.attr,
786 NULL,
787 };
788
789 static struct attribute_group ad7280_event_attrs_group = {
790 .attrs = ad7280_event_attributes,
791 };
792
ad7280_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)793 static int ad7280_read_raw(struct iio_dev *indio_dev,
794 struct iio_chan_spec const *chan,
795 int *val,
796 int *val2,
797 long m)
798 {
799 struct ad7280_state *st = iio_priv(indio_dev);
800 int ret;
801
802 switch (m) {
803 case IIO_CHAN_INFO_RAW:
804 mutex_lock(&indio_dev->mlock);
805 if (chan->address == AD7280A_ALL_CELLS)
806 ret = ad7280_read_all_channels(st, st->scan_cnt, NULL);
807 else
808 ret = ad7280_read_channel(st, chan->address >> 8,
809 chan->address & 0xFF);
810 mutex_unlock(&indio_dev->mlock);
811
812 if (ret < 0)
813 return ret;
814
815 *val = ret;
816
817 return IIO_VAL_INT;
818 case IIO_CHAN_INFO_SCALE:
819 if ((chan->address & 0xFF) <= AD7280A_CELL_VOLTAGE_6)
820 *val = 4000;
821 else
822 *val = 5000;
823
824 *val2 = AD7280A_BITS;
825 return IIO_VAL_FRACTIONAL_LOG2;
826 }
827 return -EINVAL;
828 }
829
830 static const struct iio_info ad7280_info = {
831 .read_raw = ad7280_read_raw,
832 .event_attrs = &ad7280_event_attrs_group,
833 .attrs = &ad7280_attrs_group,
834 .driver_module = THIS_MODULE,
835 };
836
837 static const struct ad7280_platform_data ad7793_default_pdata = {
838 .acquisition_time = AD7280A_ACQ_TIME_400ns,
839 .conversion_averaging = AD7280A_CONV_AVG_DIS,
840 .thermistor_term_en = true,
841 };
842
ad7280_probe(struct spi_device * spi)843 static int ad7280_probe(struct spi_device *spi)
844 {
845 const struct ad7280_platform_data *pdata = spi->dev.platform_data;
846 struct ad7280_state *st;
847 int ret;
848 const unsigned short tACQ_ns[4] = {465, 1010, 1460, 1890};
849 const unsigned short nAVG[4] = {1, 2, 4, 8};
850 struct iio_dev *indio_dev;
851
852 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
853 if (!indio_dev)
854 return -ENOMEM;
855
856 st = iio_priv(indio_dev);
857 spi_set_drvdata(spi, indio_dev);
858 st->spi = spi;
859
860 if (!pdata)
861 pdata = &ad7793_default_pdata;
862
863 ad7280_crc8_build_table(st->crc_tab);
864
865 st->spi->max_speed_hz = AD7280A_MAX_SPI_CLK_HZ;
866 st->spi->mode = SPI_MODE_1;
867 spi_setup(st->spi);
868
869 st->ctrl_lb = AD7280A_CTRL_LB_ACQ_TIME(pdata->acquisition_time & 0x3);
870 st->ctrl_hb = AD7280A_CTRL_HB_CONV_AVG(pdata->conversion_averaging
871 & 0x3) | (pdata->thermistor_term_en ?
872 AD7280A_CTRL_LB_THERMISTOR_EN : 0);
873
874 ret = ad7280_chain_setup(st);
875 if (ret < 0)
876 return ret;
877
878 st->slave_num = ret;
879 st->scan_cnt = (st->slave_num + 1) * AD7280A_NUM_CH;
880 st->cell_threshhigh = 0xFF;
881 st->aux_threshhigh = 0xFF;
882
883 /*
884 * Total Conversion Time = ((tACQ + tCONV) *
885 * (Number of Conversions per Part)) −
886 * tACQ + ((N - 1) * tDELAY)
887 *
888 * Readback Delay = Total Conversion Time + tWAIT
889 */
890
891 st->readback_delay_us =
892 ((tACQ_ns[pdata->acquisition_time & 0x3] + 695) *
893 (AD7280A_NUM_CH * nAVG[pdata->conversion_averaging & 0x3]))
894 - tACQ_ns[pdata->acquisition_time & 0x3] +
895 st->slave_num * 250;
896
897 /* Convert to usecs */
898 st->readback_delay_us = DIV_ROUND_UP(st->readback_delay_us, 1000);
899 st->readback_delay_us += 5; /* Add tWAIT */
900
901 indio_dev->name = spi_get_device_id(spi)->name;
902 indio_dev->dev.parent = &spi->dev;
903 indio_dev->modes = INDIO_DIRECT_MODE;
904
905 ret = ad7280_channel_init(st);
906 if (ret < 0)
907 return ret;
908
909 indio_dev->num_channels = ret;
910 indio_dev->channels = st->channels;
911 indio_dev->info = &ad7280_info;
912
913 ret = ad7280_attr_init(st);
914 if (ret < 0)
915 goto error_free_channels;
916
917 ret = iio_device_register(indio_dev);
918 if (ret)
919 goto error_free_attr;
920
921 if (spi->irq > 0) {
922 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER,
923 AD7280A_ALERT, 1,
924 AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN);
925 if (ret)
926 goto error_unregister;
927
928 ret = ad7280_write(st, AD7280A_DEVADDR(st->slave_num),
929 AD7280A_ALERT, 0,
930 AD7280A_ALERT_GEN_STATIC_HIGH |
931 (pdata->chain_last_alert_ignore & 0xF));
932 if (ret)
933 goto error_unregister;
934
935 ret = request_threaded_irq(spi->irq,
936 NULL,
937 ad7280_event_handler,
938 IRQF_TRIGGER_FALLING |
939 IRQF_ONESHOT,
940 indio_dev->name,
941 indio_dev);
942 if (ret)
943 goto error_unregister;
944 }
945
946 return 0;
947 error_unregister:
948 iio_device_unregister(indio_dev);
949
950 error_free_attr:
951 kfree(st->iio_attr);
952
953 error_free_channels:
954 kfree(st->channels);
955
956 return ret;
957 }
958
ad7280_remove(struct spi_device * spi)959 static int ad7280_remove(struct spi_device *spi)
960 {
961 struct iio_dev *indio_dev = spi_get_drvdata(spi);
962 struct ad7280_state *st = iio_priv(indio_dev);
963
964 if (spi->irq > 0)
965 free_irq(spi->irq, indio_dev);
966 iio_device_unregister(indio_dev);
967
968 ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1,
969 AD7280A_CTRL_HB_PWRDN_SW | st->ctrl_hb);
970
971 kfree(st->channels);
972 kfree(st->iio_attr);
973
974 return 0;
975 }
976
977 static const struct spi_device_id ad7280_id[] = {
978 {"ad7280a", 0},
979 {}
980 };
981 MODULE_DEVICE_TABLE(spi, ad7280_id);
982
983 static struct spi_driver ad7280_driver = {
984 .driver = {
985 .name = "ad7280",
986 },
987 .probe = ad7280_probe,
988 .remove = ad7280_remove,
989 .id_table = ad7280_id,
990 };
991 module_spi_driver(ad7280_driver);
992
993 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
994 MODULE_DESCRIPTION("Analog Devices AD7280A");
995 MODULE_LICENSE("GPL v2");
996