1 /*
2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * DMA support added by Chip Coldwell.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25 #include <linux/module.h>
26 #include <linux/tty.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/serial.h>
31 #include <linux/clk.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/of_gpio.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmaengine.h>
41 #include <linux/atmel_pdc.h>
42 #include <linux/atmel_serial.h>
43 #include <linux/uaccess.h>
44 #include <linux/platform_data/atmel.h>
45 #include <linux/timer.h>
46 #include <linux/gpio.h>
47 #include <linux/gpio/consumer.h>
48 #include <linux/err.h>
49 #include <linux/irq.h>
50 #include <linux/suspend.h>
51
52 #include <asm/io.h>
53 #include <asm/ioctls.h>
54
55 #define PDC_BUFFER_SIZE 512
56 /* Revisit: We should calculate this based on the actual port settings */
57 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
58
59 /* The minium number of data FIFOs should be able to contain */
60 #define ATMEL_MIN_FIFO_SIZE 8
61 /*
62 * These two offsets are substracted from the RX FIFO size to define the RTS
63 * high and low thresholds
64 */
65 #define ATMEL_RTS_HIGH_OFFSET 16
66 #define ATMEL_RTS_LOW_OFFSET 20
67
68 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
69 #define SUPPORT_SYSRQ
70 #endif
71
72 #include <linux/serial_core.h>
73
74 #include "serial_mctrl_gpio.h"
75
76 static void atmel_start_rx(struct uart_port *port);
77 static void atmel_stop_rx(struct uart_port *port);
78
79 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
80
81 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
82 * should coexist with the 8250 driver, such as if we have an external 16C550
83 * UART. */
84 #define SERIAL_ATMEL_MAJOR 204
85 #define MINOR_START 154
86 #define ATMEL_DEVICENAME "ttyAT"
87
88 #else
89
90 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
91 * name, but it is legally reserved for the 8250 driver. */
92 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
93 #define MINOR_START 64
94 #define ATMEL_DEVICENAME "ttyS"
95
96 #endif
97
98 #define ATMEL_ISR_PASS_LIMIT 256
99
100 struct atmel_dma_buffer {
101 unsigned char *buf;
102 dma_addr_t dma_addr;
103 unsigned int dma_size;
104 unsigned int ofs;
105 };
106
107 struct atmel_uart_char {
108 u16 status;
109 u16 ch;
110 };
111
112 #define ATMEL_SERIAL_RINGSIZE 1024
113
114 /*
115 * at91: 6 USARTs and one DBGU port (SAM9260)
116 * avr32: 4
117 */
118 #define ATMEL_MAX_UART 7
119
120 /*
121 * We wrap our port structure around the generic uart_port.
122 */
123 struct atmel_uart_port {
124 struct uart_port uart; /* uart */
125 struct clk *clk; /* uart clock */
126 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
127 u32 backup_imr; /* IMR saved during suspend */
128 int break_active; /* break being received */
129
130 bool use_dma_rx; /* enable DMA receiver */
131 bool use_pdc_rx; /* enable PDC receiver */
132 short pdc_rx_idx; /* current PDC RX buffer */
133 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
134
135 bool use_dma_tx; /* enable DMA transmitter */
136 bool use_pdc_tx; /* enable PDC transmitter */
137 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
138
139 spinlock_t lock_tx; /* port lock */
140 spinlock_t lock_rx; /* port lock */
141 struct dma_chan *chan_tx;
142 struct dma_chan *chan_rx;
143 struct dma_async_tx_descriptor *desc_tx;
144 struct dma_async_tx_descriptor *desc_rx;
145 dma_cookie_t cookie_tx;
146 dma_cookie_t cookie_rx;
147 struct scatterlist sg_tx;
148 struct scatterlist sg_rx;
149 struct tasklet_struct tasklet;
150 unsigned int irq_status;
151 unsigned int irq_status_prev;
152 unsigned int status_change;
153 unsigned int tx_len;
154
155 struct circ_buf rx_ring;
156
157 struct mctrl_gpios *gpios;
158 int gpio_irq[UART_GPIO_MAX];
159 unsigned int tx_done_mask;
160 u32 fifo_size;
161 u32 rts_high;
162 u32 rts_low;
163 bool ms_irq_enabled;
164 bool is_usart; /* usart or uart */
165 struct timer_list uart_timer; /* uart timer */
166
167 bool suspended;
168 unsigned int pending;
169 unsigned int pending_status;
170 spinlock_t lock_suspended;
171
172 bool hd_start_rx; /* can start RX during half-duplex operation */
173
174 int (*prepare_rx)(struct uart_port *port);
175 int (*prepare_tx)(struct uart_port *port);
176 void (*schedule_rx)(struct uart_port *port);
177 void (*schedule_tx)(struct uart_port *port);
178 void (*release_rx)(struct uart_port *port);
179 void (*release_tx)(struct uart_port *port);
180 };
181
182 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
183 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
184
185 #ifdef SUPPORT_SYSRQ
186 static struct console atmel_console;
187 #endif
188
189 #if defined(CONFIG_OF)
190 static const struct of_device_id atmel_serial_dt_ids[] = {
191 { .compatible = "atmel,at91rm9200-usart" },
192 { .compatible = "atmel,at91sam9260-usart" },
193 { /* sentinel */ }
194 };
195
196 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
197 #endif
198
199 static inline struct atmel_uart_port *
to_atmel_uart_port(struct uart_port * uart)200 to_atmel_uart_port(struct uart_port *uart)
201 {
202 return container_of(uart, struct atmel_uart_port, uart);
203 }
204
atmel_uart_readl(struct uart_port * port,u32 reg)205 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
206 {
207 return __raw_readl(port->membase + reg);
208 }
209
atmel_uart_writel(struct uart_port * port,u32 reg,u32 value)210 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
211 {
212 __raw_writel(value, port->membase + reg);
213 }
214
215 #ifdef CONFIG_AVR32
216
217 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
atmel_uart_read_char(struct uart_port * port)218 static inline u8 atmel_uart_read_char(struct uart_port *port)
219 {
220 return __raw_readl(port->membase + ATMEL_US_RHR);
221 }
222
atmel_uart_write_char(struct uart_port * port,u8 value)223 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
224 {
225 __raw_writel(value, port->membase + ATMEL_US_THR);
226 }
227
228 #else
229
atmel_uart_read_char(struct uart_port * port)230 static inline u8 atmel_uart_read_char(struct uart_port *port)
231 {
232 return __raw_readb(port->membase + ATMEL_US_RHR);
233 }
234
atmel_uart_write_char(struct uart_port * port,u8 value)235 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
236 {
237 __raw_writeb(value, port->membase + ATMEL_US_THR);
238 }
239
240 #endif
241
atmel_uart_is_half_duplex(struct uart_port * port)242 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
243 {
244 return (port->rs485.flags & SER_RS485_ENABLED) &&
245 !(port->rs485.flags & SER_RS485_RX_DURING_TX);
246 }
247
248 #ifdef CONFIG_SERIAL_ATMEL_PDC
atmel_use_pdc_rx(struct uart_port * port)249 static bool atmel_use_pdc_rx(struct uart_port *port)
250 {
251 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
252
253 return atmel_port->use_pdc_rx;
254 }
255
atmel_use_pdc_tx(struct uart_port * port)256 static bool atmel_use_pdc_tx(struct uart_port *port)
257 {
258 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
259
260 return atmel_port->use_pdc_tx;
261 }
262 #else
atmel_use_pdc_rx(struct uart_port * port)263 static bool atmel_use_pdc_rx(struct uart_port *port)
264 {
265 return false;
266 }
267
atmel_use_pdc_tx(struct uart_port * port)268 static bool atmel_use_pdc_tx(struct uart_port *port)
269 {
270 return false;
271 }
272 #endif
273
atmel_use_dma_tx(struct uart_port * port)274 static bool atmel_use_dma_tx(struct uart_port *port)
275 {
276 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
277
278 return atmel_port->use_dma_tx;
279 }
280
atmel_use_dma_rx(struct uart_port * port)281 static bool atmel_use_dma_rx(struct uart_port *port)
282 {
283 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
284
285 return atmel_port->use_dma_rx;
286 }
287
atmel_use_fifo(struct uart_port * port)288 static bool atmel_use_fifo(struct uart_port *port)
289 {
290 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
291
292 return atmel_port->fifo_size;
293 }
294
atmel_get_lines_status(struct uart_port * port)295 static unsigned int atmel_get_lines_status(struct uart_port *port)
296 {
297 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
298 unsigned int status, ret = 0;
299
300 status = atmel_uart_readl(port, ATMEL_US_CSR);
301
302 mctrl_gpio_get(atmel_port->gpios, &ret);
303
304 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
305 UART_GPIO_CTS))) {
306 if (ret & TIOCM_CTS)
307 status &= ~ATMEL_US_CTS;
308 else
309 status |= ATMEL_US_CTS;
310 }
311
312 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
313 UART_GPIO_DSR))) {
314 if (ret & TIOCM_DSR)
315 status &= ~ATMEL_US_DSR;
316 else
317 status |= ATMEL_US_DSR;
318 }
319
320 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
321 UART_GPIO_RI))) {
322 if (ret & TIOCM_RI)
323 status &= ~ATMEL_US_RI;
324 else
325 status |= ATMEL_US_RI;
326 }
327
328 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
329 UART_GPIO_DCD))) {
330 if (ret & TIOCM_CD)
331 status &= ~ATMEL_US_DCD;
332 else
333 status |= ATMEL_US_DCD;
334 }
335
336 return status;
337 }
338
339 /* Enable or disable the rs485 support */
atmel_config_rs485(struct uart_port * port,struct serial_rs485 * rs485conf)340 static int atmel_config_rs485(struct uart_port *port,
341 struct serial_rs485 *rs485conf)
342 {
343 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
344 unsigned int mode;
345
346 /* Disable interrupts */
347 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
348
349 mode = atmel_uart_readl(port, ATMEL_US_MR);
350
351 /* Resetting serial mode to RS232 (0x0) */
352 mode &= ~ATMEL_US_USMODE;
353
354 port->rs485 = *rs485conf;
355
356 if (rs485conf->flags & SER_RS485_ENABLED) {
357 dev_dbg(port->dev, "Setting UART to RS485\n");
358 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
359 atmel_uart_writel(port, ATMEL_US_TTGR,
360 rs485conf->delay_rts_after_send);
361 mode |= ATMEL_US_USMODE_RS485;
362 } else {
363 dev_dbg(port->dev, "Setting UART to RS232\n");
364 if (atmel_use_pdc_tx(port))
365 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
366 ATMEL_US_TXBUFE;
367 else
368 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
369 }
370 atmel_uart_writel(port, ATMEL_US_MR, mode);
371
372 /* Enable interrupts */
373 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
374
375 return 0;
376 }
377
378 /*
379 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
380 */
atmel_tx_empty(struct uart_port * port)381 static u_int atmel_tx_empty(struct uart_port *port)
382 {
383 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
384 TIOCSER_TEMT :
385 0;
386 }
387
388 /*
389 * Set state of the modem control output lines
390 */
atmel_set_mctrl(struct uart_port * port,u_int mctrl)391 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
392 {
393 unsigned int control = 0;
394 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
395 unsigned int rts_paused, rts_ready;
396 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
397
398 /* override mode to RS485 if needed, otherwise keep the current mode */
399 if (port->rs485.flags & SER_RS485_ENABLED) {
400 atmel_uart_writel(port, ATMEL_US_TTGR,
401 port->rs485.delay_rts_after_send);
402 mode &= ~ATMEL_US_USMODE;
403 mode |= ATMEL_US_USMODE_RS485;
404 }
405
406 /* set the RTS line state according to the mode */
407 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
408 /* force RTS line to high level */
409 rts_paused = ATMEL_US_RTSEN;
410
411 /* give the control of the RTS line back to the hardware */
412 rts_ready = ATMEL_US_RTSDIS;
413 } else {
414 /* force RTS line to high level */
415 rts_paused = ATMEL_US_RTSDIS;
416
417 /* force RTS line to low level */
418 rts_ready = ATMEL_US_RTSEN;
419 }
420
421 if (mctrl & TIOCM_RTS)
422 control |= rts_ready;
423 else
424 control |= rts_paused;
425
426 if (mctrl & TIOCM_DTR)
427 control |= ATMEL_US_DTREN;
428 else
429 control |= ATMEL_US_DTRDIS;
430
431 atmel_uart_writel(port, ATMEL_US_CR, control);
432
433 mctrl_gpio_set(atmel_port->gpios, mctrl);
434
435 /* Local loopback mode? */
436 mode &= ~ATMEL_US_CHMODE;
437 if (mctrl & TIOCM_LOOP)
438 mode |= ATMEL_US_CHMODE_LOC_LOOP;
439 else
440 mode |= ATMEL_US_CHMODE_NORMAL;
441
442 atmel_uart_writel(port, ATMEL_US_MR, mode);
443 }
444
445 /*
446 * Get state of the modem control input lines
447 */
atmel_get_mctrl(struct uart_port * port)448 static u_int atmel_get_mctrl(struct uart_port *port)
449 {
450 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
451 unsigned int ret = 0, status;
452
453 status = atmel_uart_readl(port, ATMEL_US_CSR);
454
455 /*
456 * The control signals are active low.
457 */
458 if (!(status & ATMEL_US_DCD))
459 ret |= TIOCM_CD;
460 if (!(status & ATMEL_US_CTS))
461 ret |= TIOCM_CTS;
462 if (!(status & ATMEL_US_DSR))
463 ret |= TIOCM_DSR;
464 if (!(status & ATMEL_US_RI))
465 ret |= TIOCM_RI;
466
467 return mctrl_gpio_get(atmel_port->gpios, &ret);
468 }
469
470 /*
471 * Stop transmitting.
472 */
atmel_stop_tx(struct uart_port * port)473 static void atmel_stop_tx(struct uart_port *port)
474 {
475 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
476
477 if (atmel_use_pdc_tx(port)) {
478 /* disable PDC transmit */
479 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
480 }
481
482 /*
483 * Disable the transmitter.
484 * This is mandatory when DMA is used, otherwise the DMA buffer
485 * is fully transmitted.
486 */
487 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
488
489 /* Disable interrupts */
490 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
491
492 if (atmel_uart_is_half_duplex(port))
493 atmel_start_rx(port);
494
495 }
496
497 /*
498 * Start transmitting.
499 */
atmel_start_tx(struct uart_port * port)500 static void atmel_start_tx(struct uart_port *port)
501 {
502 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
503
504 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
505 & ATMEL_PDC_TXTEN))
506 /* The transmitter is already running. Yes, we
507 really need this.*/
508 return;
509
510 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
511 if (atmel_uart_is_half_duplex(port))
512 atmel_stop_rx(port);
513
514 if (atmel_use_pdc_tx(port))
515 /* re-enable PDC transmit */
516 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
517
518 /* Enable interrupts */
519 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
520
521 /* re-enable the transmitter */
522 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
523 }
524
525 /*
526 * start receiving - port is in process of being opened.
527 */
atmel_start_rx(struct uart_port * port)528 static void atmel_start_rx(struct uart_port *port)
529 {
530 /* reset status and receiver */
531 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
532
533 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
534
535 if (atmel_use_pdc_rx(port)) {
536 /* enable PDC controller */
537 atmel_uart_writel(port, ATMEL_US_IER,
538 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
539 port->read_status_mask);
540 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
541 } else {
542 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
543 }
544 }
545
546 /*
547 * Stop receiving - port is in process of being closed.
548 */
atmel_stop_rx(struct uart_port * port)549 static void atmel_stop_rx(struct uart_port *port)
550 {
551 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
552
553 if (atmel_use_pdc_rx(port)) {
554 /* disable PDC receive */
555 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
556 atmel_uart_writel(port, ATMEL_US_IDR,
557 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
558 port->read_status_mask);
559 } else {
560 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
561 }
562 }
563
564 /*
565 * Enable modem status interrupts
566 */
atmel_enable_ms(struct uart_port * port)567 static void atmel_enable_ms(struct uart_port *port)
568 {
569 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
570 uint32_t ier = 0;
571
572 /*
573 * Interrupt should not be enabled twice
574 */
575 if (atmel_port->ms_irq_enabled)
576 return;
577
578 atmel_port->ms_irq_enabled = true;
579
580 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
581 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
582 else
583 ier |= ATMEL_US_CTSIC;
584
585 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
586 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
587 else
588 ier |= ATMEL_US_DSRIC;
589
590 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
591 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
592 else
593 ier |= ATMEL_US_RIIC;
594
595 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
596 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
597 else
598 ier |= ATMEL_US_DCDIC;
599
600 atmel_uart_writel(port, ATMEL_US_IER, ier);
601 }
602
603 /*
604 * Disable modem status interrupts
605 */
atmel_disable_ms(struct uart_port * port)606 static void atmel_disable_ms(struct uart_port *port)
607 {
608 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
609 uint32_t idr = 0;
610
611 /*
612 * Interrupt should not be disabled twice
613 */
614 if (!atmel_port->ms_irq_enabled)
615 return;
616
617 atmel_port->ms_irq_enabled = false;
618
619 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
620 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
621 else
622 idr |= ATMEL_US_CTSIC;
623
624 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
625 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
626 else
627 idr |= ATMEL_US_DSRIC;
628
629 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
630 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
631 else
632 idr |= ATMEL_US_RIIC;
633
634 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
635 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
636 else
637 idr |= ATMEL_US_DCDIC;
638
639 atmel_uart_writel(port, ATMEL_US_IDR, idr);
640 }
641
642 /*
643 * Control the transmission of a break signal
644 */
atmel_break_ctl(struct uart_port * port,int break_state)645 static void atmel_break_ctl(struct uart_port *port, int break_state)
646 {
647 if (break_state != 0)
648 /* start break */
649 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
650 else
651 /* stop break */
652 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
653 }
654
655 /*
656 * Stores the incoming character in the ring buffer
657 */
658 static void
atmel_buffer_rx_char(struct uart_port * port,unsigned int status,unsigned int ch)659 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
660 unsigned int ch)
661 {
662 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
663 struct circ_buf *ring = &atmel_port->rx_ring;
664 struct atmel_uart_char *c;
665
666 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
667 /* Buffer overflow, ignore char */
668 return;
669
670 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
671 c->status = status;
672 c->ch = ch;
673
674 /* Make sure the character is stored before we update head. */
675 smp_wmb();
676
677 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
678 }
679
680 /*
681 * Deal with parity, framing and overrun errors.
682 */
atmel_pdc_rxerr(struct uart_port * port,unsigned int status)683 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
684 {
685 /* clear error */
686 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
687
688 if (status & ATMEL_US_RXBRK) {
689 /* ignore side-effect */
690 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
691 port->icount.brk++;
692 }
693 if (status & ATMEL_US_PARE)
694 port->icount.parity++;
695 if (status & ATMEL_US_FRAME)
696 port->icount.frame++;
697 if (status & ATMEL_US_OVRE)
698 port->icount.overrun++;
699 }
700
701 /*
702 * Characters received (called from interrupt handler)
703 */
atmel_rx_chars(struct uart_port * port)704 static void atmel_rx_chars(struct uart_port *port)
705 {
706 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
707 unsigned int status, ch;
708
709 status = atmel_uart_readl(port, ATMEL_US_CSR);
710 while (status & ATMEL_US_RXRDY) {
711 ch = atmel_uart_read_char(port);
712
713 /*
714 * note that the error handling code is
715 * out of the main execution path
716 */
717 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
718 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
719 || atmel_port->break_active)) {
720
721 /* clear error */
722 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
723
724 if (status & ATMEL_US_RXBRK
725 && !atmel_port->break_active) {
726 atmel_port->break_active = 1;
727 atmel_uart_writel(port, ATMEL_US_IER,
728 ATMEL_US_RXBRK);
729 } else {
730 /*
731 * This is either the end-of-break
732 * condition or we've received at
733 * least one character without RXBRK
734 * being set. In both cases, the next
735 * RXBRK will indicate start-of-break.
736 */
737 atmel_uart_writel(port, ATMEL_US_IDR,
738 ATMEL_US_RXBRK);
739 status &= ~ATMEL_US_RXBRK;
740 atmel_port->break_active = 0;
741 }
742 }
743
744 atmel_buffer_rx_char(port, status, ch);
745 status = atmel_uart_readl(port, ATMEL_US_CSR);
746 }
747
748 tasklet_schedule(&atmel_port->tasklet);
749 }
750
751 /*
752 * Transmit characters (called from tasklet with TXRDY interrupt
753 * disabled)
754 */
atmel_tx_chars(struct uart_port * port)755 static void atmel_tx_chars(struct uart_port *port)
756 {
757 struct circ_buf *xmit = &port->state->xmit;
758 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
759
760 if (port->x_char &&
761 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
762 atmel_uart_write_char(port, port->x_char);
763 port->icount.tx++;
764 port->x_char = 0;
765 }
766 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
767 return;
768
769 while (atmel_uart_readl(port, ATMEL_US_CSR) &
770 atmel_port->tx_done_mask) {
771 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
772 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
773 port->icount.tx++;
774 if (uart_circ_empty(xmit))
775 break;
776 }
777
778 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
779 uart_write_wakeup(port);
780
781 if (!uart_circ_empty(xmit))
782 /* Enable interrupts */
783 atmel_uart_writel(port, ATMEL_US_IER,
784 atmel_port->tx_done_mask);
785 }
786
atmel_complete_tx_dma(void * arg)787 static void atmel_complete_tx_dma(void *arg)
788 {
789 struct atmel_uart_port *atmel_port = arg;
790 struct uart_port *port = &atmel_port->uart;
791 struct circ_buf *xmit = &port->state->xmit;
792 struct dma_chan *chan = atmel_port->chan_tx;
793 unsigned long flags;
794
795 spin_lock_irqsave(&port->lock, flags);
796
797 if (chan)
798 dmaengine_terminate_all(chan);
799 xmit->tail += atmel_port->tx_len;
800 xmit->tail &= UART_XMIT_SIZE - 1;
801
802 port->icount.tx += atmel_port->tx_len;
803
804 spin_lock_irq(&atmel_port->lock_tx);
805 async_tx_ack(atmel_port->desc_tx);
806 atmel_port->cookie_tx = -EINVAL;
807 atmel_port->desc_tx = NULL;
808 spin_unlock_irq(&atmel_port->lock_tx);
809
810 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
811 uart_write_wakeup(port);
812
813 /*
814 * xmit is a circular buffer so, if we have just send data from
815 * xmit->tail to the end of xmit->buf, now we have to transmit the
816 * remaining data from the beginning of xmit->buf to xmit->head.
817 */
818 if (!uart_circ_empty(xmit))
819 tasklet_schedule(&atmel_port->tasklet);
820 else if (atmel_uart_is_half_duplex(port)) {
821 /*
822 * DMA done, re-enable TXEMPTY and signal that we can stop
823 * TX and start RX for RS485
824 */
825 atmel_port->hd_start_rx = true;
826 atmel_uart_writel(port, ATMEL_US_IER,
827 atmel_port->tx_done_mask);
828 }
829
830 spin_unlock_irqrestore(&port->lock, flags);
831 }
832
atmel_release_tx_dma(struct uart_port * port)833 static void atmel_release_tx_dma(struct uart_port *port)
834 {
835 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
836 struct dma_chan *chan = atmel_port->chan_tx;
837
838 if (chan) {
839 dmaengine_terminate_all(chan);
840 dma_release_channel(chan);
841 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
842 DMA_TO_DEVICE);
843 }
844
845 atmel_port->desc_tx = NULL;
846 atmel_port->chan_tx = NULL;
847 atmel_port->cookie_tx = -EINVAL;
848 }
849
850 /*
851 * Called from tasklet with TXRDY interrupt is disabled.
852 */
atmel_tx_dma(struct uart_port * port)853 static void atmel_tx_dma(struct uart_port *port)
854 {
855 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
856 struct circ_buf *xmit = &port->state->xmit;
857 struct dma_chan *chan = atmel_port->chan_tx;
858 struct dma_async_tx_descriptor *desc;
859 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
860 unsigned int tx_len, part1_len, part2_len, sg_len;
861 dma_addr_t phys_addr;
862
863 /* Make sure we have an idle channel */
864 if (atmel_port->desc_tx != NULL)
865 return;
866
867 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
868 /*
869 * DMA is idle now.
870 * Port xmit buffer is already mapped,
871 * and it is one page... Just adjust
872 * offsets and lengths. Since it is a circular buffer,
873 * we have to transmit till the end, and then the rest.
874 * Take the port lock to get a
875 * consistent xmit buffer state.
876 */
877 tx_len = CIRC_CNT_TO_END(xmit->head,
878 xmit->tail,
879 UART_XMIT_SIZE);
880
881 if (atmel_port->fifo_size) {
882 /* multi data mode */
883 part1_len = (tx_len & ~0x3); /* DWORD access */
884 part2_len = (tx_len & 0x3); /* BYTE access */
885 } else {
886 /* single data (legacy) mode */
887 part1_len = 0;
888 part2_len = tx_len; /* BYTE access only */
889 }
890
891 sg_init_table(sgl, 2);
892 sg_len = 0;
893 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
894 if (part1_len) {
895 sg = &sgl[sg_len++];
896 sg_dma_address(sg) = phys_addr;
897 sg_dma_len(sg) = part1_len;
898
899 phys_addr += part1_len;
900 }
901
902 if (part2_len) {
903 sg = &sgl[sg_len++];
904 sg_dma_address(sg) = phys_addr;
905 sg_dma_len(sg) = part2_len;
906 }
907
908 /*
909 * save tx_len so atmel_complete_tx_dma() will increase
910 * xmit->tail correctly
911 */
912 atmel_port->tx_len = tx_len;
913
914 desc = dmaengine_prep_slave_sg(chan,
915 sgl,
916 sg_len,
917 DMA_MEM_TO_DEV,
918 DMA_PREP_INTERRUPT |
919 DMA_CTRL_ACK);
920 if (!desc) {
921 dev_err(port->dev, "Failed to send via dma!\n");
922 return;
923 }
924
925 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
926
927 atmel_port->desc_tx = desc;
928 desc->callback = atmel_complete_tx_dma;
929 desc->callback_param = atmel_port;
930 atmel_port->cookie_tx = dmaengine_submit(desc);
931 if (dma_submit_error(atmel_port->cookie_tx)) {
932 dev_err(port->dev, "dma_submit_error %d\n",
933 atmel_port->cookie_tx);
934 return;
935 }
936
937 dma_async_issue_pending(chan);
938 }
939
940 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
941 uart_write_wakeup(port);
942 }
943
atmel_prepare_tx_dma(struct uart_port * port)944 static int atmel_prepare_tx_dma(struct uart_port *port)
945 {
946 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
947 dma_cap_mask_t mask;
948 struct dma_slave_config config;
949 int ret, nent;
950
951 dma_cap_zero(mask);
952 dma_cap_set(DMA_SLAVE, mask);
953
954 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
955 if (atmel_port->chan_tx == NULL)
956 goto chan_err;
957 dev_info(port->dev, "using %s for tx DMA transfers\n",
958 dma_chan_name(atmel_port->chan_tx));
959
960 spin_lock_init(&atmel_port->lock_tx);
961 sg_init_table(&atmel_port->sg_tx, 1);
962 /* UART circular tx buffer is an aligned page. */
963 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
964 sg_set_page(&atmel_port->sg_tx,
965 virt_to_page(port->state->xmit.buf),
966 UART_XMIT_SIZE,
967 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
968 nent = dma_map_sg(port->dev,
969 &atmel_port->sg_tx,
970 1,
971 DMA_TO_DEVICE);
972
973 if (!nent) {
974 dev_dbg(port->dev, "need to release resource of dma\n");
975 goto chan_err;
976 } else {
977 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
978 sg_dma_len(&atmel_port->sg_tx),
979 port->state->xmit.buf,
980 &sg_dma_address(&atmel_port->sg_tx));
981 }
982
983 /* Configure the slave DMA */
984 memset(&config, 0, sizeof(config));
985 config.direction = DMA_MEM_TO_DEV;
986 config.dst_addr_width = (atmel_port->fifo_size) ?
987 DMA_SLAVE_BUSWIDTH_4_BYTES :
988 DMA_SLAVE_BUSWIDTH_1_BYTE;
989 config.dst_addr = port->mapbase + ATMEL_US_THR;
990 config.dst_maxburst = 1;
991
992 ret = dmaengine_slave_config(atmel_port->chan_tx,
993 &config);
994 if (ret) {
995 dev_err(port->dev, "DMA tx slave configuration failed\n");
996 goto chan_err;
997 }
998
999 return 0;
1000
1001 chan_err:
1002 dev_err(port->dev, "TX channel not available, switch to pio\n");
1003 atmel_port->use_dma_tx = 0;
1004 if (atmel_port->chan_tx)
1005 atmel_release_tx_dma(port);
1006 return -EINVAL;
1007 }
1008
atmel_complete_rx_dma(void * arg)1009 static void atmel_complete_rx_dma(void *arg)
1010 {
1011 struct uart_port *port = arg;
1012 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1013
1014 tasklet_schedule(&atmel_port->tasklet);
1015 }
1016
atmel_release_rx_dma(struct uart_port * port)1017 static void atmel_release_rx_dma(struct uart_port *port)
1018 {
1019 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1020 struct dma_chan *chan = atmel_port->chan_rx;
1021
1022 if (chan) {
1023 dmaengine_terminate_all(chan);
1024 dma_release_channel(chan);
1025 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1026 DMA_FROM_DEVICE);
1027 }
1028
1029 atmel_port->desc_rx = NULL;
1030 atmel_port->chan_rx = NULL;
1031 atmel_port->cookie_rx = -EINVAL;
1032 }
1033
atmel_rx_from_dma(struct uart_port * port)1034 static void atmel_rx_from_dma(struct uart_port *port)
1035 {
1036 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1037 struct tty_port *tport = &port->state->port;
1038 struct circ_buf *ring = &atmel_port->rx_ring;
1039 struct dma_chan *chan = atmel_port->chan_rx;
1040 struct dma_tx_state state;
1041 enum dma_status dmastat;
1042 size_t count;
1043
1044
1045 /* Reset the UART timeout early so that we don't miss one */
1046 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1047 dmastat = dmaengine_tx_status(chan,
1048 atmel_port->cookie_rx,
1049 &state);
1050 /* Restart a new tasklet if DMA status is error */
1051 if (dmastat == DMA_ERROR) {
1052 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1053 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1054 tasklet_schedule(&atmel_port->tasklet);
1055 return;
1056 }
1057
1058 /* CPU claims ownership of RX DMA buffer */
1059 dma_sync_sg_for_cpu(port->dev,
1060 &atmel_port->sg_rx,
1061 1,
1062 DMA_FROM_DEVICE);
1063
1064 /*
1065 * ring->head points to the end of data already written by the DMA.
1066 * ring->tail points to the beginning of data to be read by the
1067 * framework.
1068 * The current transfer size should not be larger than the dma buffer
1069 * length.
1070 */
1071 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1072 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1073 /*
1074 * At this point ring->head may point to the first byte right after the
1075 * last byte of the dma buffer:
1076 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1077 *
1078 * However ring->tail must always points inside the dma buffer:
1079 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1080 *
1081 * Since we use a ring buffer, we have to handle the case
1082 * where head is lower than tail. In such a case, we first read from
1083 * tail to the end of the buffer then reset tail.
1084 */
1085 if (ring->head < ring->tail) {
1086 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1087
1088 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1089 ring->tail = 0;
1090 port->icount.rx += count;
1091 }
1092
1093 /* Finally we read data from tail to head */
1094 if (ring->tail < ring->head) {
1095 count = ring->head - ring->tail;
1096
1097 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1098 /* Wrap ring->head if needed */
1099 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1100 ring->head = 0;
1101 ring->tail = ring->head;
1102 port->icount.rx += count;
1103 }
1104
1105 /* USART retreives ownership of RX DMA buffer */
1106 dma_sync_sg_for_device(port->dev,
1107 &atmel_port->sg_rx,
1108 1,
1109 DMA_FROM_DEVICE);
1110
1111 /*
1112 * Drop the lock here since it might end up calling
1113 * uart_start(), which takes the lock.
1114 */
1115 spin_unlock(&port->lock);
1116 tty_flip_buffer_push(tport);
1117 spin_lock(&port->lock);
1118
1119 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1120 }
1121
atmel_prepare_rx_dma(struct uart_port * port)1122 static int atmel_prepare_rx_dma(struct uart_port *port)
1123 {
1124 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1125 struct dma_async_tx_descriptor *desc;
1126 dma_cap_mask_t mask;
1127 struct dma_slave_config config;
1128 struct circ_buf *ring;
1129 int ret, nent;
1130
1131 ring = &atmel_port->rx_ring;
1132
1133 dma_cap_zero(mask);
1134 dma_cap_set(DMA_CYCLIC, mask);
1135
1136 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1137 if (atmel_port->chan_rx == NULL)
1138 goto chan_err;
1139 dev_info(port->dev, "using %s for rx DMA transfers\n",
1140 dma_chan_name(atmel_port->chan_rx));
1141
1142 spin_lock_init(&atmel_port->lock_rx);
1143 sg_init_table(&atmel_port->sg_rx, 1);
1144 /* UART circular rx buffer is an aligned page. */
1145 BUG_ON(!PAGE_ALIGNED(ring->buf));
1146 sg_set_page(&atmel_port->sg_rx,
1147 virt_to_page(ring->buf),
1148 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1149 (unsigned long)ring->buf & ~PAGE_MASK);
1150 nent = dma_map_sg(port->dev,
1151 &atmel_port->sg_rx,
1152 1,
1153 DMA_FROM_DEVICE);
1154
1155 if (!nent) {
1156 dev_dbg(port->dev, "need to release resource of dma\n");
1157 goto chan_err;
1158 } else {
1159 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1160 sg_dma_len(&atmel_port->sg_rx),
1161 ring->buf,
1162 &sg_dma_address(&atmel_port->sg_rx));
1163 }
1164
1165 /* Configure the slave DMA */
1166 memset(&config, 0, sizeof(config));
1167 config.direction = DMA_DEV_TO_MEM;
1168 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1169 config.src_addr = port->mapbase + ATMEL_US_RHR;
1170 config.src_maxburst = 1;
1171
1172 ret = dmaengine_slave_config(atmel_port->chan_rx,
1173 &config);
1174 if (ret) {
1175 dev_err(port->dev, "DMA rx slave configuration failed\n");
1176 goto chan_err;
1177 }
1178 /*
1179 * Prepare a cyclic dma transfer, assign 2 descriptors,
1180 * each one is half ring buffer size
1181 */
1182 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1183 sg_dma_address(&atmel_port->sg_rx),
1184 sg_dma_len(&atmel_port->sg_rx),
1185 sg_dma_len(&atmel_port->sg_rx)/2,
1186 DMA_DEV_TO_MEM,
1187 DMA_PREP_INTERRUPT);
1188 if (!desc) {
1189 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1190 goto chan_err;
1191 }
1192 desc->callback = atmel_complete_rx_dma;
1193 desc->callback_param = port;
1194 atmel_port->desc_rx = desc;
1195 atmel_port->cookie_rx = dmaengine_submit(desc);
1196 if (dma_submit_error(atmel_port->cookie_rx)) {
1197 dev_err(port->dev, "dma_submit_error %d\n",
1198 atmel_port->cookie_rx);
1199 goto chan_err;
1200 }
1201
1202 dma_async_issue_pending(atmel_port->chan_rx);
1203
1204 return 0;
1205
1206 chan_err:
1207 dev_err(port->dev, "RX channel not available, switch to pio\n");
1208 atmel_port->use_dma_rx = 0;
1209 if (atmel_port->chan_rx)
1210 atmel_release_rx_dma(port);
1211 return -EINVAL;
1212 }
1213
atmel_uart_timer_callback(unsigned long data)1214 static void atmel_uart_timer_callback(unsigned long data)
1215 {
1216 struct uart_port *port = (void *)data;
1217 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1218
1219 tasklet_schedule(&atmel_port->tasklet);
1220 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1221 }
1222
1223 /*
1224 * receive interrupt handler.
1225 */
1226 static void
atmel_handle_receive(struct uart_port * port,unsigned int pending)1227 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1228 {
1229 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1230
1231 if (atmel_use_pdc_rx(port)) {
1232 /*
1233 * PDC receive. Just schedule the tasklet and let it
1234 * figure out the details.
1235 *
1236 * TODO: We're not handling error flags correctly at
1237 * the moment.
1238 */
1239 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1240 atmel_uart_writel(port, ATMEL_US_IDR,
1241 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1242 tasklet_schedule(&atmel_port->tasklet);
1243 }
1244
1245 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1246 ATMEL_US_FRAME | ATMEL_US_PARE))
1247 atmel_pdc_rxerr(port, pending);
1248 }
1249
1250 if (atmel_use_dma_rx(port)) {
1251 if (pending & ATMEL_US_TIMEOUT) {
1252 atmel_uart_writel(port, ATMEL_US_IDR,
1253 ATMEL_US_TIMEOUT);
1254 tasklet_schedule(&atmel_port->tasklet);
1255 }
1256 }
1257
1258 /* Interrupt receive */
1259 if (pending & ATMEL_US_RXRDY)
1260 atmel_rx_chars(port);
1261 else if (pending & ATMEL_US_RXBRK) {
1262 /*
1263 * End of break detected. If it came along with a
1264 * character, atmel_rx_chars will handle it.
1265 */
1266 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1267 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1268 atmel_port->break_active = 0;
1269 }
1270 }
1271
1272 /*
1273 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1274 */
1275 static void
atmel_handle_transmit(struct uart_port * port,unsigned int pending)1276 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1277 {
1278 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1279
1280 if (pending & atmel_port->tx_done_mask) {
1281 atmel_uart_writel(port, ATMEL_US_IDR,
1282 atmel_port->tx_done_mask);
1283
1284 /* Start RX if flag was set and FIFO is empty */
1285 if (atmel_port->hd_start_rx) {
1286 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1287 & ATMEL_US_TXEMPTY))
1288 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1289
1290 atmel_port->hd_start_rx = false;
1291 atmel_start_rx(port);
1292 }
1293
1294 tasklet_schedule(&atmel_port->tasklet);
1295 }
1296 }
1297
1298 /*
1299 * status flags interrupt handler.
1300 */
1301 static void
atmel_handle_status(struct uart_port * port,unsigned int pending,unsigned int status)1302 atmel_handle_status(struct uart_port *port, unsigned int pending,
1303 unsigned int status)
1304 {
1305 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1306
1307 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1308 | ATMEL_US_CTSIC)) {
1309 atmel_port->irq_status = status;
1310 atmel_port->status_change = atmel_port->irq_status ^
1311 atmel_port->irq_status_prev;
1312 atmel_port->irq_status_prev = status;
1313 tasklet_schedule(&atmel_port->tasklet);
1314 }
1315 }
1316
1317 /*
1318 * Interrupt handler
1319 */
atmel_interrupt(int irq,void * dev_id)1320 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1321 {
1322 struct uart_port *port = dev_id;
1323 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1324 unsigned int status, pending, mask, pass_counter = 0;
1325 bool gpio_handled = false;
1326
1327 spin_lock(&atmel_port->lock_suspended);
1328
1329 do {
1330 status = atmel_get_lines_status(port);
1331 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1332 pending = status & mask;
1333 if (!gpio_handled) {
1334 /*
1335 * Dealing with GPIO interrupt
1336 */
1337 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS])
1338 pending |= ATMEL_US_CTSIC;
1339
1340 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR])
1341 pending |= ATMEL_US_DSRIC;
1342
1343 if (irq == atmel_port->gpio_irq[UART_GPIO_RI])
1344 pending |= ATMEL_US_RIIC;
1345
1346 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD])
1347 pending |= ATMEL_US_DCDIC;
1348
1349 gpio_handled = true;
1350 }
1351 if (!pending)
1352 break;
1353
1354 if (atmel_port->suspended) {
1355 atmel_port->pending |= pending;
1356 atmel_port->pending_status = status;
1357 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1358 pm_system_wakeup();
1359 break;
1360 }
1361
1362 atmel_handle_receive(port, pending);
1363 atmel_handle_status(port, pending, status);
1364 atmel_handle_transmit(port, pending);
1365 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1366
1367 spin_unlock(&atmel_port->lock_suspended);
1368
1369 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1370 }
1371
atmel_release_tx_pdc(struct uart_port * port)1372 static void atmel_release_tx_pdc(struct uart_port *port)
1373 {
1374 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1375 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1376
1377 dma_unmap_single(port->dev,
1378 pdc->dma_addr,
1379 pdc->dma_size,
1380 DMA_TO_DEVICE);
1381 }
1382
1383 /*
1384 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1385 */
atmel_tx_pdc(struct uart_port * port)1386 static void atmel_tx_pdc(struct uart_port *port)
1387 {
1388 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1389 struct circ_buf *xmit = &port->state->xmit;
1390 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1391 int count;
1392
1393 /* nothing left to transmit? */
1394 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1395 return;
1396
1397 xmit->tail += pdc->ofs;
1398 xmit->tail &= UART_XMIT_SIZE - 1;
1399
1400 port->icount.tx += pdc->ofs;
1401 pdc->ofs = 0;
1402
1403 /* more to transmit - setup next transfer */
1404
1405 /* disable PDC transmit */
1406 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1407
1408 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1409 dma_sync_single_for_device(port->dev,
1410 pdc->dma_addr,
1411 pdc->dma_size,
1412 DMA_TO_DEVICE);
1413
1414 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1415 pdc->ofs = count;
1416
1417 atmel_uart_writel(port, ATMEL_PDC_TPR,
1418 pdc->dma_addr + xmit->tail);
1419 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1420 /* re-enable PDC transmit */
1421 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1422 /* Enable interrupts */
1423 atmel_uart_writel(port, ATMEL_US_IER,
1424 atmel_port->tx_done_mask);
1425 } else {
1426 if (atmel_uart_is_half_duplex(port)) {
1427 /* DMA done, stop TX, start RX for RS485 */
1428 atmel_start_rx(port);
1429 }
1430 }
1431
1432 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1433 uart_write_wakeup(port);
1434 }
1435
atmel_prepare_tx_pdc(struct uart_port * port)1436 static int atmel_prepare_tx_pdc(struct uart_port *port)
1437 {
1438 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1439 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1440 struct circ_buf *xmit = &port->state->xmit;
1441
1442 pdc->buf = xmit->buf;
1443 pdc->dma_addr = dma_map_single(port->dev,
1444 pdc->buf,
1445 UART_XMIT_SIZE,
1446 DMA_TO_DEVICE);
1447 pdc->dma_size = UART_XMIT_SIZE;
1448 pdc->ofs = 0;
1449
1450 return 0;
1451 }
1452
atmel_rx_from_ring(struct uart_port * port)1453 static void atmel_rx_from_ring(struct uart_port *port)
1454 {
1455 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1456 struct circ_buf *ring = &atmel_port->rx_ring;
1457 unsigned int flg;
1458 unsigned int status;
1459
1460 while (ring->head != ring->tail) {
1461 struct atmel_uart_char c;
1462
1463 /* Make sure c is loaded after head. */
1464 smp_rmb();
1465
1466 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1467
1468 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1469
1470 port->icount.rx++;
1471 status = c.status;
1472 flg = TTY_NORMAL;
1473
1474 /*
1475 * note that the error handling code is
1476 * out of the main execution path
1477 */
1478 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1479 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1480 if (status & ATMEL_US_RXBRK) {
1481 /* ignore side-effect */
1482 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1483
1484 port->icount.brk++;
1485 if (uart_handle_break(port))
1486 continue;
1487 }
1488 if (status & ATMEL_US_PARE)
1489 port->icount.parity++;
1490 if (status & ATMEL_US_FRAME)
1491 port->icount.frame++;
1492 if (status & ATMEL_US_OVRE)
1493 port->icount.overrun++;
1494
1495 status &= port->read_status_mask;
1496
1497 if (status & ATMEL_US_RXBRK)
1498 flg = TTY_BREAK;
1499 else if (status & ATMEL_US_PARE)
1500 flg = TTY_PARITY;
1501 else if (status & ATMEL_US_FRAME)
1502 flg = TTY_FRAME;
1503 }
1504
1505
1506 if (uart_handle_sysrq_char(port, c.ch))
1507 continue;
1508
1509 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1510 }
1511
1512 /*
1513 * Drop the lock here since it might end up calling
1514 * uart_start(), which takes the lock.
1515 */
1516 spin_unlock(&port->lock);
1517 tty_flip_buffer_push(&port->state->port);
1518 spin_lock(&port->lock);
1519 }
1520
atmel_release_rx_pdc(struct uart_port * port)1521 static void atmel_release_rx_pdc(struct uart_port *port)
1522 {
1523 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1524 int i;
1525
1526 for (i = 0; i < 2; i++) {
1527 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1528
1529 dma_unmap_single(port->dev,
1530 pdc->dma_addr,
1531 pdc->dma_size,
1532 DMA_FROM_DEVICE);
1533 kfree(pdc->buf);
1534 }
1535 }
1536
atmel_rx_from_pdc(struct uart_port * port)1537 static void atmel_rx_from_pdc(struct uart_port *port)
1538 {
1539 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1540 struct tty_port *tport = &port->state->port;
1541 struct atmel_dma_buffer *pdc;
1542 int rx_idx = atmel_port->pdc_rx_idx;
1543 unsigned int head;
1544 unsigned int tail;
1545 unsigned int count;
1546
1547 do {
1548 /* Reset the UART timeout early so that we don't miss one */
1549 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1550
1551 pdc = &atmel_port->pdc_rx[rx_idx];
1552 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1553 tail = pdc->ofs;
1554
1555 /* If the PDC has switched buffers, RPR won't contain
1556 * any address within the current buffer. Since head
1557 * is unsigned, we just need a one-way comparison to
1558 * find out.
1559 *
1560 * In this case, we just need to consume the entire
1561 * buffer and resubmit it for DMA. This will clear the
1562 * ENDRX bit as well, so that we can safely re-enable
1563 * all interrupts below.
1564 */
1565 head = min(head, pdc->dma_size);
1566
1567 if (likely(head != tail)) {
1568 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1569 pdc->dma_size, DMA_FROM_DEVICE);
1570
1571 /*
1572 * head will only wrap around when we recycle
1573 * the DMA buffer, and when that happens, we
1574 * explicitly set tail to 0. So head will
1575 * always be greater than tail.
1576 */
1577 count = head - tail;
1578
1579 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1580 count);
1581
1582 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1583 pdc->dma_size, DMA_FROM_DEVICE);
1584
1585 port->icount.rx += count;
1586 pdc->ofs = head;
1587 }
1588
1589 /*
1590 * If the current buffer is full, we need to check if
1591 * the next one contains any additional data.
1592 */
1593 if (head >= pdc->dma_size) {
1594 pdc->ofs = 0;
1595 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1596 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1597
1598 rx_idx = !rx_idx;
1599 atmel_port->pdc_rx_idx = rx_idx;
1600 }
1601 } while (head >= pdc->dma_size);
1602
1603 /*
1604 * Drop the lock here since it might end up calling
1605 * uart_start(), which takes the lock.
1606 */
1607 spin_unlock(&port->lock);
1608 tty_flip_buffer_push(tport);
1609 spin_lock(&port->lock);
1610
1611 atmel_uart_writel(port, ATMEL_US_IER,
1612 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1613 }
1614
atmel_prepare_rx_pdc(struct uart_port * port)1615 static int atmel_prepare_rx_pdc(struct uart_port *port)
1616 {
1617 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1618 int i;
1619
1620 for (i = 0; i < 2; i++) {
1621 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1622
1623 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1624 if (pdc->buf == NULL) {
1625 if (i != 0) {
1626 dma_unmap_single(port->dev,
1627 atmel_port->pdc_rx[0].dma_addr,
1628 PDC_BUFFER_SIZE,
1629 DMA_FROM_DEVICE);
1630 kfree(atmel_port->pdc_rx[0].buf);
1631 }
1632 atmel_port->use_pdc_rx = 0;
1633 return -ENOMEM;
1634 }
1635 pdc->dma_addr = dma_map_single(port->dev,
1636 pdc->buf,
1637 PDC_BUFFER_SIZE,
1638 DMA_FROM_DEVICE);
1639 pdc->dma_size = PDC_BUFFER_SIZE;
1640 pdc->ofs = 0;
1641 }
1642
1643 atmel_port->pdc_rx_idx = 0;
1644
1645 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1646 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1647
1648 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1649 atmel_port->pdc_rx[1].dma_addr);
1650 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1651
1652 return 0;
1653 }
1654
1655 /*
1656 * tasklet handling tty stuff outside the interrupt handler.
1657 */
atmel_tasklet_func(unsigned long data)1658 static void atmel_tasklet_func(unsigned long data)
1659 {
1660 struct uart_port *port = (struct uart_port *)data;
1661 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1662 unsigned int status = atmel_port->irq_status;
1663 unsigned int status_change = atmel_port->status_change;
1664
1665 /* The interrupt handler does not take the lock */
1666 spin_lock(&port->lock);
1667
1668 atmel_port->schedule_tx(port);
1669
1670 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1671 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1672 /* TODO: All reads to CSR will clear these interrupts! */
1673 if (status_change & ATMEL_US_RI)
1674 port->icount.rng++;
1675 if (status_change & ATMEL_US_DSR)
1676 port->icount.dsr++;
1677 if (status_change & ATMEL_US_DCD)
1678 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1679 if (status_change & ATMEL_US_CTS)
1680 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1681
1682 wake_up_interruptible(&port->state->port.delta_msr_wait);
1683
1684 atmel_port->status_change = 0;
1685 }
1686
1687 atmel_port->schedule_rx(port);
1688
1689 spin_unlock(&port->lock);
1690 }
1691
atmel_init_property(struct atmel_uart_port * atmel_port,struct platform_device * pdev)1692 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1693 struct platform_device *pdev)
1694 {
1695 struct device_node *np = pdev->dev.of_node;
1696 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1697
1698 if (np) {
1699 /* DMA/PDC usage specification */
1700 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1701 if (of_get_property(np, "dmas", NULL)) {
1702 atmel_port->use_dma_rx = true;
1703 atmel_port->use_pdc_rx = false;
1704 } else {
1705 atmel_port->use_dma_rx = false;
1706 atmel_port->use_pdc_rx = true;
1707 }
1708 } else {
1709 atmel_port->use_dma_rx = false;
1710 atmel_port->use_pdc_rx = false;
1711 }
1712
1713 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1714 if (of_get_property(np, "dmas", NULL)) {
1715 atmel_port->use_dma_tx = true;
1716 atmel_port->use_pdc_tx = false;
1717 } else {
1718 atmel_port->use_dma_tx = false;
1719 atmel_port->use_pdc_tx = true;
1720 }
1721 } else {
1722 atmel_port->use_dma_tx = false;
1723 atmel_port->use_pdc_tx = false;
1724 }
1725
1726 } else {
1727 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1728 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1729 atmel_port->use_dma_rx = false;
1730 atmel_port->use_dma_tx = false;
1731 }
1732
1733 }
1734
atmel_init_rs485(struct uart_port * port,struct platform_device * pdev)1735 static void atmel_init_rs485(struct uart_port *port,
1736 struct platform_device *pdev)
1737 {
1738 struct device_node *np = pdev->dev.of_node;
1739 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1740
1741 if (np) {
1742 struct serial_rs485 *rs485conf = &port->rs485;
1743 u32 rs485_delay[2];
1744 /* rs485 properties */
1745 if (of_property_read_u32_array(np, "rs485-rts-delay",
1746 rs485_delay, 2) == 0) {
1747 rs485conf->delay_rts_before_send = rs485_delay[0];
1748 rs485conf->delay_rts_after_send = rs485_delay[1];
1749 rs485conf->flags = 0;
1750 }
1751
1752 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1753 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1754
1755 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1756 NULL))
1757 rs485conf->flags |= SER_RS485_ENABLED;
1758 } else {
1759 port->rs485 = pdata->rs485;
1760 }
1761
1762 }
1763
atmel_set_ops(struct uart_port * port)1764 static void atmel_set_ops(struct uart_port *port)
1765 {
1766 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1767
1768 if (atmel_use_dma_rx(port)) {
1769 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1770 atmel_port->schedule_rx = &atmel_rx_from_dma;
1771 atmel_port->release_rx = &atmel_release_rx_dma;
1772 } else if (atmel_use_pdc_rx(port)) {
1773 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1774 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1775 atmel_port->release_rx = &atmel_release_rx_pdc;
1776 } else {
1777 atmel_port->prepare_rx = NULL;
1778 atmel_port->schedule_rx = &atmel_rx_from_ring;
1779 atmel_port->release_rx = NULL;
1780 }
1781
1782 if (atmel_use_dma_tx(port)) {
1783 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1784 atmel_port->schedule_tx = &atmel_tx_dma;
1785 atmel_port->release_tx = &atmel_release_tx_dma;
1786 } else if (atmel_use_pdc_tx(port)) {
1787 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1788 atmel_port->schedule_tx = &atmel_tx_pdc;
1789 atmel_port->release_tx = &atmel_release_tx_pdc;
1790 } else {
1791 atmel_port->prepare_tx = NULL;
1792 atmel_port->schedule_tx = &atmel_tx_chars;
1793 atmel_port->release_tx = NULL;
1794 }
1795 }
1796
1797 /*
1798 * Get ip name usart or uart
1799 */
atmel_get_ip_name(struct uart_port * port)1800 static void atmel_get_ip_name(struct uart_port *port)
1801 {
1802 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1803 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1804 u32 version;
1805 int usart, uart;
1806 /* usart and uart ascii */
1807 usart = 0x55534152;
1808 uart = 0x44424755;
1809
1810 atmel_port->is_usart = false;
1811
1812 if (name == usart) {
1813 dev_dbg(port->dev, "This is usart\n");
1814 atmel_port->is_usart = true;
1815 } else if (name == uart) {
1816 dev_dbg(port->dev, "This is uart\n");
1817 atmel_port->is_usart = false;
1818 } else {
1819 /* fallback for older SoCs: use version field */
1820 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1821 switch (version) {
1822 case 0x302:
1823 case 0x10213:
1824 case 0x10302:
1825 dev_dbg(port->dev, "This version is usart\n");
1826 atmel_port->is_usart = true;
1827 break;
1828 case 0x203:
1829 case 0x10202:
1830 dev_dbg(port->dev, "This version is uart\n");
1831 atmel_port->is_usart = false;
1832 break;
1833 default:
1834 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1835 }
1836 }
1837 }
1838
atmel_free_gpio_irq(struct uart_port * port)1839 static void atmel_free_gpio_irq(struct uart_port *port)
1840 {
1841 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1842 enum mctrl_gpio_idx i;
1843
1844 for (i = 0; i < UART_GPIO_MAX; i++)
1845 if (atmel_port->gpio_irq[i] >= 0)
1846 free_irq(atmel_port->gpio_irq[i], port);
1847 }
1848
atmel_request_gpio_irq(struct uart_port * port)1849 static int atmel_request_gpio_irq(struct uart_port *port)
1850 {
1851 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1852 int *irq = atmel_port->gpio_irq;
1853 enum mctrl_gpio_idx i;
1854 int err = 0;
1855
1856 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1857 if (irq[i] < 0)
1858 continue;
1859
1860 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1861 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH,
1862 "atmel_serial", port);
1863 if (err)
1864 dev_err(port->dev, "atmel_startup - Can't get %d irq\n",
1865 irq[i]);
1866 }
1867
1868 /*
1869 * If something went wrong, rollback.
1870 */
1871 while (err && (--i >= 0))
1872 if (irq[i] >= 0)
1873 free_irq(irq[i], port);
1874
1875 return err;
1876 }
1877
1878 /*
1879 * Perform initialization and enable port for reception
1880 */
atmel_startup(struct uart_port * port)1881 static int atmel_startup(struct uart_port *port)
1882 {
1883 struct platform_device *pdev = to_platform_device(port->dev);
1884 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1885 struct tty_struct *tty = port->state->port.tty;
1886 int retval;
1887
1888 /*
1889 * Ensure that no interrupts are enabled otherwise when
1890 * request_irq() is called we could get stuck trying to
1891 * handle an unexpected interrupt
1892 */
1893 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1894 atmel_port->ms_irq_enabled = false;
1895
1896 /*
1897 * Allocate the IRQ
1898 */
1899 retval = request_irq(port->irq, atmel_interrupt,
1900 IRQF_SHARED | IRQF_COND_SUSPEND,
1901 tty ? tty->name : "atmel_serial", port);
1902 if (retval) {
1903 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1904 return retval;
1905 }
1906
1907 /*
1908 * Get the GPIO lines IRQ
1909 */
1910 retval = atmel_request_gpio_irq(port);
1911 if (retval)
1912 goto free_irq;
1913
1914 tasklet_enable(&atmel_port->tasklet);
1915
1916 /*
1917 * Initialize DMA (if necessary)
1918 */
1919 atmel_init_property(atmel_port, pdev);
1920 atmel_set_ops(port);
1921
1922 if (atmel_port->prepare_rx) {
1923 retval = atmel_port->prepare_rx(port);
1924 if (retval < 0)
1925 atmel_set_ops(port);
1926 }
1927
1928 if (atmel_port->prepare_tx) {
1929 retval = atmel_port->prepare_tx(port);
1930 if (retval < 0)
1931 atmel_set_ops(port);
1932 }
1933
1934 /*
1935 * Enable FIFO when available
1936 */
1937 if (atmel_port->fifo_size) {
1938 unsigned int txrdym = ATMEL_US_ONE_DATA;
1939 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1940 unsigned int fmr;
1941
1942 atmel_uart_writel(port, ATMEL_US_CR,
1943 ATMEL_US_FIFOEN |
1944 ATMEL_US_RXFCLR |
1945 ATMEL_US_TXFLCLR);
1946
1947 if (atmel_use_dma_tx(port))
1948 txrdym = ATMEL_US_FOUR_DATA;
1949
1950 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1951 if (atmel_port->rts_high &&
1952 atmel_port->rts_low)
1953 fmr |= ATMEL_US_FRTSC |
1954 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1955 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1956
1957 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1958 }
1959
1960 /* Save current CSR for comparison in atmel_tasklet_func() */
1961 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1962 atmel_port->irq_status = atmel_port->irq_status_prev;
1963
1964 /*
1965 * Finally, enable the serial port
1966 */
1967 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1968 /* enable xmit & rcvr */
1969 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1970
1971 setup_timer(&atmel_port->uart_timer,
1972 atmel_uart_timer_callback,
1973 (unsigned long)port);
1974
1975 if (atmel_use_pdc_rx(port)) {
1976 /* set UART timeout */
1977 if (!atmel_port->is_usart) {
1978 mod_timer(&atmel_port->uart_timer,
1979 jiffies + uart_poll_timeout(port));
1980 /* set USART timeout */
1981 } else {
1982 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1983 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1984
1985 atmel_uart_writel(port, ATMEL_US_IER,
1986 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1987 }
1988 /* enable PDC controller */
1989 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1990 } else if (atmel_use_dma_rx(port)) {
1991 /* set UART timeout */
1992 if (!atmel_port->is_usart) {
1993 mod_timer(&atmel_port->uart_timer,
1994 jiffies + uart_poll_timeout(port));
1995 /* set USART timeout */
1996 } else {
1997 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1998 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1999
2000 atmel_uart_writel(port, ATMEL_US_IER,
2001 ATMEL_US_TIMEOUT);
2002 }
2003 } else {
2004 /* enable receive only */
2005 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2006 }
2007
2008 return 0;
2009
2010 free_irq:
2011 free_irq(port->irq, port);
2012
2013 return retval;
2014 }
2015
2016 /*
2017 * Flush any TX data submitted for DMA. Called when the TX circular
2018 * buffer is reset.
2019 */
atmel_flush_buffer(struct uart_port * port)2020 static void atmel_flush_buffer(struct uart_port *port)
2021 {
2022 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2023
2024 if (atmel_use_pdc_tx(port)) {
2025 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2026 atmel_port->pdc_tx.ofs = 0;
2027 }
2028 /*
2029 * in uart_flush_buffer(), the xmit circular buffer has just
2030 * been cleared, so we have to reset tx_len accordingly.
2031 */
2032 atmel_port->tx_len = 0;
2033 }
2034
2035 /*
2036 * Disable the port
2037 */
atmel_shutdown(struct uart_port * port)2038 static void atmel_shutdown(struct uart_port *port)
2039 {
2040 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2041
2042 /*
2043 * Prevent any tasklets being scheduled during
2044 * cleanup
2045 */
2046 del_timer_sync(&atmel_port->uart_timer);
2047
2048 /*
2049 * Clear out any scheduled tasklets before
2050 * we destroy the buffers
2051 */
2052 tasklet_disable(&atmel_port->tasklet);
2053 tasklet_kill(&atmel_port->tasklet);
2054
2055 /*
2056 * Ensure everything is stopped and
2057 * disable all interrupts, port and break condition.
2058 */
2059 atmel_stop_rx(port);
2060 atmel_stop_tx(port);
2061
2062 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2063 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2064
2065
2066 /*
2067 * Shut-down the DMA.
2068 */
2069 if (atmel_port->release_rx)
2070 atmel_port->release_rx(port);
2071 if (atmel_port->release_tx)
2072 atmel_port->release_tx(port);
2073
2074 /*
2075 * Reset ring buffer pointers
2076 */
2077 atmel_port->rx_ring.head = 0;
2078 atmel_port->rx_ring.tail = 0;
2079
2080 /*
2081 * Free the interrupts
2082 */
2083 free_irq(port->irq, port);
2084 atmel_free_gpio_irq(port);
2085
2086 atmel_port->ms_irq_enabled = false;
2087
2088 atmel_flush_buffer(port);
2089 }
2090
2091 /*
2092 * Power / Clock management.
2093 */
atmel_serial_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2094 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2095 unsigned int oldstate)
2096 {
2097 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2098
2099 switch (state) {
2100 case 0:
2101 /*
2102 * Enable the peripheral clock for this serial port.
2103 * This is called on uart_open() or a resume event.
2104 */
2105 clk_prepare_enable(atmel_port->clk);
2106
2107 /* re-enable interrupts if we disabled some on suspend */
2108 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2109 break;
2110 case 3:
2111 /* Back up the interrupt mask and disable all interrupts */
2112 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2113 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2114
2115 /*
2116 * Disable the peripheral clock for this serial port.
2117 * This is called on uart_close() or a suspend event.
2118 */
2119 clk_disable_unprepare(atmel_port->clk);
2120 break;
2121 default:
2122 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2123 }
2124 }
2125
2126 /*
2127 * Change the port parameters
2128 */
atmel_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)2129 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2130 struct ktermios *old)
2131 {
2132 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2133 unsigned long flags;
2134 unsigned int old_mode, mode, imr, quot, baud;
2135
2136 /* save the current mode register */
2137 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2138
2139 /* reset the mode, clock divisor, parity, stop bits and data size */
2140 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2141 ATMEL_US_PAR | ATMEL_US_USMODE);
2142
2143 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2144 quot = uart_get_divisor(port, baud);
2145
2146 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2147 quot /= 8;
2148 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2149 }
2150
2151 /* byte size */
2152 switch (termios->c_cflag & CSIZE) {
2153 case CS5:
2154 mode |= ATMEL_US_CHRL_5;
2155 break;
2156 case CS6:
2157 mode |= ATMEL_US_CHRL_6;
2158 break;
2159 case CS7:
2160 mode |= ATMEL_US_CHRL_7;
2161 break;
2162 default:
2163 mode |= ATMEL_US_CHRL_8;
2164 break;
2165 }
2166
2167 /* stop bits */
2168 if (termios->c_cflag & CSTOPB)
2169 mode |= ATMEL_US_NBSTOP_2;
2170
2171 /* parity */
2172 if (termios->c_cflag & PARENB) {
2173 /* Mark or Space parity */
2174 if (termios->c_cflag & CMSPAR) {
2175 if (termios->c_cflag & PARODD)
2176 mode |= ATMEL_US_PAR_MARK;
2177 else
2178 mode |= ATMEL_US_PAR_SPACE;
2179 } else if (termios->c_cflag & PARODD)
2180 mode |= ATMEL_US_PAR_ODD;
2181 else
2182 mode |= ATMEL_US_PAR_EVEN;
2183 } else
2184 mode |= ATMEL_US_PAR_NONE;
2185
2186 spin_lock_irqsave(&port->lock, flags);
2187
2188 port->read_status_mask = ATMEL_US_OVRE;
2189 if (termios->c_iflag & INPCK)
2190 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2191 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2192 port->read_status_mask |= ATMEL_US_RXBRK;
2193
2194 if (atmel_use_pdc_rx(port))
2195 /* need to enable error interrupts */
2196 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2197
2198 /*
2199 * Characters to ignore
2200 */
2201 port->ignore_status_mask = 0;
2202 if (termios->c_iflag & IGNPAR)
2203 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2204 if (termios->c_iflag & IGNBRK) {
2205 port->ignore_status_mask |= ATMEL_US_RXBRK;
2206 /*
2207 * If we're ignoring parity and break indicators,
2208 * ignore overruns too (for real raw support).
2209 */
2210 if (termios->c_iflag & IGNPAR)
2211 port->ignore_status_mask |= ATMEL_US_OVRE;
2212 }
2213 /* TODO: Ignore all characters if CREAD is set.*/
2214
2215 /* update the per-port timeout */
2216 uart_update_timeout(port, termios->c_cflag, baud);
2217
2218 /*
2219 * save/disable interrupts. The tty layer will ensure that the
2220 * transmitter is empty if requested by the caller, so there's
2221 * no need to wait for it here.
2222 */
2223 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2224 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2225
2226 /* disable receiver and transmitter */
2227 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2228
2229 /* mode */
2230 if (port->rs485.flags & SER_RS485_ENABLED) {
2231 atmel_uart_writel(port, ATMEL_US_TTGR,
2232 port->rs485.delay_rts_after_send);
2233 mode |= ATMEL_US_USMODE_RS485;
2234 } else if (termios->c_cflag & CRTSCTS) {
2235 /* RS232 with hardware handshake (RTS/CTS) */
2236 if (atmel_use_fifo(port) &&
2237 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2238 /*
2239 * with ATMEL_US_USMODE_HWHS set, the controller will
2240 * be able to drive the RTS pin high/low when the RX
2241 * FIFO is above RXFTHRES/below RXFTHRES2.
2242 * It will also disable the transmitter when the CTS
2243 * pin is high.
2244 * This mode is not activated if CTS pin is a GPIO
2245 * because in this case, the transmitter is always
2246 * disabled (there must be an internal pull-up
2247 * responsible for this behaviour).
2248 * If the RTS pin is a GPIO, the controller won't be
2249 * able to drive it according to the FIFO thresholds,
2250 * but it will be handled by the driver.
2251 */
2252 mode |= ATMEL_US_USMODE_HWHS;
2253 } else {
2254 /*
2255 * For platforms without FIFO, the flow control is
2256 * handled by the driver.
2257 */
2258 mode |= ATMEL_US_USMODE_NORMAL;
2259 }
2260 } else {
2261 /* RS232 without hadware handshake */
2262 mode |= ATMEL_US_USMODE_NORMAL;
2263 }
2264
2265 /* set the mode, clock divisor, parity, stop bits and data size */
2266 atmel_uart_writel(port, ATMEL_US_MR, mode);
2267
2268 /*
2269 * when switching the mode, set the RTS line state according to the
2270 * new mode, otherwise keep the former state
2271 */
2272 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2273 unsigned int rts_state;
2274
2275 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2276 /* let the hardware control the RTS line */
2277 rts_state = ATMEL_US_RTSDIS;
2278 } else {
2279 /* force RTS line to low level */
2280 rts_state = ATMEL_US_RTSEN;
2281 }
2282
2283 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2284 }
2285
2286 /* set the baud rate */
2287 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2288 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2289 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2290
2291 /* restore interrupts */
2292 atmel_uart_writel(port, ATMEL_US_IER, imr);
2293
2294 /* CTS flow-control and modem-status interrupts */
2295 if (UART_ENABLE_MS(port, termios->c_cflag))
2296 atmel_enable_ms(port);
2297 else
2298 atmel_disable_ms(port);
2299
2300 spin_unlock_irqrestore(&port->lock, flags);
2301 }
2302
atmel_set_ldisc(struct uart_port * port,struct ktermios * termios)2303 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2304 {
2305 if (termios->c_line == N_PPS) {
2306 port->flags |= UPF_HARDPPS_CD;
2307 spin_lock_irq(&port->lock);
2308 atmel_enable_ms(port);
2309 spin_unlock_irq(&port->lock);
2310 } else {
2311 port->flags &= ~UPF_HARDPPS_CD;
2312 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2313 spin_lock_irq(&port->lock);
2314 atmel_disable_ms(port);
2315 spin_unlock_irq(&port->lock);
2316 }
2317 }
2318 }
2319
2320 /*
2321 * Return string describing the specified port
2322 */
atmel_type(struct uart_port * port)2323 static const char *atmel_type(struct uart_port *port)
2324 {
2325 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2326 }
2327
2328 /*
2329 * Release the memory region(s) being used by 'port'.
2330 */
atmel_release_port(struct uart_port * port)2331 static void atmel_release_port(struct uart_port *port)
2332 {
2333 struct platform_device *pdev = to_platform_device(port->dev);
2334 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2335
2336 release_mem_region(port->mapbase, size);
2337
2338 if (port->flags & UPF_IOREMAP) {
2339 iounmap(port->membase);
2340 port->membase = NULL;
2341 }
2342 }
2343
2344 /*
2345 * Request the memory region(s) being used by 'port'.
2346 */
atmel_request_port(struct uart_port * port)2347 static int atmel_request_port(struct uart_port *port)
2348 {
2349 struct platform_device *pdev = to_platform_device(port->dev);
2350 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2351
2352 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2353 return -EBUSY;
2354
2355 if (port->flags & UPF_IOREMAP) {
2356 port->membase = ioremap(port->mapbase, size);
2357 if (port->membase == NULL) {
2358 release_mem_region(port->mapbase, size);
2359 return -ENOMEM;
2360 }
2361 }
2362
2363 return 0;
2364 }
2365
2366 /*
2367 * Configure/autoconfigure the port.
2368 */
atmel_config_port(struct uart_port * port,int flags)2369 static void atmel_config_port(struct uart_port *port, int flags)
2370 {
2371 if (flags & UART_CONFIG_TYPE) {
2372 port->type = PORT_ATMEL;
2373 atmel_request_port(port);
2374 }
2375 }
2376
2377 /*
2378 * Verify the new serial_struct (for TIOCSSERIAL).
2379 */
atmel_verify_port(struct uart_port * port,struct serial_struct * ser)2380 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2381 {
2382 int ret = 0;
2383 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2384 ret = -EINVAL;
2385 if (port->irq != ser->irq)
2386 ret = -EINVAL;
2387 if (ser->io_type != SERIAL_IO_MEM)
2388 ret = -EINVAL;
2389 if (port->uartclk / 16 != ser->baud_base)
2390 ret = -EINVAL;
2391 if (port->mapbase != (unsigned long)ser->iomem_base)
2392 ret = -EINVAL;
2393 if (port->iobase != ser->port)
2394 ret = -EINVAL;
2395 if (ser->hub6 != 0)
2396 ret = -EINVAL;
2397 return ret;
2398 }
2399
2400 #ifdef CONFIG_CONSOLE_POLL
atmel_poll_get_char(struct uart_port * port)2401 static int atmel_poll_get_char(struct uart_port *port)
2402 {
2403 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2404 cpu_relax();
2405
2406 return atmel_uart_read_char(port);
2407 }
2408
atmel_poll_put_char(struct uart_port * port,unsigned char ch)2409 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2410 {
2411 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2412 cpu_relax();
2413
2414 atmel_uart_write_char(port, ch);
2415 }
2416 #endif
2417
2418 static struct uart_ops atmel_pops = {
2419 .tx_empty = atmel_tx_empty,
2420 .set_mctrl = atmel_set_mctrl,
2421 .get_mctrl = atmel_get_mctrl,
2422 .stop_tx = atmel_stop_tx,
2423 .start_tx = atmel_start_tx,
2424 .stop_rx = atmel_stop_rx,
2425 .enable_ms = atmel_enable_ms,
2426 .break_ctl = atmel_break_ctl,
2427 .startup = atmel_startup,
2428 .shutdown = atmel_shutdown,
2429 .flush_buffer = atmel_flush_buffer,
2430 .set_termios = atmel_set_termios,
2431 .set_ldisc = atmel_set_ldisc,
2432 .type = atmel_type,
2433 .release_port = atmel_release_port,
2434 .request_port = atmel_request_port,
2435 .config_port = atmel_config_port,
2436 .verify_port = atmel_verify_port,
2437 .pm = atmel_serial_pm,
2438 #ifdef CONFIG_CONSOLE_POLL
2439 .poll_get_char = atmel_poll_get_char,
2440 .poll_put_char = atmel_poll_put_char,
2441 #endif
2442 };
2443
2444 /*
2445 * Configure the port from the platform device resource info.
2446 */
atmel_init_port(struct atmel_uart_port * atmel_port,struct platform_device * pdev)2447 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2448 struct platform_device *pdev)
2449 {
2450 int ret;
2451 struct uart_port *port = &atmel_port->uart;
2452 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2453
2454 atmel_init_property(atmel_port, pdev);
2455 atmel_set_ops(port);
2456
2457 atmel_init_rs485(port, pdev);
2458
2459 port->iotype = UPIO_MEM;
2460 port->flags = UPF_BOOT_AUTOCONF;
2461 port->ops = &atmel_pops;
2462 port->fifosize = 1;
2463 port->dev = &pdev->dev;
2464 port->mapbase = pdev->resource[0].start;
2465 port->irq = pdev->resource[1].start;
2466 port->rs485_config = atmel_config_rs485;
2467
2468 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2469 (unsigned long)port);
2470 tasklet_disable(&atmel_port->tasklet);
2471
2472 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2473
2474 if (pdata && pdata->regs) {
2475 /* Already mapped by setup code */
2476 port->membase = pdata->regs;
2477 } else {
2478 port->flags |= UPF_IOREMAP;
2479 port->membase = NULL;
2480 }
2481
2482 /* for console, the clock could already be configured */
2483 if (!atmel_port->clk) {
2484 atmel_port->clk = clk_get(&pdev->dev, "usart");
2485 if (IS_ERR(atmel_port->clk)) {
2486 ret = PTR_ERR(atmel_port->clk);
2487 atmel_port->clk = NULL;
2488 return ret;
2489 }
2490 ret = clk_prepare_enable(atmel_port->clk);
2491 if (ret) {
2492 clk_put(atmel_port->clk);
2493 atmel_port->clk = NULL;
2494 return ret;
2495 }
2496 port->uartclk = clk_get_rate(atmel_port->clk);
2497 clk_disable_unprepare(atmel_port->clk);
2498 /* only enable clock when USART is in use */
2499 }
2500
2501 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2502 if (port->rs485.flags & SER_RS485_ENABLED)
2503 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2504 else if (atmel_use_pdc_tx(port)) {
2505 port->fifosize = PDC_BUFFER_SIZE;
2506 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2507 } else {
2508 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2509 }
2510
2511 return 0;
2512 }
2513
2514 struct platform_device *atmel_default_console_device; /* the serial console device */
2515
2516 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
atmel_console_putchar(struct uart_port * port,int ch)2517 static void atmel_console_putchar(struct uart_port *port, int ch)
2518 {
2519 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2520 cpu_relax();
2521 atmel_uart_write_char(port, ch);
2522 }
2523
2524 /*
2525 * Interrupts are disabled on entering
2526 */
atmel_console_write(struct console * co,const char * s,u_int count)2527 static void atmel_console_write(struct console *co, const char *s, u_int count)
2528 {
2529 struct uart_port *port = &atmel_ports[co->index].uart;
2530 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2531 unsigned int status, imr;
2532 unsigned int pdc_tx;
2533
2534 /*
2535 * First, save IMR and then disable interrupts
2536 */
2537 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2538 atmel_uart_writel(port, ATMEL_US_IDR,
2539 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2540
2541 /* Store PDC transmit status and disable it */
2542 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2543 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2544
2545 /* Make sure that tx path is actually able to send characters */
2546 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2547
2548 uart_console_write(port, s, count, atmel_console_putchar);
2549
2550 /*
2551 * Finally, wait for transmitter to become empty
2552 * and restore IMR
2553 */
2554 do {
2555 status = atmel_uart_readl(port, ATMEL_US_CSR);
2556 } while (!(status & ATMEL_US_TXRDY));
2557
2558 /* Restore PDC transmit status */
2559 if (pdc_tx)
2560 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2561
2562 /* set interrupts back the way they were */
2563 atmel_uart_writel(port, ATMEL_US_IER, imr);
2564 }
2565
2566 /*
2567 * If the port was already initialised (eg, by a boot loader),
2568 * try to determine the current setup.
2569 */
atmel_console_get_options(struct uart_port * port,int * baud,int * parity,int * bits)2570 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2571 int *parity, int *bits)
2572 {
2573 unsigned int mr, quot;
2574
2575 /*
2576 * If the baud rate generator isn't running, the port wasn't
2577 * initialized by the boot loader.
2578 */
2579 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2580 if (!quot)
2581 return;
2582
2583 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2584 if (mr == ATMEL_US_CHRL_8)
2585 *bits = 8;
2586 else
2587 *bits = 7;
2588
2589 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2590 if (mr == ATMEL_US_PAR_EVEN)
2591 *parity = 'e';
2592 else if (mr == ATMEL_US_PAR_ODD)
2593 *parity = 'o';
2594
2595 /*
2596 * The serial core only rounds down when matching this to a
2597 * supported baud rate. Make sure we don't end up slightly
2598 * lower than one of those, as it would make us fall through
2599 * to a much lower baud rate than we really want.
2600 */
2601 *baud = port->uartclk / (16 * (quot - 1));
2602 }
2603
atmel_console_setup(struct console * co,char * options)2604 static int __init atmel_console_setup(struct console *co, char *options)
2605 {
2606 int ret;
2607 struct uart_port *port = &atmel_ports[co->index].uart;
2608 int baud = 115200;
2609 int bits = 8;
2610 int parity = 'n';
2611 int flow = 'n';
2612
2613 if (port->membase == NULL) {
2614 /* Port not initialized yet - delay setup */
2615 return -ENODEV;
2616 }
2617
2618 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2619 if (ret)
2620 return ret;
2621
2622 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2623 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2624 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2625
2626 if (options)
2627 uart_parse_options(options, &baud, &parity, &bits, &flow);
2628 else
2629 atmel_console_get_options(port, &baud, &parity, &bits);
2630
2631 return uart_set_options(port, co, baud, parity, bits, flow);
2632 }
2633
2634 static struct uart_driver atmel_uart;
2635
2636 static struct console atmel_console = {
2637 .name = ATMEL_DEVICENAME,
2638 .write = atmel_console_write,
2639 .device = uart_console_device,
2640 .setup = atmel_console_setup,
2641 .flags = CON_PRINTBUFFER,
2642 .index = -1,
2643 .data = &atmel_uart,
2644 };
2645
2646 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2647
2648 /*
2649 * Early console initialization (before VM subsystem initialized).
2650 */
atmel_console_init(void)2651 static int __init atmel_console_init(void)
2652 {
2653 int ret;
2654 if (atmel_default_console_device) {
2655 struct atmel_uart_data *pdata =
2656 dev_get_platdata(&atmel_default_console_device->dev);
2657 int id = pdata->num;
2658 struct atmel_uart_port *port = &atmel_ports[id];
2659
2660 port->backup_imr = 0;
2661 port->uart.line = id;
2662
2663 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2664 ret = atmel_init_port(port, atmel_default_console_device);
2665 if (ret)
2666 return ret;
2667 register_console(&atmel_console);
2668 }
2669
2670 return 0;
2671 }
2672
2673 console_initcall(atmel_console_init);
2674
2675 /*
2676 * Late console initialization.
2677 */
atmel_late_console_init(void)2678 static int __init atmel_late_console_init(void)
2679 {
2680 if (atmel_default_console_device
2681 && !(atmel_console.flags & CON_ENABLED))
2682 register_console(&atmel_console);
2683
2684 return 0;
2685 }
2686
2687 core_initcall(atmel_late_console_init);
2688
atmel_is_console_port(struct uart_port * port)2689 static inline bool atmel_is_console_port(struct uart_port *port)
2690 {
2691 return port->cons && port->cons->index == port->line;
2692 }
2693
2694 #else
2695 #define ATMEL_CONSOLE_DEVICE NULL
2696
atmel_is_console_port(struct uart_port * port)2697 static inline bool atmel_is_console_port(struct uart_port *port)
2698 {
2699 return false;
2700 }
2701 #endif
2702
2703 static struct uart_driver atmel_uart = {
2704 .owner = THIS_MODULE,
2705 .driver_name = "atmel_serial",
2706 .dev_name = ATMEL_DEVICENAME,
2707 .major = SERIAL_ATMEL_MAJOR,
2708 .minor = MINOR_START,
2709 .nr = ATMEL_MAX_UART,
2710 .cons = ATMEL_CONSOLE_DEVICE,
2711 };
2712
2713 #ifdef CONFIG_PM
atmel_serial_clk_will_stop(void)2714 static bool atmel_serial_clk_will_stop(void)
2715 {
2716 #ifdef CONFIG_ARCH_AT91
2717 return at91_suspend_entering_slow_clock();
2718 #else
2719 return false;
2720 #endif
2721 }
2722
atmel_serial_suspend(struct platform_device * pdev,pm_message_t state)2723 static int atmel_serial_suspend(struct platform_device *pdev,
2724 pm_message_t state)
2725 {
2726 struct uart_port *port = platform_get_drvdata(pdev);
2727 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2728
2729 if (atmel_is_console_port(port) && console_suspend_enabled) {
2730 /* Drain the TX shifter */
2731 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2732 ATMEL_US_TXEMPTY))
2733 cpu_relax();
2734 }
2735
2736 /* we can not wake up if we're running on slow clock */
2737 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2738 if (atmel_serial_clk_will_stop()) {
2739 unsigned long flags;
2740
2741 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2742 atmel_port->suspended = true;
2743 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2744 device_set_wakeup_enable(&pdev->dev, 0);
2745 }
2746
2747 uart_suspend_port(&atmel_uart, port);
2748
2749 return 0;
2750 }
2751
atmel_serial_resume(struct platform_device * pdev)2752 static int atmel_serial_resume(struct platform_device *pdev)
2753 {
2754 struct uart_port *port = platform_get_drvdata(pdev);
2755 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2756 unsigned long flags;
2757
2758 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2759 if (atmel_port->pending) {
2760 atmel_handle_receive(port, atmel_port->pending);
2761 atmel_handle_status(port, atmel_port->pending,
2762 atmel_port->pending_status);
2763 atmel_handle_transmit(port, atmel_port->pending);
2764 atmel_port->pending = 0;
2765 }
2766 atmel_port->suspended = false;
2767 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2768
2769 uart_resume_port(&atmel_uart, port);
2770 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2771
2772 return 0;
2773 }
2774 #else
2775 #define atmel_serial_suspend NULL
2776 #define atmel_serial_resume NULL
2777 #endif
2778
atmel_init_gpios(struct atmel_uart_port * p,struct device * dev)2779 static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev)
2780 {
2781 enum mctrl_gpio_idx i;
2782 struct gpio_desc *gpiod;
2783
2784 p->gpios = mctrl_gpio_init_noauto(dev, 0);
2785 if (IS_ERR(p->gpios))
2786 return PTR_ERR(p->gpios);
2787
2788 for (i = 0; i < UART_GPIO_MAX; i++) {
2789 gpiod = mctrl_gpio_to_gpiod(p->gpios, i);
2790 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
2791 p->gpio_irq[i] = gpiod_to_irq(gpiod);
2792 else
2793 p->gpio_irq[i] = -EINVAL;
2794 }
2795
2796 return 0;
2797 }
2798
atmel_serial_probe_fifos(struct atmel_uart_port * port,struct platform_device * pdev)2799 static void atmel_serial_probe_fifos(struct atmel_uart_port *port,
2800 struct platform_device *pdev)
2801 {
2802 port->fifo_size = 0;
2803 port->rts_low = 0;
2804 port->rts_high = 0;
2805
2806 if (of_property_read_u32(pdev->dev.of_node,
2807 "atmel,fifo-size",
2808 &port->fifo_size))
2809 return;
2810
2811 if (!port->fifo_size)
2812 return;
2813
2814 if (port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2815 port->fifo_size = 0;
2816 dev_err(&pdev->dev, "Invalid FIFO size\n");
2817 return;
2818 }
2819
2820 /*
2821 * 0 <= rts_low <= rts_high <= fifo_size
2822 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2823 * to flush their internal TX FIFO, commonly up to 16 data, before
2824 * actually stopping to send new data. So we try to set the RTS High
2825 * Threshold to a reasonably high value respecting this 16 data
2826 * empirical rule when possible.
2827 */
2828 port->rts_high = max_t(int, port->fifo_size >> 1,
2829 port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2830 port->rts_low = max_t(int, port->fifo_size >> 2,
2831 port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2832
2833 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2834 port->fifo_size);
2835 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2836 port->rts_high);
2837 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2838 port->rts_low);
2839 }
2840
atmel_serial_probe(struct platform_device * pdev)2841 static int atmel_serial_probe(struct platform_device *pdev)
2842 {
2843 struct atmel_uart_port *port;
2844 struct device_node *np = pdev->dev.of_node;
2845 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2846 void *data;
2847 int ret = -ENODEV;
2848 bool rs485_enabled;
2849
2850 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2851
2852 if (np)
2853 ret = of_alias_get_id(np, "serial");
2854 else
2855 if (pdata)
2856 ret = pdata->num;
2857
2858 if (ret < 0)
2859 /* port id not found in platform data nor device-tree aliases:
2860 * auto-enumerate it */
2861 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2862
2863 if (ret >= ATMEL_MAX_UART) {
2864 ret = -ENODEV;
2865 goto err;
2866 }
2867
2868 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2869 /* port already in use */
2870 ret = -EBUSY;
2871 goto err;
2872 }
2873
2874 port = &atmel_ports[ret];
2875 port->backup_imr = 0;
2876 port->uart.line = ret;
2877 atmel_serial_probe_fifos(port, pdev);
2878
2879 spin_lock_init(&port->lock_suspended);
2880
2881 ret = atmel_init_gpios(port, &pdev->dev);
2882 if (ret < 0) {
2883 dev_err(&pdev->dev, "Failed to initialize GPIOs.");
2884 goto err_clear_bit;
2885 }
2886
2887 ret = atmel_init_port(port, pdev);
2888 if (ret)
2889 goto err_clear_bit;
2890
2891 if (!atmel_use_pdc_rx(&port->uart)) {
2892 ret = -ENOMEM;
2893 data = kmalloc(sizeof(struct atmel_uart_char)
2894 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2895 if (!data)
2896 goto err_alloc_ring;
2897 port->rx_ring.buf = data;
2898 }
2899
2900 rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED;
2901
2902 ret = uart_add_one_port(&atmel_uart, &port->uart);
2903 if (ret)
2904 goto err_add_port;
2905
2906 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2907 if (atmel_is_console_port(&port->uart)
2908 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2909 /*
2910 * The serial core enabled the clock for us, so undo
2911 * the clk_prepare_enable() in atmel_console_setup()
2912 */
2913 clk_disable_unprepare(port->clk);
2914 }
2915 #endif
2916
2917 device_init_wakeup(&pdev->dev, 1);
2918 platform_set_drvdata(pdev, port);
2919
2920 /*
2921 * The peripheral clock has been disabled by atmel_init_port():
2922 * enable it before accessing I/O registers
2923 */
2924 clk_prepare_enable(port->clk);
2925
2926 if (rs485_enabled) {
2927 atmel_uart_writel(&port->uart, ATMEL_US_MR,
2928 ATMEL_US_USMODE_NORMAL);
2929 atmel_uart_writel(&port->uart, ATMEL_US_CR, ATMEL_US_RTSEN);
2930 }
2931
2932 /*
2933 * Get port name of usart or uart
2934 */
2935 atmel_get_ip_name(&port->uart);
2936
2937 /*
2938 * The peripheral clock can now safely be disabled till the port
2939 * is used
2940 */
2941 clk_disable_unprepare(port->clk);
2942
2943 return 0;
2944
2945 err_add_port:
2946 kfree(port->rx_ring.buf);
2947 port->rx_ring.buf = NULL;
2948 err_alloc_ring:
2949 if (!atmel_is_console_port(&port->uart)) {
2950 clk_put(port->clk);
2951 port->clk = NULL;
2952 }
2953 err_clear_bit:
2954 clear_bit(port->uart.line, atmel_ports_in_use);
2955 err:
2956 return ret;
2957 }
2958
atmel_serial_remove(struct platform_device * pdev)2959 static int atmel_serial_remove(struct platform_device *pdev)
2960 {
2961 struct uart_port *port = platform_get_drvdata(pdev);
2962 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2963 int ret = 0;
2964
2965 tasklet_kill(&atmel_port->tasklet);
2966
2967 device_init_wakeup(&pdev->dev, 0);
2968
2969 ret = uart_remove_one_port(&atmel_uart, port);
2970
2971 kfree(atmel_port->rx_ring.buf);
2972
2973 /* "port" is allocated statically, so we shouldn't free it */
2974
2975 clear_bit(port->line, atmel_ports_in_use);
2976
2977 clk_put(atmel_port->clk);
2978
2979 return ret;
2980 }
2981
2982 static struct platform_driver atmel_serial_driver = {
2983 .probe = atmel_serial_probe,
2984 .remove = atmel_serial_remove,
2985 .suspend = atmel_serial_suspend,
2986 .resume = atmel_serial_resume,
2987 .driver = {
2988 .name = "atmel_usart",
2989 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2990 },
2991 };
2992
atmel_serial_init(void)2993 static int __init atmel_serial_init(void)
2994 {
2995 int ret;
2996
2997 ret = uart_register_driver(&atmel_uart);
2998 if (ret)
2999 return ret;
3000
3001 ret = platform_driver_register(&atmel_serial_driver);
3002 if (ret)
3003 uart_unregister_driver(&atmel_uart);
3004
3005 return ret;
3006 }
3007
atmel_serial_exit(void)3008 static void __exit atmel_serial_exit(void)
3009 {
3010 platform_driver_unregister(&atmel_serial_driver);
3011 uart_unregister_driver(&atmel_uart);
3012 }
3013
3014 module_init(atmel_serial_init);
3015 module_exit(atmel_serial_exit);
3016
3017 MODULE_AUTHOR("Rick Bronson");
3018 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
3019 MODULE_LICENSE("GPL");
3020 MODULE_ALIAS("platform:atmel_usart");
3021