1 /*
2 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
3 *
4 * Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
7 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
8 * Based on max3107.c, by Aavamobile
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/gpio.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/regmap.h>
25 #include <linux/serial_core.h>
26 #include <linux/serial.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/spi/spi.h>
30 #include <linux/uaccess.h>
31
32 #define MAX310X_NAME "max310x"
33 #define MAX310X_MAJOR 204
34 #define MAX310X_MINOR 209
35
36 /* MAX310X register definitions */
37 #define MAX310X_RHR_REG (0x00) /* RX FIFO */
38 #define MAX310X_THR_REG (0x00) /* TX FIFO */
39 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
40 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
41 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
42 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
43 #define MAX310X_REG_05 (0x05)
44 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
45 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
46 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
47 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
48 #define MAX310X_MODE1_REG (0x09) /* MODE1 */
49 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
50 #define MAX310X_LCR_REG (0x0b) /* LCR */
51 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
52 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
53 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
54 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
55 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
56 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
57 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
58 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
59 #define MAX310X_XON1_REG (0x14) /* XON1 character */
60 #define MAX310X_XON2_REG (0x15) /* XON2 character */
61 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
62 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
63 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
64 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
65 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
66 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
67 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
68 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
69 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
70 #define MAX310X_REG_1F (0x1f)
71
72 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
73
74 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
75 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
76
77 /* Extended registers */
78 #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */
79
80 /* IRQ register bits */
81 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
82 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
83 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
84 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
85 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
86 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
87 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
88 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
89
90 /* LSR register bits */
91 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
92 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
93 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
94 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
95 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
96 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
97 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
98
99 /* Special character register bits */
100 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
101 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
102 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
103 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
104 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
105 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
106
107 /* Status register bits */
108 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
109 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
110 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
111 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
112 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
113 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
114
115 /* MODE1 register bits */
116 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
117 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
118 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
119 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
120 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
121 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
122 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
123 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
124
125 /* MODE2 register bits */
126 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
127 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
128 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
129 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
130 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
131 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
132 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
133 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
134
135 /* LCR register bits */
136 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
137 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
138 *
139 * Word length bits table:
140 * 00 -> 5 bit words
141 * 01 -> 6 bit words
142 * 10 -> 7 bit words
143 * 11 -> 8 bit words
144 */
145 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
146 *
147 * STOP length bit table:
148 * 0 -> 1 stop bit
149 * 1 -> 1-1.5 stop bits if
150 * word length is 5,
151 * 2 stop bits otherwise
152 */
153 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
154 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
155 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
156 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
157 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
158 #define MAX310X_LCR_WORD_LEN_5 (0x00)
159 #define MAX310X_LCR_WORD_LEN_6 (0x01)
160 #define MAX310X_LCR_WORD_LEN_7 (0x02)
161 #define MAX310X_LCR_WORD_LEN_8 (0x03)
162
163 /* IRDA register bits */
164 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
165 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
166
167 /* Flow control trigger level register masks */
168 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
169 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
170 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
171 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
172
173 /* FIFO interrupt trigger level register masks */
174 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
175 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
176 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
177 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
178
179 /* Flow control register bits */
180 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
181 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
182 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
183 * are used in conjunction with
184 * XOFF2 for definition of
185 * special character */
186 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
187 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
188 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
189 *
190 * SWFLOW bits 1 & 0 table:
191 * 00 -> no transmitter flow
192 * control
193 * 01 -> receiver compares
194 * XON2 and XOFF2
195 * and controls
196 * transmitter
197 * 10 -> receiver compares
198 * XON1 and XOFF1
199 * and controls
200 * transmitter
201 * 11 -> receiver compares
202 * XON1, XON2, XOFF1 and
203 * XOFF2 and controls
204 * transmitter
205 */
206 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
207 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
208 *
209 * SWFLOW bits 3 & 2 table:
210 * 00 -> no received flow
211 * control
212 * 01 -> transmitter generates
213 * XON2 and XOFF2
214 * 10 -> transmitter generates
215 * XON1 and XOFF1
216 * 11 -> transmitter generates
217 * XON1, XON2, XOFF1 and
218 * XOFF2
219 */
220
221 /* PLL configuration register masks */
222 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
223 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
224
225 /* Baud rate generator configuration register bits */
226 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
227 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
228
229 /* Clock source register bits */
230 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
231 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
232 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
233 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
234 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
235
236 /* Global commands */
237 #define MAX310X_EXTREG_ENBL (0xce)
238 #define MAX310X_EXTREG_DSBL (0xcd)
239
240 /* Misc definitions */
241 #define MAX310X_FIFO_SIZE (128)
242 #define MAX310x_REV_MASK (0xfc)
243
244 /* MAX3107 specific */
245 #define MAX3107_REV_ID (0xa0)
246
247 /* MAX3109 specific */
248 #define MAX3109_REV_ID (0xc0)
249
250 /* MAX14830 specific */
251 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
252 #define MAX14830_REV_ID (0xb0)
253
254 struct max310x_devtype {
255 char name[9];
256 int nr;
257 int (*detect)(struct device *);
258 void (*power)(struct uart_port *, int);
259 };
260
261 struct max310x_one {
262 struct uart_port port;
263 struct work_struct tx_work;
264 struct work_struct md_work;
265 };
266
267 struct max310x_port {
268 struct uart_driver uart;
269 struct max310x_devtype *devtype;
270 struct regmap *regmap;
271 struct mutex mutex;
272 struct clk *clk;
273 #ifdef CONFIG_GPIOLIB
274 struct gpio_chip gpio;
275 #endif
276 struct max310x_one p[0];
277 };
278
max310x_port_read(struct uart_port * port,u8 reg)279 static u8 max310x_port_read(struct uart_port *port, u8 reg)
280 {
281 struct max310x_port *s = dev_get_drvdata(port->dev);
282 unsigned int val = 0;
283
284 regmap_read(s->regmap, port->iobase + reg, &val);
285
286 return val;
287 }
288
max310x_port_write(struct uart_port * port,u8 reg,u8 val)289 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
290 {
291 struct max310x_port *s = dev_get_drvdata(port->dev);
292
293 regmap_write(s->regmap, port->iobase + reg, val);
294 }
295
max310x_port_update(struct uart_port * port,u8 reg,u8 mask,u8 val)296 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
297 {
298 struct max310x_port *s = dev_get_drvdata(port->dev);
299
300 regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
301 }
302
max3107_detect(struct device * dev)303 static int max3107_detect(struct device *dev)
304 {
305 struct max310x_port *s = dev_get_drvdata(dev);
306 unsigned int val = 0;
307 int ret;
308
309 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
310 if (ret)
311 return ret;
312
313 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
314 dev_err(dev,
315 "%s ID 0x%02x does not match\n", s->devtype->name, val);
316 return -ENODEV;
317 }
318
319 return 0;
320 }
321
max3108_detect(struct device * dev)322 static int max3108_detect(struct device *dev)
323 {
324 struct max310x_port *s = dev_get_drvdata(dev);
325 unsigned int val = 0;
326 int ret;
327
328 /* MAX3108 have not REV ID register, we just check default value
329 * from clocksource register to make sure everything works.
330 */
331 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
332 if (ret)
333 return ret;
334
335 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
336 dev_err(dev, "%s not present\n", s->devtype->name);
337 return -ENODEV;
338 }
339
340 return 0;
341 }
342
max3109_detect(struct device * dev)343 static int max3109_detect(struct device *dev)
344 {
345 struct max310x_port *s = dev_get_drvdata(dev);
346 unsigned int val = 0;
347 int ret;
348
349 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
350 MAX310X_EXTREG_ENBL);
351 if (ret)
352 return ret;
353
354 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
355 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
356 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
357 dev_err(dev,
358 "%s ID 0x%02x does not match\n", s->devtype->name, val);
359 return -ENODEV;
360 }
361
362 return 0;
363 }
364
max310x_power(struct uart_port * port,int on)365 static void max310x_power(struct uart_port *port, int on)
366 {
367 max310x_port_update(port, MAX310X_MODE1_REG,
368 MAX310X_MODE1_FORCESLEEP_BIT,
369 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
370 if (on)
371 msleep(50);
372 }
373
max14830_detect(struct device * dev)374 static int max14830_detect(struct device *dev)
375 {
376 struct max310x_port *s = dev_get_drvdata(dev);
377 unsigned int val = 0;
378 int ret;
379
380 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
381 MAX310X_EXTREG_ENBL);
382 if (ret)
383 return ret;
384
385 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
386 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
387 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
388 dev_err(dev,
389 "%s ID 0x%02x does not match\n", s->devtype->name, val);
390 return -ENODEV;
391 }
392
393 return 0;
394 }
395
max14830_power(struct uart_port * port,int on)396 static void max14830_power(struct uart_port *port, int on)
397 {
398 max310x_port_update(port, MAX310X_BRGCFG_REG,
399 MAX14830_BRGCFG_CLKDIS_BIT,
400 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
401 if (on)
402 msleep(50);
403 }
404
405 static const struct max310x_devtype max3107_devtype = {
406 .name = "MAX3107",
407 .nr = 1,
408 .detect = max3107_detect,
409 .power = max310x_power,
410 };
411
412 static const struct max310x_devtype max3108_devtype = {
413 .name = "MAX3108",
414 .nr = 1,
415 .detect = max3108_detect,
416 .power = max310x_power,
417 };
418
419 static const struct max310x_devtype max3109_devtype = {
420 .name = "MAX3109",
421 .nr = 2,
422 .detect = max3109_detect,
423 .power = max310x_power,
424 };
425
426 static const struct max310x_devtype max14830_devtype = {
427 .name = "MAX14830",
428 .nr = 4,
429 .detect = max14830_detect,
430 .power = max14830_power,
431 };
432
max310x_reg_writeable(struct device * dev,unsigned int reg)433 static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
434 {
435 switch (reg & 0x1f) {
436 case MAX310X_IRQSTS_REG:
437 case MAX310X_LSR_IRQSTS_REG:
438 case MAX310X_SPCHR_IRQSTS_REG:
439 case MAX310X_STS_IRQSTS_REG:
440 case MAX310X_TXFIFOLVL_REG:
441 case MAX310X_RXFIFOLVL_REG:
442 return false;
443 default:
444 break;
445 }
446
447 return true;
448 }
449
max310x_reg_volatile(struct device * dev,unsigned int reg)450 static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
451 {
452 switch (reg & 0x1f) {
453 case MAX310X_RHR_REG:
454 case MAX310X_IRQSTS_REG:
455 case MAX310X_LSR_IRQSTS_REG:
456 case MAX310X_SPCHR_IRQSTS_REG:
457 case MAX310X_STS_IRQSTS_REG:
458 case MAX310X_TXFIFOLVL_REG:
459 case MAX310X_RXFIFOLVL_REG:
460 case MAX310X_GPIODATA_REG:
461 case MAX310X_BRGDIVLSB_REG:
462 case MAX310X_REG_05:
463 case MAX310X_REG_1F:
464 return true;
465 default:
466 break;
467 }
468
469 return false;
470 }
471
max310x_reg_precious(struct device * dev,unsigned int reg)472 static bool max310x_reg_precious(struct device *dev, unsigned int reg)
473 {
474 switch (reg & 0x1f) {
475 case MAX310X_RHR_REG:
476 case MAX310X_IRQSTS_REG:
477 case MAX310X_SPCHR_IRQSTS_REG:
478 case MAX310X_STS_IRQSTS_REG:
479 return true;
480 default:
481 break;
482 }
483
484 return false;
485 }
486
max310x_set_baud(struct uart_port * port,int baud)487 static int max310x_set_baud(struct uart_port *port, int baud)
488 {
489 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0;
490
491 /*
492 * Calculate the integer divisor first. Select a proper mode
493 * in case if the requested baud is too high for the pre-defined
494 * clocks frequency.
495 */
496 div = port->uartclk / baud;
497 if (div < 8) {
498 /* Mode x4 */
499 c = 4;
500 mode = MAX310X_BRGCFG_4XMODE_BIT;
501 } else if (div < 16) {
502 /* Mode x2 */
503 c = 8;
504 mode = MAX310X_BRGCFG_2XMODE_BIT;
505 } else {
506 c = 16;
507 }
508
509 /* Calculate the divisor in accordance with the fraction coefficient */
510 div /= c;
511 F = c*baud;
512
513 /* Calculate the baud rate fraction */
514 if (div > 0)
515 frac = (16*(port->uartclk % F)) / F;
516 else
517 div = 1;
518
519 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
520 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
521 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode);
522
523 /* Return the actual baud rate we just programmed */
524 return (16*port->uartclk) / (c*(16*div + frac));
525 }
526
max310x_update_best_err(unsigned long f,long * besterr)527 static int max310x_update_best_err(unsigned long f, long *besterr)
528 {
529 /* Use baudrate 115200 for calculate error */
530 long err = f % (460800 * 16);
531
532 if ((*besterr < 0) || (*besterr > err)) {
533 *besterr = err;
534 return 0;
535 }
536
537 return 1;
538 }
539
max310x_set_ref_clk(struct max310x_port * s,unsigned long freq,bool xtal)540 static int max310x_set_ref_clk(struct max310x_port *s, unsigned long freq,
541 bool xtal)
542 {
543 unsigned int div, clksrc, pllcfg = 0;
544 long besterr = -1;
545 unsigned long fdiv, fmul, bestfreq = freq;
546
547 /* First, update error without PLL */
548 max310x_update_best_err(freq, &besterr);
549
550 /* Try all possible PLL dividers */
551 for (div = 1; (div <= 63) && besterr; div++) {
552 fdiv = DIV_ROUND_CLOSEST(freq, div);
553
554 /* Try multiplier 6 */
555 fmul = fdiv * 6;
556 if ((fdiv >= 500000) && (fdiv <= 800000))
557 if (!max310x_update_best_err(fmul, &besterr)) {
558 pllcfg = (0 << 6) | div;
559 bestfreq = fmul;
560 }
561 /* Try multiplier 48 */
562 fmul = fdiv * 48;
563 if ((fdiv >= 850000) && (fdiv <= 1200000))
564 if (!max310x_update_best_err(fmul, &besterr)) {
565 pllcfg = (1 << 6) | div;
566 bestfreq = fmul;
567 }
568 /* Try multiplier 96 */
569 fmul = fdiv * 96;
570 if ((fdiv >= 425000) && (fdiv <= 1000000))
571 if (!max310x_update_best_err(fmul, &besterr)) {
572 pllcfg = (2 << 6) | div;
573 bestfreq = fmul;
574 }
575 /* Try multiplier 144 */
576 fmul = fdiv * 144;
577 if ((fdiv >= 390000) && (fdiv <= 667000))
578 if (!max310x_update_best_err(fmul, &besterr)) {
579 pllcfg = (3 << 6) | div;
580 bestfreq = fmul;
581 }
582 }
583
584 /* Configure clock source */
585 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0);
586
587 /* Configure PLL */
588 if (pllcfg) {
589 clksrc |= MAX310X_CLKSRC_PLL_BIT;
590 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
591 } else
592 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
593
594 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
595
596 /* Wait for crystal */
597 if (pllcfg && xtal)
598 msleep(10);
599
600 return (int)bestfreq;
601 }
602
max310x_handle_rx(struct uart_port * port,unsigned int rxlen)603 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
604 {
605 unsigned int sts, ch, flag;
606
607 if (unlikely(rxlen >= port->fifosize)) {
608 dev_warn_ratelimited(port->dev,
609 "Port %i: Possible RX FIFO overrun\n",
610 port->line);
611 port->icount.buf_overrun++;
612 /* Ensure sanity of RX level */
613 rxlen = port->fifosize;
614 }
615
616 while (rxlen--) {
617 ch = max310x_port_read(port, MAX310X_RHR_REG);
618 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
619
620 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
621 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
622
623 port->icount.rx++;
624 flag = TTY_NORMAL;
625
626 if (unlikely(sts)) {
627 if (sts & MAX310X_LSR_RXBRK_BIT) {
628 port->icount.brk++;
629 if (uart_handle_break(port))
630 continue;
631 } else if (sts & MAX310X_LSR_RXPAR_BIT)
632 port->icount.parity++;
633 else if (sts & MAX310X_LSR_FRERR_BIT)
634 port->icount.frame++;
635 else if (sts & MAX310X_LSR_RXOVR_BIT)
636 port->icount.overrun++;
637
638 sts &= port->read_status_mask;
639 if (sts & MAX310X_LSR_RXBRK_BIT)
640 flag = TTY_BREAK;
641 else if (sts & MAX310X_LSR_RXPAR_BIT)
642 flag = TTY_PARITY;
643 else if (sts & MAX310X_LSR_FRERR_BIT)
644 flag = TTY_FRAME;
645 else if (sts & MAX310X_LSR_RXOVR_BIT)
646 flag = TTY_OVERRUN;
647 }
648
649 if (uart_handle_sysrq_char(port, ch))
650 continue;
651
652 if (sts & port->ignore_status_mask)
653 continue;
654
655 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
656 }
657
658 tty_flip_buffer_push(&port->state->port);
659 }
660
max310x_handle_tx(struct uart_port * port)661 static void max310x_handle_tx(struct uart_port *port)
662 {
663 struct circ_buf *xmit = &port->state->xmit;
664 unsigned int txlen, to_send;
665
666 if (unlikely(port->x_char)) {
667 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
668 port->icount.tx++;
669 port->x_char = 0;
670 return;
671 }
672
673 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
674 return;
675
676 /* Get length of data pending in circular buffer */
677 to_send = uart_circ_chars_pending(xmit);
678 if (likely(to_send)) {
679 /* Limit to size of TX FIFO */
680 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
681 txlen = port->fifosize - txlen;
682 to_send = (to_send > txlen) ? txlen : to_send;
683
684 /* Add data to send */
685 port->icount.tx += to_send;
686 while (to_send--) {
687 max310x_port_write(port, MAX310X_THR_REG,
688 xmit->buf[xmit->tail]);
689 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
690 }
691 }
692
693 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
694 uart_write_wakeup(port);
695 }
696
max310x_port_irq(struct max310x_port * s,int portno)697 static void max310x_port_irq(struct max310x_port *s, int portno)
698 {
699 struct uart_port *port = &s->p[portno].port;
700
701 do {
702 unsigned int ists, lsr, rxlen;
703
704 /* Read IRQ status & RX FIFO level */
705 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
706 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
707 if (!ists && !rxlen)
708 break;
709
710 if (ists & MAX310X_IRQ_CTS_BIT) {
711 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
712 uart_handle_cts_change(port,
713 !!(lsr & MAX310X_LSR_CTS_BIT));
714 }
715 if (rxlen)
716 max310x_handle_rx(port, rxlen);
717 if (ists & MAX310X_IRQ_TXEMPTY_BIT) {
718 mutex_lock(&s->mutex);
719 max310x_handle_tx(port);
720 mutex_unlock(&s->mutex);
721 }
722 } while (1);
723 }
724
max310x_ist(int irq,void * dev_id)725 static irqreturn_t max310x_ist(int irq, void *dev_id)
726 {
727 struct max310x_port *s = (struct max310x_port *)dev_id;
728
729 if (s->uart.nr > 1) {
730 do {
731 unsigned int val = ~0;
732
733 WARN_ON_ONCE(regmap_read(s->regmap,
734 MAX310X_GLOBALIRQ_REG, &val));
735 val = ((1 << s->uart.nr) - 1) & ~val;
736 if (!val)
737 break;
738 max310x_port_irq(s, fls(val) - 1);
739 } while (1);
740 } else
741 max310x_port_irq(s, 0);
742
743 return IRQ_HANDLED;
744 }
745
max310x_wq_proc(struct work_struct * ws)746 static void max310x_wq_proc(struct work_struct *ws)
747 {
748 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
749 struct max310x_port *s = dev_get_drvdata(one->port.dev);
750
751 mutex_lock(&s->mutex);
752 max310x_handle_tx(&one->port);
753 mutex_unlock(&s->mutex);
754 }
755
max310x_start_tx(struct uart_port * port)756 static void max310x_start_tx(struct uart_port *port)
757 {
758 struct max310x_one *one = container_of(port, struct max310x_one, port);
759
760 if (!work_pending(&one->tx_work))
761 schedule_work(&one->tx_work);
762 }
763
max310x_tx_empty(struct uart_port * port)764 static unsigned int max310x_tx_empty(struct uart_port *port)
765 {
766 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
767
768 return lvl ? 0 : TIOCSER_TEMT;
769 }
770
max310x_get_mctrl(struct uart_port * port)771 static unsigned int max310x_get_mctrl(struct uart_port *port)
772 {
773 /* DCD and DSR are not wired and CTS/RTS is handled automatically
774 * so just indicate DSR and CAR asserted
775 */
776 return TIOCM_DSR | TIOCM_CAR;
777 }
778
max310x_md_proc(struct work_struct * ws)779 static void max310x_md_proc(struct work_struct *ws)
780 {
781 struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
782
783 max310x_port_update(&one->port, MAX310X_MODE2_REG,
784 MAX310X_MODE2_LOOPBACK_BIT,
785 (one->port.mctrl & TIOCM_LOOP) ?
786 MAX310X_MODE2_LOOPBACK_BIT : 0);
787 }
788
max310x_set_mctrl(struct uart_port * port,unsigned int mctrl)789 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
790 {
791 struct max310x_one *one = container_of(port, struct max310x_one, port);
792
793 schedule_work(&one->md_work);
794 }
795
max310x_break_ctl(struct uart_port * port,int break_state)796 static void max310x_break_ctl(struct uart_port *port, int break_state)
797 {
798 max310x_port_update(port, MAX310X_LCR_REG,
799 MAX310X_LCR_TXBREAK_BIT,
800 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
801 }
802
max310x_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)803 static void max310x_set_termios(struct uart_port *port,
804 struct ktermios *termios,
805 struct ktermios *old)
806 {
807 unsigned int lcr, flow = 0;
808 int baud;
809
810 /* Mask termios capabilities we don't support */
811 termios->c_cflag &= ~CMSPAR;
812
813 /* Word size */
814 switch (termios->c_cflag & CSIZE) {
815 case CS5:
816 lcr = MAX310X_LCR_WORD_LEN_5;
817 break;
818 case CS6:
819 lcr = MAX310X_LCR_WORD_LEN_6;
820 break;
821 case CS7:
822 lcr = MAX310X_LCR_WORD_LEN_7;
823 break;
824 case CS8:
825 default:
826 lcr = MAX310X_LCR_WORD_LEN_8;
827 break;
828 }
829
830 /* Parity */
831 if (termios->c_cflag & PARENB) {
832 lcr |= MAX310X_LCR_PARITY_BIT;
833 if (!(termios->c_cflag & PARODD))
834 lcr |= MAX310X_LCR_EVENPARITY_BIT;
835 }
836
837 /* Stop bits */
838 if (termios->c_cflag & CSTOPB)
839 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
840
841 /* Update LCR register */
842 max310x_port_write(port, MAX310X_LCR_REG, lcr);
843
844 /* Set read status mask */
845 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
846 if (termios->c_iflag & INPCK)
847 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
848 MAX310X_LSR_FRERR_BIT;
849 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
850 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
851
852 /* Set status ignore mask */
853 port->ignore_status_mask = 0;
854 if (termios->c_iflag & IGNBRK)
855 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
856 if (!(termios->c_cflag & CREAD))
857 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
858 MAX310X_LSR_RXOVR_BIT |
859 MAX310X_LSR_FRERR_BIT |
860 MAX310X_LSR_RXBRK_BIT;
861
862 /* Configure flow control */
863 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
864 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
865 if (termios->c_cflag & CRTSCTS)
866 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
867 MAX310X_FLOWCTRL_AUTORTS_BIT;
868 if (termios->c_iflag & IXON)
869 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
870 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
871 if (termios->c_iflag & IXOFF)
872 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
873 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
874 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
875
876 /* Get baud rate generator configuration */
877 baud = uart_get_baud_rate(port, termios, old,
878 port->uartclk / 16 / 0xffff,
879 port->uartclk / 4);
880
881 /* Setup baudrate generator */
882 baud = max310x_set_baud(port, baud);
883
884 /* Update timeout according to new baud rate */
885 uart_update_timeout(port, termios->c_cflag, baud);
886 }
887
max310x_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)888 static int max310x_rs485_config(struct uart_port *port,
889 struct serial_rs485 *rs485)
890 {
891 unsigned int val;
892
893 if (rs485->delay_rts_before_send > 0x0f ||
894 rs485->delay_rts_after_send > 0x0f)
895 return -ERANGE;
896
897 val = (rs485->delay_rts_before_send << 4) |
898 rs485->delay_rts_after_send;
899 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
900 if (rs485->flags & SER_RS485_ENABLED) {
901 max310x_port_update(port, MAX310X_MODE1_REG,
902 MAX310X_MODE1_TRNSCVCTRL_BIT,
903 MAX310X_MODE1_TRNSCVCTRL_BIT);
904 max310x_port_update(port, MAX310X_MODE2_REG,
905 MAX310X_MODE2_ECHOSUPR_BIT,
906 MAX310X_MODE2_ECHOSUPR_BIT);
907 } else {
908 max310x_port_update(port, MAX310X_MODE1_REG,
909 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
910 max310x_port_update(port, MAX310X_MODE2_REG,
911 MAX310X_MODE2_ECHOSUPR_BIT, 0);
912 }
913
914 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_ENABLED;
915 memset(rs485->padding, 0, sizeof(rs485->padding));
916 port->rs485 = *rs485;
917
918 return 0;
919 }
920
max310x_startup(struct uart_port * port)921 static int max310x_startup(struct uart_port *port)
922 {
923 struct max310x_port *s = dev_get_drvdata(port->dev);
924 unsigned int val;
925
926 s->devtype->power(port, 1);
927
928 /* Configure MODE1 register */
929 max310x_port_update(port, MAX310X_MODE1_REG,
930 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
931
932 /* Configure MODE2 register & Reset FIFOs*/
933 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
934 max310x_port_write(port, MAX310X_MODE2_REG, val);
935 max310x_port_update(port, MAX310X_MODE2_REG,
936 MAX310X_MODE2_FIFORST_BIT, 0);
937
938 /* Configure flow control levels */
939 /* Flow control halt level 96, resume level 48 */
940 max310x_port_write(port, MAX310X_FLOWLVL_REG,
941 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
942
943 /* Clear IRQ status register */
944 max310x_port_read(port, MAX310X_IRQSTS_REG);
945
946 /* Enable RX, TX, CTS change interrupts */
947 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
948 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
949
950 return 0;
951 }
952
max310x_shutdown(struct uart_port * port)953 static void max310x_shutdown(struct uart_port *port)
954 {
955 struct max310x_port *s = dev_get_drvdata(port->dev);
956
957 /* Disable all interrupts */
958 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
959
960 s->devtype->power(port, 0);
961 }
962
max310x_type(struct uart_port * port)963 static const char *max310x_type(struct uart_port *port)
964 {
965 struct max310x_port *s = dev_get_drvdata(port->dev);
966
967 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
968 }
969
max310x_request_port(struct uart_port * port)970 static int max310x_request_port(struct uart_port *port)
971 {
972 /* Do nothing */
973 return 0;
974 }
975
max310x_config_port(struct uart_port * port,int flags)976 static void max310x_config_port(struct uart_port *port, int flags)
977 {
978 if (flags & UART_CONFIG_TYPE)
979 port->type = PORT_MAX310X;
980 }
981
max310x_verify_port(struct uart_port * port,struct serial_struct * s)982 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
983 {
984 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
985 return -EINVAL;
986 if (s->irq != port->irq)
987 return -EINVAL;
988
989 return 0;
990 }
991
max310x_null_void(struct uart_port * port)992 static void max310x_null_void(struct uart_port *port)
993 {
994 /* Do nothing */
995 }
996
997 static const struct uart_ops max310x_ops = {
998 .tx_empty = max310x_tx_empty,
999 .set_mctrl = max310x_set_mctrl,
1000 .get_mctrl = max310x_get_mctrl,
1001 .stop_tx = max310x_null_void,
1002 .start_tx = max310x_start_tx,
1003 .stop_rx = max310x_null_void,
1004 .break_ctl = max310x_break_ctl,
1005 .startup = max310x_startup,
1006 .shutdown = max310x_shutdown,
1007 .set_termios = max310x_set_termios,
1008 .type = max310x_type,
1009 .request_port = max310x_request_port,
1010 .release_port = max310x_null_void,
1011 .config_port = max310x_config_port,
1012 .verify_port = max310x_verify_port,
1013 };
1014
max310x_suspend(struct device * dev)1015 static int __maybe_unused max310x_suspend(struct device *dev)
1016 {
1017 struct max310x_port *s = dev_get_drvdata(dev);
1018 int i;
1019
1020 for (i = 0; i < s->uart.nr; i++) {
1021 uart_suspend_port(&s->uart, &s->p[i].port);
1022 s->devtype->power(&s->p[i].port, 0);
1023 }
1024
1025 return 0;
1026 }
1027
max310x_resume(struct device * dev)1028 static int __maybe_unused max310x_resume(struct device *dev)
1029 {
1030 struct max310x_port *s = dev_get_drvdata(dev);
1031 int i;
1032
1033 for (i = 0; i < s->uart.nr; i++) {
1034 s->devtype->power(&s->p[i].port, 1);
1035 uart_resume_port(&s->uart, &s->p[i].port);
1036 }
1037
1038 return 0;
1039 }
1040
1041 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1042
1043 #ifdef CONFIG_GPIOLIB
max310x_gpio_get(struct gpio_chip * chip,unsigned offset)1044 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1045 {
1046 unsigned int val;
1047 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1048 struct uart_port *port = &s->p[offset / 4].port;
1049
1050 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1051
1052 return !!((val >> 4) & (1 << (offset % 4)));
1053 }
1054
max310x_gpio_set(struct gpio_chip * chip,unsigned offset,int value)1055 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1056 {
1057 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1058 struct uart_port *port = &s->p[offset / 4].port;
1059
1060 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1061 value ? 1 << (offset % 4) : 0);
1062 }
1063
max310x_gpio_direction_input(struct gpio_chip * chip,unsigned offset)1064 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1065 {
1066 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1067 struct uart_port *port = &s->p[offset / 4].port;
1068
1069 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1070
1071 return 0;
1072 }
1073
max310x_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)1074 static int max310x_gpio_direction_output(struct gpio_chip *chip,
1075 unsigned offset, int value)
1076 {
1077 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1078 struct uart_port *port = &s->p[offset / 4].port;
1079
1080 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1081 value ? 1 << (offset % 4) : 0);
1082 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1083 1 << (offset % 4));
1084
1085 return 0;
1086 }
1087 #endif
1088
max310x_probe(struct device * dev,struct max310x_devtype * devtype,struct regmap * regmap,int irq,unsigned long flags)1089 static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
1090 struct regmap *regmap, int irq, unsigned long flags)
1091 {
1092 int i, ret, fmin, fmax, freq, uartclk;
1093 struct clk *clk_osc, *clk_xtal;
1094 struct max310x_port *s;
1095 bool xtal = false;
1096
1097 if (IS_ERR(regmap))
1098 return PTR_ERR(regmap);
1099
1100 /* Alloc port structure */
1101 s = devm_kzalloc(dev, sizeof(*s) +
1102 sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL);
1103 if (!s) {
1104 dev_err(dev, "Error allocating port structure\n");
1105 return -ENOMEM;
1106 }
1107
1108 clk_osc = devm_clk_get(dev, "osc");
1109 clk_xtal = devm_clk_get(dev, "xtal");
1110 if (!IS_ERR(clk_osc)) {
1111 s->clk = clk_osc;
1112 fmin = 500000;
1113 fmax = 35000000;
1114 } else if (!IS_ERR(clk_xtal)) {
1115 s->clk = clk_xtal;
1116 fmin = 1000000;
1117 fmax = 4000000;
1118 xtal = true;
1119 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER ||
1120 PTR_ERR(clk_xtal) == -EPROBE_DEFER) {
1121 return -EPROBE_DEFER;
1122 } else {
1123 dev_err(dev, "Cannot get clock\n");
1124 return -EINVAL;
1125 }
1126
1127 ret = clk_prepare_enable(s->clk);
1128 if (ret)
1129 return ret;
1130
1131 freq = clk_get_rate(s->clk);
1132 /* Check frequency limits */
1133 if (freq < fmin || freq > fmax) {
1134 ret = -ERANGE;
1135 goto out_clk;
1136 }
1137
1138 s->regmap = regmap;
1139 s->devtype = devtype;
1140 dev_set_drvdata(dev, s);
1141
1142 /* Check device to ensure we are talking to what we expect */
1143 ret = devtype->detect(dev);
1144 if (ret)
1145 goto out_clk;
1146
1147 for (i = 0; i < devtype->nr; i++) {
1148 unsigned int offs = i << 5;
1149
1150 /* Reset port */
1151 regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
1152 MAX310X_MODE2_RST_BIT);
1153 /* Clear port reset */
1154 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
1155
1156 /* Wait for port startup */
1157 do {
1158 regmap_read(s->regmap,
1159 MAX310X_BRGDIVLSB_REG + offs, &ret);
1160 } while (ret != 0x01);
1161
1162 regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs,
1163 MAX310X_MODE1_AUTOSLEEP_BIT,
1164 MAX310X_MODE1_AUTOSLEEP_BIT);
1165 }
1166
1167 uartclk = max310x_set_ref_clk(s, freq, xtal);
1168 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1169
1170 /* Register UART driver */
1171 s->uart.owner = THIS_MODULE;
1172 s->uart.dev_name = "ttyMAX";
1173 s->uart.major = MAX310X_MAJOR;
1174 s->uart.minor = MAX310X_MINOR;
1175 s->uart.nr = devtype->nr;
1176 ret = uart_register_driver(&s->uart);
1177 if (ret) {
1178 dev_err(dev, "Registering UART driver failed\n");
1179 goto out_clk;
1180 }
1181
1182 #ifdef CONFIG_GPIOLIB
1183 /* Setup GPIO cotroller */
1184 s->gpio.owner = THIS_MODULE;
1185 s->gpio.dev = dev;
1186 s->gpio.label = dev_name(dev);
1187 s->gpio.direction_input = max310x_gpio_direction_input;
1188 s->gpio.get = max310x_gpio_get;
1189 s->gpio.direction_output= max310x_gpio_direction_output;
1190 s->gpio.set = max310x_gpio_set;
1191 s->gpio.base = -1;
1192 s->gpio.ngpio = devtype->nr * 4;
1193 s->gpio.can_sleep = 1;
1194 ret = gpiochip_add(&s->gpio);
1195 if (ret)
1196 goto out_uart;
1197 #endif
1198
1199 mutex_init(&s->mutex);
1200
1201 for (i = 0; i < devtype->nr; i++) {
1202 /* Initialize port data */
1203 s->p[i].port.line = i;
1204 s->p[i].port.dev = dev;
1205 s->p[i].port.irq = irq;
1206 s->p[i].port.type = PORT_MAX310X;
1207 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1208 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1209 s->p[i].port.iotype = UPIO_PORT;
1210 s->p[i].port.iobase = i * 0x20;
1211 s->p[i].port.membase = (void __iomem *)~0;
1212 s->p[i].port.uartclk = uartclk;
1213 s->p[i].port.rs485_config = max310x_rs485_config;
1214 s->p[i].port.ops = &max310x_ops;
1215 /* Disable all interrupts */
1216 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1217 /* Clear IRQ status register */
1218 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1219 /* Enable IRQ pin */
1220 max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG,
1221 MAX310X_MODE1_IRQSEL_BIT,
1222 MAX310X_MODE1_IRQSEL_BIT);
1223 /* Initialize queue for start TX */
1224 INIT_WORK(&s->p[i].tx_work, max310x_wq_proc);
1225 /* Initialize queue for changing mode */
1226 INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1227 /* Register port */
1228 uart_add_one_port(&s->uart, &s->p[i].port);
1229 /* Go to suspend mode */
1230 devtype->power(&s->p[i].port, 0);
1231 }
1232
1233 /* Setup interrupt */
1234 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1235 IRQF_ONESHOT | flags, dev_name(dev), s);
1236 if (!ret)
1237 return 0;
1238
1239 dev_err(dev, "Unable to reguest IRQ %i\n", irq);
1240
1241 mutex_destroy(&s->mutex);
1242
1243 #ifdef CONFIG_GPIOLIB
1244 gpiochip_remove(&s->gpio);
1245
1246 out_uart:
1247 #endif
1248 uart_unregister_driver(&s->uart);
1249
1250 out_clk:
1251 clk_disable_unprepare(s->clk);
1252
1253 return ret;
1254 }
1255
max310x_remove(struct device * dev)1256 static int max310x_remove(struct device *dev)
1257 {
1258 struct max310x_port *s = dev_get_drvdata(dev);
1259 int i;
1260
1261 #ifdef CONFIG_GPIOLIB
1262 gpiochip_remove(&s->gpio);
1263 #endif
1264
1265 for (i = 0; i < s->uart.nr; i++) {
1266 cancel_work_sync(&s->p[i].tx_work);
1267 cancel_work_sync(&s->p[i].md_work);
1268 uart_remove_one_port(&s->uart, &s->p[i].port);
1269 s->devtype->power(&s->p[i].port, 0);
1270 }
1271
1272 mutex_destroy(&s->mutex);
1273 uart_unregister_driver(&s->uart);
1274 clk_disable_unprepare(s->clk);
1275
1276 return 0;
1277 }
1278
1279 static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1280 { .compatible = "maxim,max3107", .data = &max3107_devtype, },
1281 { .compatible = "maxim,max3108", .data = &max3108_devtype, },
1282 { .compatible = "maxim,max3109", .data = &max3109_devtype, },
1283 { .compatible = "maxim,max14830", .data = &max14830_devtype },
1284 { }
1285 };
1286 MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1287
1288 static struct regmap_config regcfg = {
1289 .reg_bits = 8,
1290 .val_bits = 8,
1291 .write_flag_mask = 0x80,
1292 .cache_type = REGCACHE_RBTREE,
1293 .writeable_reg = max310x_reg_writeable,
1294 .volatile_reg = max310x_reg_volatile,
1295 .precious_reg = max310x_reg_precious,
1296 };
1297
1298 #ifdef CONFIG_SPI_MASTER
max310x_spi_probe(struct spi_device * spi)1299 static int max310x_spi_probe(struct spi_device *spi)
1300 {
1301 struct max310x_devtype *devtype;
1302 unsigned long flags = 0;
1303 struct regmap *regmap;
1304 int ret;
1305
1306 /* Setup SPI bus */
1307 spi->bits_per_word = 8;
1308 spi->mode = spi->mode ? : SPI_MODE_0;
1309 spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
1310 ret = spi_setup(spi);
1311 if (ret)
1312 return ret;
1313
1314 if (spi->dev.of_node) {
1315 const struct of_device_id *of_id =
1316 of_match_device(max310x_dt_ids, &spi->dev);
1317 if (!of_id)
1318 return -ENODEV;
1319
1320 devtype = (struct max310x_devtype *)of_id->data;
1321 } else {
1322 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1323
1324 devtype = (struct max310x_devtype *)id_entry->driver_data;
1325 flags = IRQF_TRIGGER_FALLING;
1326 }
1327
1328 regcfg.max_register = devtype->nr * 0x20 - 1;
1329 regmap = devm_regmap_init_spi(spi, ®cfg);
1330
1331 return max310x_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1332 }
1333
max310x_spi_remove(struct spi_device * spi)1334 static int max310x_spi_remove(struct spi_device *spi)
1335 {
1336 return max310x_remove(&spi->dev);
1337 }
1338
1339 static const struct spi_device_id max310x_id_table[] = {
1340 { "max3107", (kernel_ulong_t)&max3107_devtype, },
1341 { "max3108", (kernel_ulong_t)&max3108_devtype, },
1342 { "max3109", (kernel_ulong_t)&max3109_devtype, },
1343 { "max14830", (kernel_ulong_t)&max14830_devtype, },
1344 { }
1345 };
1346 MODULE_DEVICE_TABLE(spi, max310x_id_table);
1347
1348 static struct spi_driver max310x_uart_driver = {
1349 .driver = {
1350 .name = MAX310X_NAME,
1351 .of_match_table = of_match_ptr(max310x_dt_ids),
1352 .pm = &max310x_pm_ops,
1353 },
1354 .probe = max310x_spi_probe,
1355 .remove = max310x_spi_remove,
1356 .id_table = max310x_id_table,
1357 };
1358 module_spi_driver(max310x_uart_driver);
1359 #endif
1360
1361 MODULE_LICENSE("GPL");
1362 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1363 MODULE_DESCRIPTION("MAX310X serial driver");
1364