1 /*
2 * Driver for msm7k serial device and console
3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 # define SUPPORT_SYSRQ
20 #endif
21
22 #include <linux/atomic.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmaengine.h>
25 #include <linux/hrtimer.h>
26 #include <linux/module.h>
27 #include <linux/io.h>
28 #include <linux/ioport.h>
29 #include <linux/irq.h>
30 #include <linux/init.h>
31 #include <linux/console.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_core.h>
35 #include <linux/serial.h>
36 #include <linux/slab.h>
37 #include <linux/clk.h>
38 #include <linux/platform_device.h>
39 #include <linux/delay.h>
40 #include <linux/of.h>
41 #include <linux/of_device.h>
42
43 #include "msm_serial.h"
44
45 #define UARTDM_BURST_SIZE 16 /* in bytes */
46 #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
47 #define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
48 #define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
49
50 enum {
51 UARTDM_1P1 = 1,
52 UARTDM_1P2,
53 UARTDM_1P3,
54 UARTDM_1P4,
55 };
56
57 struct msm_dma {
58 struct dma_chan *chan;
59 enum dma_data_direction dir;
60 dma_addr_t phys;
61 unsigned char *virt;
62 dma_cookie_t cookie;
63 u32 enable_bit;
64 unsigned int count;
65 struct dma_async_tx_descriptor *desc;
66 };
67
68 struct msm_port {
69 struct uart_port uart;
70 char name[16];
71 struct clk *clk;
72 struct clk *pclk;
73 unsigned int imr;
74 int is_uartdm;
75 unsigned int old_snap_state;
76 bool break_detected;
77 struct msm_dma tx_dma;
78 struct msm_dma rx_dma;
79 };
80
81 static void msm_handle_tx(struct uart_port *port);
82 static void msm_start_rx_dma(struct msm_port *msm_port);
83
msm_stop_dma(struct uart_port * port,struct msm_dma * dma)84 void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
85 {
86 struct device *dev = port->dev;
87 unsigned int mapped;
88 u32 val;
89
90 mapped = dma->count;
91 dma->count = 0;
92
93 dmaengine_terminate_all(dma->chan);
94
95 /*
96 * DMA Stall happens if enqueue and flush command happens concurrently.
97 * For example before changing the baud rate/protocol configuration and
98 * sending flush command to ADM, disable the channel of UARTDM.
99 * Note: should not reset the receiver here immediately as it is not
100 * suggested to do disable/reset or reset/disable at the same time.
101 */
102 val = msm_read(port, UARTDM_DMEN);
103 val &= ~dma->enable_bit;
104 msm_write(port, val, UARTDM_DMEN);
105
106 if (mapped)
107 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
108 }
109
msm_release_dma(struct msm_port * msm_port)110 static void msm_release_dma(struct msm_port *msm_port)
111 {
112 struct msm_dma *dma;
113
114 dma = &msm_port->tx_dma;
115 if (dma->chan) {
116 msm_stop_dma(&msm_port->uart, dma);
117 dma_release_channel(dma->chan);
118 }
119
120 memset(dma, 0, sizeof(*dma));
121
122 dma = &msm_port->rx_dma;
123 if (dma->chan) {
124 msm_stop_dma(&msm_port->uart, dma);
125 dma_release_channel(dma->chan);
126 kfree(dma->virt);
127 }
128
129 memset(dma, 0, sizeof(*dma));
130 }
131
msm_request_tx_dma(struct msm_port * msm_port,resource_size_t base)132 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
133 {
134 struct device *dev = msm_port->uart.dev;
135 struct dma_slave_config conf;
136 struct msm_dma *dma;
137 u32 crci = 0;
138 int ret;
139
140 dma = &msm_port->tx_dma;
141
142 /* allocate DMA resources, if available */
143 dma->chan = dma_request_slave_channel_reason(dev, "tx");
144 if (IS_ERR(dma->chan))
145 goto no_tx;
146
147 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
148
149 memset(&conf, 0, sizeof(conf));
150 conf.direction = DMA_MEM_TO_DEV;
151 conf.device_fc = true;
152 conf.dst_addr = base + UARTDM_TF;
153 conf.dst_maxburst = UARTDM_BURST_SIZE;
154 conf.slave_id = crci;
155
156 ret = dmaengine_slave_config(dma->chan, &conf);
157 if (ret)
158 goto rel_tx;
159
160 dma->dir = DMA_TO_DEVICE;
161
162 if (msm_port->is_uartdm < UARTDM_1P4)
163 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
164 else
165 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
166
167 return;
168
169 rel_tx:
170 dma_release_channel(dma->chan);
171 no_tx:
172 memset(dma, 0, sizeof(*dma));
173 }
174
msm_request_rx_dma(struct msm_port * msm_port,resource_size_t base)175 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
176 {
177 struct device *dev = msm_port->uart.dev;
178 struct dma_slave_config conf;
179 struct msm_dma *dma;
180 u32 crci = 0;
181 int ret;
182
183 dma = &msm_port->rx_dma;
184
185 /* allocate DMA resources, if available */
186 dma->chan = dma_request_slave_channel_reason(dev, "rx");
187 if (IS_ERR(dma->chan))
188 goto no_rx;
189
190 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
191
192 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
193 if (!dma->virt)
194 goto rel_rx;
195
196 memset(&conf, 0, sizeof(conf));
197 conf.direction = DMA_DEV_TO_MEM;
198 conf.device_fc = true;
199 conf.src_addr = base + UARTDM_RF;
200 conf.src_maxburst = UARTDM_BURST_SIZE;
201 conf.slave_id = crci;
202
203 ret = dmaengine_slave_config(dma->chan, &conf);
204 if (ret)
205 goto err;
206
207 dma->dir = DMA_FROM_DEVICE;
208
209 if (msm_port->is_uartdm < UARTDM_1P4)
210 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
211 else
212 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
213
214 return;
215 err:
216 kfree(dma->virt);
217 rel_rx:
218 dma_release_channel(dma->chan);
219 no_rx:
220 memset(dma, 0, sizeof(*dma));
221 }
222
msm_wait_for_xmitr(struct uart_port * port)223 static inline void msm_wait_for_xmitr(struct uart_port *port)
224 {
225 unsigned int timeout = 500000;
226
227 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
228 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
229 break;
230 udelay(1);
231 if (!timeout--)
232 break;
233 }
234 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
235 }
236
msm_stop_tx(struct uart_port * port)237 static void msm_stop_tx(struct uart_port *port)
238 {
239 struct msm_port *msm_port = UART_TO_MSM(port);
240
241 msm_port->imr &= ~UART_IMR_TXLEV;
242 msm_write(port, msm_port->imr, UART_IMR);
243 }
244
msm_start_tx(struct uart_port * port)245 static void msm_start_tx(struct uart_port *port)
246 {
247 struct msm_port *msm_port = UART_TO_MSM(port);
248 struct msm_dma *dma = &msm_port->tx_dma;
249
250 /* Already started in DMA mode */
251 if (dma->count)
252 return;
253
254 msm_port->imr |= UART_IMR_TXLEV;
255 msm_write(port, msm_port->imr, UART_IMR);
256 }
257
msm_reset_dm_count(struct uart_port * port,int count)258 static void msm_reset_dm_count(struct uart_port *port, int count)
259 {
260 msm_wait_for_xmitr(port);
261 msm_write(port, count, UARTDM_NCF_TX);
262 msm_read(port, UARTDM_NCF_TX);
263 }
264
msm_complete_tx_dma(void * args)265 static void msm_complete_tx_dma(void *args)
266 {
267 struct msm_port *msm_port = args;
268 struct uart_port *port = &msm_port->uart;
269 struct circ_buf *xmit = &port->state->xmit;
270 struct msm_dma *dma = &msm_port->tx_dma;
271 struct dma_tx_state state;
272 enum dma_status status;
273 unsigned long flags;
274 unsigned int count;
275 u32 val;
276
277 spin_lock_irqsave(&port->lock, flags);
278
279 /* Already stopped */
280 if (!dma->count)
281 goto done;
282
283 status = dmaengine_tx_status(dma->chan, dma->cookie, &state);
284
285 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
286
287 val = msm_read(port, UARTDM_DMEN);
288 val &= ~dma->enable_bit;
289 msm_write(port, val, UARTDM_DMEN);
290
291 if (msm_port->is_uartdm > UARTDM_1P3) {
292 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
293 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
294 }
295
296 count = dma->count - state.residue;
297 port->icount.tx += count;
298 dma->count = 0;
299
300 xmit->tail += count;
301 xmit->tail &= UART_XMIT_SIZE - 1;
302
303 /* Restore "Tx FIFO below watermark" interrupt */
304 msm_port->imr |= UART_IMR_TXLEV;
305 msm_write(port, msm_port->imr, UART_IMR);
306
307 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
308 uart_write_wakeup(port);
309
310 msm_handle_tx(port);
311 done:
312 spin_unlock_irqrestore(&port->lock, flags);
313 }
314
msm_handle_tx_dma(struct msm_port * msm_port,unsigned int count)315 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
316 {
317 struct circ_buf *xmit = &msm_port->uart.state->xmit;
318 struct uart_port *port = &msm_port->uart;
319 struct msm_dma *dma = &msm_port->tx_dma;
320 void *cpu_addr;
321 int ret;
322 u32 val;
323
324 cpu_addr = &xmit->buf[xmit->tail];
325
326 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
327 ret = dma_mapping_error(port->dev, dma->phys);
328 if (ret)
329 return ret;
330
331 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
332 count, DMA_MEM_TO_DEV,
333 DMA_PREP_INTERRUPT |
334 DMA_PREP_FENCE);
335 if (!dma->desc) {
336 ret = -EIO;
337 goto unmap;
338 }
339
340 dma->desc->callback = msm_complete_tx_dma;
341 dma->desc->callback_param = msm_port;
342
343 dma->cookie = dmaengine_submit(dma->desc);
344 ret = dma_submit_error(dma->cookie);
345 if (ret)
346 goto unmap;
347
348 /*
349 * Using DMA complete for Tx FIFO reload, no need for
350 * "Tx FIFO below watermark" one, disable it
351 */
352 msm_port->imr &= ~UART_IMR_TXLEV;
353 msm_write(port, msm_port->imr, UART_IMR);
354
355 dma->count = count;
356
357 val = msm_read(port, UARTDM_DMEN);
358 val |= dma->enable_bit;
359
360 if (msm_port->is_uartdm < UARTDM_1P4)
361 msm_write(port, val, UARTDM_DMEN);
362
363 msm_reset_dm_count(port, count);
364
365 if (msm_port->is_uartdm > UARTDM_1P3)
366 msm_write(port, val, UARTDM_DMEN);
367
368 dma_async_issue_pending(dma->chan);
369 return 0;
370 unmap:
371 dma_unmap_single(port->dev, dma->phys, count, dma->dir);
372 return ret;
373 }
374
msm_complete_rx_dma(void * args)375 static void msm_complete_rx_dma(void *args)
376 {
377 struct msm_port *msm_port = args;
378 struct uart_port *port = &msm_port->uart;
379 struct tty_port *tport = &port->state->port;
380 struct msm_dma *dma = &msm_port->rx_dma;
381 int count = 0, i, sysrq;
382 unsigned long flags;
383 u32 val;
384
385 spin_lock_irqsave(&port->lock, flags);
386
387 /* Already stopped */
388 if (!dma->count)
389 goto done;
390
391 val = msm_read(port, UARTDM_DMEN);
392 val &= ~dma->enable_bit;
393 msm_write(port, val, UARTDM_DMEN);
394
395 /* Restore interrupts */
396 msm_port->imr |= UART_IMR_RXLEV | UART_IMR_RXSTALE;
397 msm_write(port, msm_port->imr, UART_IMR);
398
399 if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
400 port->icount.overrun++;
401 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
402 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
403 }
404
405 count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
406
407 port->icount.rx += count;
408
409 dma->count = 0;
410
411 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
412
413 for (i = 0; i < count; i++) {
414 char flag = TTY_NORMAL;
415
416 if (msm_port->break_detected && dma->virt[i] == 0) {
417 port->icount.brk++;
418 flag = TTY_BREAK;
419 msm_port->break_detected = false;
420 if (uart_handle_break(port))
421 continue;
422 }
423
424 if (!(port->read_status_mask & UART_SR_RX_BREAK))
425 flag = TTY_NORMAL;
426
427 spin_unlock_irqrestore(&port->lock, flags);
428 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
429 spin_lock_irqsave(&port->lock, flags);
430 if (!sysrq)
431 tty_insert_flip_char(tport, dma->virt[i], flag);
432 }
433
434 msm_start_rx_dma(msm_port);
435 done:
436 spin_unlock_irqrestore(&port->lock, flags);
437
438 if (count)
439 tty_flip_buffer_push(tport);
440 }
441
msm_start_rx_dma(struct msm_port * msm_port)442 static void msm_start_rx_dma(struct msm_port *msm_port)
443 {
444 struct msm_dma *dma = &msm_port->rx_dma;
445 struct uart_port *uart = &msm_port->uart;
446 u32 val;
447 int ret;
448
449 if (IS_ENABLED(CONFIG_CONSOLE_POLL))
450 return;
451
452 if (!dma->chan)
453 return;
454
455 dma->phys = dma_map_single(uart->dev, dma->virt,
456 UARTDM_RX_SIZE, dma->dir);
457 ret = dma_mapping_error(uart->dev, dma->phys);
458 if (ret)
459 return;
460
461 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
462 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
463 DMA_PREP_INTERRUPT);
464 if (!dma->desc)
465 goto unmap;
466
467 dma->desc->callback = msm_complete_rx_dma;
468 dma->desc->callback_param = msm_port;
469
470 dma->cookie = dmaengine_submit(dma->desc);
471 ret = dma_submit_error(dma->cookie);
472 if (ret)
473 goto unmap;
474 /*
475 * Using DMA for FIFO off-load, no need for "Rx FIFO over
476 * watermark" or "stale" interrupts, disable them
477 */
478 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
479
480 /*
481 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
482 * we need RXSTALE to flush input DMA fifo to memory
483 */
484 if (msm_port->is_uartdm < UARTDM_1P4)
485 msm_port->imr |= UART_IMR_RXSTALE;
486
487 msm_write(uart, msm_port->imr, UART_IMR);
488
489 dma->count = UARTDM_RX_SIZE;
490
491 dma_async_issue_pending(dma->chan);
492
493 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
494 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
495
496 val = msm_read(uart, UARTDM_DMEN);
497 val |= dma->enable_bit;
498
499 if (msm_port->is_uartdm < UARTDM_1P4)
500 msm_write(uart, val, UARTDM_DMEN);
501
502 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
503
504 if (msm_port->is_uartdm > UARTDM_1P3)
505 msm_write(uart, val, UARTDM_DMEN);
506
507 return;
508 unmap:
509 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
510 }
511
msm_stop_rx(struct uart_port * port)512 static void msm_stop_rx(struct uart_port *port)
513 {
514 struct msm_port *msm_port = UART_TO_MSM(port);
515 struct msm_dma *dma = &msm_port->rx_dma;
516
517 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
518 msm_write(port, msm_port->imr, UART_IMR);
519
520 if (dma->chan)
521 msm_stop_dma(port, dma);
522 }
523
msm_enable_ms(struct uart_port * port)524 static void msm_enable_ms(struct uart_port *port)
525 {
526 struct msm_port *msm_port = UART_TO_MSM(port);
527
528 msm_port->imr |= UART_IMR_DELTA_CTS;
529 msm_write(port, msm_port->imr, UART_IMR);
530 }
531
msm_handle_rx_dm(struct uart_port * port,unsigned int misr)532 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
533 {
534 struct tty_port *tport = &port->state->port;
535 unsigned int sr;
536 int count = 0;
537 struct msm_port *msm_port = UART_TO_MSM(port);
538
539 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
540 port->icount.overrun++;
541 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
542 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
543 }
544
545 if (misr & UART_IMR_RXSTALE) {
546 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
547 msm_port->old_snap_state;
548 msm_port->old_snap_state = 0;
549 } else {
550 count = 4 * (msm_read(port, UART_RFWR));
551 msm_port->old_snap_state += count;
552 }
553
554 /* TODO: Precise error reporting */
555
556 port->icount.rx += count;
557
558 while (count > 0) {
559 unsigned char buf[4];
560 int sysrq, r_count, i;
561
562 sr = msm_read(port, UART_SR);
563 if ((sr & UART_SR_RX_READY) == 0) {
564 msm_port->old_snap_state -= count;
565 break;
566 }
567
568 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
569 r_count = min_t(int, count, sizeof(buf));
570
571 for (i = 0; i < r_count; i++) {
572 char flag = TTY_NORMAL;
573
574 if (msm_port->break_detected && buf[i] == 0) {
575 port->icount.brk++;
576 flag = TTY_BREAK;
577 msm_port->break_detected = false;
578 if (uart_handle_break(port))
579 continue;
580 }
581
582 if (!(port->read_status_mask & UART_SR_RX_BREAK))
583 flag = TTY_NORMAL;
584
585 spin_unlock(&port->lock);
586 sysrq = uart_handle_sysrq_char(port, buf[i]);
587 spin_lock(&port->lock);
588 if (!sysrq)
589 tty_insert_flip_char(tport, buf[i], flag);
590 }
591 count -= r_count;
592 }
593
594 spin_unlock(&port->lock);
595 tty_flip_buffer_push(tport);
596 spin_lock(&port->lock);
597
598 if (misr & (UART_IMR_RXSTALE))
599 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
600 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
601 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
602
603 /* Try to use DMA */
604 msm_start_rx_dma(msm_port);
605 }
606
msm_handle_rx(struct uart_port * port)607 static void msm_handle_rx(struct uart_port *port)
608 {
609 struct tty_port *tport = &port->state->port;
610 unsigned int sr;
611
612 /*
613 * Handle overrun. My understanding of the hardware is that overrun
614 * is not tied to the RX buffer, so we handle the case out of band.
615 */
616 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
617 port->icount.overrun++;
618 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
619 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
620 }
621
622 /* and now the main RX loop */
623 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
624 unsigned int c;
625 char flag = TTY_NORMAL;
626 int sysrq;
627
628 c = msm_read(port, UART_RF);
629
630 if (sr & UART_SR_RX_BREAK) {
631 port->icount.brk++;
632 if (uart_handle_break(port))
633 continue;
634 } else if (sr & UART_SR_PAR_FRAME_ERR) {
635 port->icount.frame++;
636 } else {
637 port->icount.rx++;
638 }
639
640 /* Mask conditions we're ignorning. */
641 sr &= port->read_status_mask;
642
643 if (sr & UART_SR_RX_BREAK)
644 flag = TTY_BREAK;
645 else if (sr & UART_SR_PAR_FRAME_ERR)
646 flag = TTY_FRAME;
647
648 spin_unlock(&port->lock);
649 sysrq = uart_handle_sysrq_char(port, c);
650 spin_lock(&port->lock);
651 if (!sysrq)
652 tty_insert_flip_char(tport, c, flag);
653 }
654
655 spin_unlock(&port->lock);
656 tty_flip_buffer_push(tport);
657 spin_lock(&port->lock);
658 }
659
msm_handle_tx_pio(struct uart_port * port,unsigned int tx_count)660 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
661 {
662 struct circ_buf *xmit = &port->state->xmit;
663 struct msm_port *msm_port = UART_TO_MSM(port);
664 unsigned int num_chars;
665 unsigned int tf_pointer = 0;
666 void __iomem *tf;
667
668 if (msm_port->is_uartdm)
669 tf = port->membase + UARTDM_TF;
670 else
671 tf = port->membase + UART_TF;
672
673 if (tx_count && msm_port->is_uartdm)
674 msm_reset_dm_count(port, tx_count);
675
676 while (tf_pointer < tx_count) {
677 int i;
678 char buf[4] = { 0 };
679
680 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
681 break;
682
683 if (msm_port->is_uartdm)
684 num_chars = min(tx_count - tf_pointer,
685 (unsigned int)sizeof(buf));
686 else
687 num_chars = 1;
688
689 for (i = 0; i < num_chars; i++) {
690 buf[i] = xmit->buf[xmit->tail + i];
691 port->icount.tx++;
692 }
693
694 iowrite32_rep(tf, buf, 1);
695 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
696 tf_pointer += num_chars;
697 }
698
699 /* disable tx interrupts if nothing more to send */
700 if (uart_circ_empty(xmit))
701 msm_stop_tx(port);
702
703 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
704 uart_write_wakeup(port);
705 }
706
msm_handle_tx(struct uart_port * port)707 static void msm_handle_tx(struct uart_port *port)
708 {
709 struct msm_port *msm_port = UART_TO_MSM(port);
710 struct circ_buf *xmit = &msm_port->uart.state->xmit;
711 struct msm_dma *dma = &msm_port->tx_dma;
712 unsigned int pio_count, dma_count, dma_min;
713 char buf[4] = { 0 };
714 void __iomem *tf;
715 int err = 0;
716
717 if (port->x_char) {
718 if (msm_port->is_uartdm)
719 tf = port->membase + UARTDM_TF;
720 else
721 tf = port->membase + UART_TF;
722
723 buf[0] = port->x_char;
724
725 if (msm_port->is_uartdm)
726 msm_reset_dm_count(port, 1);
727
728 iowrite32_rep(tf, buf, 1);
729 port->icount.tx++;
730 port->x_char = 0;
731 return;
732 }
733
734 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
735 msm_stop_tx(port);
736 return;
737 }
738
739 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
740 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
741
742 dma_min = 1; /* Always DMA */
743 if (msm_port->is_uartdm > UARTDM_1P3) {
744 dma_count = UARTDM_TX_AIGN(dma_count);
745 dma_min = UARTDM_BURST_SIZE;
746 } else {
747 if (dma_count > UARTDM_TX_MAX)
748 dma_count = UARTDM_TX_MAX;
749 }
750
751 if (pio_count > port->fifosize)
752 pio_count = port->fifosize;
753
754 if (!dma->chan || dma_count < dma_min)
755 msm_handle_tx_pio(port, pio_count);
756 else
757 err = msm_handle_tx_dma(msm_port, dma_count);
758
759 if (err) /* fall back to PIO mode */
760 msm_handle_tx_pio(port, pio_count);
761 }
762
msm_handle_delta_cts(struct uart_port * port)763 static void msm_handle_delta_cts(struct uart_port *port)
764 {
765 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
766 port->icount.cts++;
767 wake_up_interruptible(&port->state->port.delta_msr_wait);
768 }
769
msm_uart_irq(int irq,void * dev_id)770 static irqreturn_t msm_uart_irq(int irq, void *dev_id)
771 {
772 struct uart_port *port = dev_id;
773 struct msm_port *msm_port = UART_TO_MSM(port);
774 struct msm_dma *dma = &msm_port->rx_dma;
775 unsigned long flags;
776 unsigned int misr;
777 u32 val;
778
779 spin_lock_irqsave(&port->lock, flags);
780 misr = msm_read(port, UART_MISR);
781 msm_write(port, 0, UART_IMR); /* disable interrupt */
782
783 if (misr & UART_IMR_RXBREAK_START) {
784 msm_port->break_detected = true;
785 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
786 }
787
788 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
789 if (dma->count) {
790 val = UART_CR_CMD_STALE_EVENT_DISABLE;
791 msm_write(port, val, UART_CR);
792 val = UART_CR_CMD_RESET_STALE_INT;
793 msm_write(port, val, UART_CR);
794 /*
795 * Flush DMA input fifo to memory, this will also
796 * trigger DMA RX completion
797 */
798 dmaengine_terminate_all(dma->chan);
799 } else if (msm_port->is_uartdm) {
800 msm_handle_rx_dm(port, misr);
801 } else {
802 msm_handle_rx(port);
803 }
804 }
805 if (misr & UART_IMR_TXLEV)
806 msm_handle_tx(port);
807 if (misr & UART_IMR_DELTA_CTS)
808 msm_handle_delta_cts(port);
809
810 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
811 spin_unlock_irqrestore(&port->lock, flags);
812
813 return IRQ_HANDLED;
814 }
815
msm_tx_empty(struct uart_port * port)816 static unsigned int msm_tx_empty(struct uart_port *port)
817 {
818 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
819 }
820
msm_get_mctrl(struct uart_port * port)821 static unsigned int msm_get_mctrl(struct uart_port *port)
822 {
823 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
824 }
825
msm_reset(struct uart_port * port)826 static void msm_reset(struct uart_port *port)
827 {
828 struct msm_port *msm_port = UART_TO_MSM(port);
829 unsigned int mr;
830
831 /* reset everything */
832 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
833 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
834 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
835 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
836 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
837 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
838 mr = msm_read(port, UART_MR1);
839 mr &= ~UART_MR1_RX_RDY_CTL;
840 msm_write(port, mr, UART_MR1);
841
842 /* Disable DM modes */
843 if (msm_port->is_uartdm)
844 msm_write(port, 0, UARTDM_DMEN);
845 }
846
msm_set_mctrl(struct uart_port * port,unsigned int mctrl)847 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
848 {
849 unsigned int mr;
850
851 mr = msm_read(port, UART_MR1);
852
853 if (!(mctrl & TIOCM_RTS)) {
854 mr &= ~UART_MR1_RX_RDY_CTL;
855 msm_write(port, mr, UART_MR1);
856 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
857 } else {
858 mr |= UART_MR1_RX_RDY_CTL;
859 msm_write(port, mr, UART_MR1);
860 }
861 }
862
msm_break_ctl(struct uart_port * port,int break_ctl)863 static void msm_break_ctl(struct uart_port *port, int break_ctl)
864 {
865 if (break_ctl)
866 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
867 else
868 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
869 }
870
871 struct msm_baud_map {
872 u16 divisor;
873 u8 code;
874 u8 rxstale;
875 };
876
877 static const struct msm_baud_map *
msm_find_best_baud(struct uart_port * port,unsigned int baud,unsigned long * rate)878 msm_find_best_baud(struct uart_port *port, unsigned int baud,
879 unsigned long *rate)
880 {
881 struct msm_port *msm_port = UART_TO_MSM(port);
882 unsigned int divisor, result;
883 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
884 const struct msm_baud_map *entry, *end, *best;
885 static const struct msm_baud_map table[] = {
886 { 1, 0xff, 31 },
887 { 2, 0xee, 16 },
888 { 3, 0xdd, 8 },
889 { 4, 0xcc, 6 },
890 { 6, 0xbb, 6 },
891 { 8, 0xaa, 6 },
892 { 12, 0x99, 6 },
893 { 16, 0x88, 1 },
894 { 24, 0x77, 1 },
895 { 32, 0x66, 1 },
896 { 48, 0x55, 1 },
897 { 96, 0x44, 1 },
898 { 192, 0x33, 1 },
899 { 384, 0x22, 1 },
900 { 768, 0x11, 1 },
901 { 1536, 0x00, 1 },
902 };
903
904 best = table; /* Default to smallest divider */
905 target = clk_round_rate(msm_port->clk, 16 * baud);
906 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
907
908 end = table + ARRAY_SIZE(table);
909 entry = table;
910 while (entry < end) {
911 if (entry->divisor <= divisor) {
912 result = target / entry->divisor / 16;
913 diff = abs(result - baud);
914
915 /* Keep track of best entry */
916 if (diff < best_diff) {
917 best_diff = diff;
918 best = entry;
919 best_rate = target;
920 }
921
922 if (result == baud)
923 break;
924 } else if (entry->divisor > divisor) {
925 old = target;
926 target = clk_round_rate(msm_port->clk, old + 1);
927 /*
928 * The rate didn't get any faster so we can't do
929 * better at dividing it down
930 */
931 if (target == old)
932 break;
933
934 /* Start the divisor search over at this new rate */
935 entry = table;
936 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
937 continue;
938 }
939 entry++;
940 }
941
942 *rate = best_rate;
943 return best;
944 }
945
msm_set_baud_rate(struct uart_port * port,unsigned int baud,unsigned long * saved_flags)946 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
947 unsigned long *saved_flags)
948 {
949 unsigned int rxstale, watermark, mask;
950 struct msm_port *msm_port = UART_TO_MSM(port);
951 const struct msm_baud_map *entry;
952 unsigned long flags, rate;
953
954 flags = *saved_flags;
955 spin_unlock_irqrestore(&port->lock, flags);
956
957 entry = msm_find_best_baud(port, baud, &rate);
958 clk_set_rate(msm_port->clk, rate);
959 baud = rate / 16 / entry->divisor;
960
961 spin_lock_irqsave(&port->lock, flags);
962 *saved_flags = flags;
963 port->uartclk = rate;
964
965 msm_write(port, entry->code, UART_CSR);
966
967 /* RX stale watermark */
968 rxstale = entry->rxstale;
969 watermark = UART_IPR_STALE_LSB & rxstale;
970 if (msm_port->is_uartdm) {
971 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
972 } else {
973 watermark |= UART_IPR_RXSTALE_LAST;
974 mask = UART_IPR_STALE_TIMEOUT_MSB;
975 }
976
977 watermark |= mask & (rxstale << 2);
978
979 msm_write(port, watermark, UART_IPR);
980
981 /* set RX watermark */
982 watermark = (port->fifosize * 3) / 4;
983 msm_write(port, watermark, UART_RFWR);
984
985 /* set TX watermark */
986 msm_write(port, 10, UART_TFWR);
987
988 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
989 msm_reset(port);
990
991 /* Enable RX and TX */
992 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
993
994 /* turn on RX and CTS interrupts */
995 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
996 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
997
998 msm_write(port, msm_port->imr, UART_IMR);
999
1000 if (msm_port->is_uartdm) {
1001 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1002 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1003 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1004 }
1005
1006 return baud;
1007 }
1008
msm_init_clock(struct uart_port * port)1009 static void msm_init_clock(struct uart_port *port)
1010 {
1011 struct msm_port *msm_port = UART_TO_MSM(port);
1012
1013 clk_prepare_enable(msm_port->clk);
1014 clk_prepare_enable(msm_port->pclk);
1015 msm_serial_set_mnd_regs(port);
1016 }
1017
msm_startup(struct uart_port * port)1018 static int msm_startup(struct uart_port *port)
1019 {
1020 struct msm_port *msm_port = UART_TO_MSM(port);
1021 unsigned int data, rfr_level, mask;
1022 int ret;
1023
1024 snprintf(msm_port->name, sizeof(msm_port->name),
1025 "msm_serial%d", port->line);
1026
1027 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1028 msm_port->name, port);
1029 if (unlikely(ret))
1030 return ret;
1031
1032 msm_init_clock(port);
1033
1034 if (likely(port->fifosize > 12))
1035 rfr_level = port->fifosize - 12;
1036 else
1037 rfr_level = port->fifosize;
1038
1039 /* set automatic RFR level */
1040 data = msm_read(port, UART_MR1);
1041
1042 if (msm_port->is_uartdm)
1043 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
1044 else
1045 mask = UART_MR1_AUTO_RFR_LEVEL1;
1046
1047 data &= ~mask;
1048 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1049 data |= mask & (rfr_level << 2);
1050 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1051 msm_write(port, data, UART_MR1);
1052
1053 if (msm_port->is_uartdm) {
1054 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1055 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1056 }
1057
1058 return 0;
1059 }
1060
msm_shutdown(struct uart_port * port)1061 static void msm_shutdown(struct uart_port *port)
1062 {
1063 struct msm_port *msm_port = UART_TO_MSM(port);
1064
1065 msm_port->imr = 0;
1066 msm_write(port, 0, UART_IMR); /* disable interrupts */
1067
1068 if (msm_port->is_uartdm)
1069 msm_release_dma(msm_port);
1070
1071 clk_disable_unprepare(msm_port->clk);
1072
1073 free_irq(port->irq, port);
1074 }
1075
msm_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)1076 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1077 struct ktermios *old)
1078 {
1079 struct msm_port *msm_port = UART_TO_MSM(port);
1080 struct msm_dma *dma = &msm_port->rx_dma;
1081 unsigned long flags;
1082 unsigned int baud, mr;
1083
1084 spin_lock_irqsave(&port->lock, flags);
1085
1086 if (dma->chan) /* Terminate if any */
1087 msm_stop_dma(port, dma);
1088
1089 /* calculate and set baud rate */
1090 baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1091 baud = msm_set_baud_rate(port, baud, &flags);
1092 if (tty_termios_baud_rate(termios))
1093 tty_termios_encode_baud_rate(termios, baud, baud);
1094
1095 /* calculate parity */
1096 mr = msm_read(port, UART_MR2);
1097 mr &= ~UART_MR2_PARITY_MODE;
1098 if (termios->c_cflag & PARENB) {
1099 if (termios->c_cflag & PARODD)
1100 mr |= UART_MR2_PARITY_MODE_ODD;
1101 else if (termios->c_cflag & CMSPAR)
1102 mr |= UART_MR2_PARITY_MODE_SPACE;
1103 else
1104 mr |= UART_MR2_PARITY_MODE_EVEN;
1105 }
1106
1107 /* calculate bits per char */
1108 mr &= ~UART_MR2_BITS_PER_CHAR;
1109 switch (termios->c_cflag & CSIZE) {
1110 case CS5:
1111 mr |= UART_MR2_BITS_PER_CHAR_5;
1112 break;
1113 case CS6:
1114 mr |= UART_MR2_BITS_PER_CHAR_6;
1115 break;
1116 case CS7:
1117 mr |= UART_MR2_BITS_PER_CHAR_7;
1118 break;
1119 case CS8:
1120 default:
1121 mr |= UART_MR2_BITS_PER_CHAR_8;
1122 break;
1123 }
1124
1125 /* calculate stop bits */
1126 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1127 if (termios->c_cflag & CSTOPB)
1128 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1129 else
1130 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1131
1132 /* set parity, bits per char, and stop bit */
1133 msm_write(port, mr, UART_MR2);
1134
1135 /* calculate and set hardware flow control */
1136 mr = msm_read(port, UART_MR1);
1137 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1138 if (termios->c_cflag & CRTSCTS) {
1139 mr |= UART_MR1_CTS_CTL;
1140 mr |= UART_MR1_RX_RDY_CTL;
1141 }
1142 msm_write(port, mr, UART_MR1);
1143
1144 /* Configure status bits to ignore based on termio flags. */
1145 port->read_status_mask = 0;
1146 if (termios->c_iflag & INPCK)
1147 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1148 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1149 port->read_status_mask |= UART_SR_RX_BREAK;
1150
1151 uart_update_timeout(port, termios->c_cflag, baud);
1152
1153 /* Try to use DMA */
1154 msm_start_rx_dma(msm_port);
1155
1156 spin_unlock_irqrestore(&port->lock, flags);
1157 }
1158
msm_type(struct uart_port * port)1159 static const char *msm_type(struct uart_port *port)
1160 {
1161 return "MSM";
1162 }
1163
msm_release_port(struct uart_port * port)1164 static void msm_release_port(struct uart_port *port)
1165 {
1166 struct platform_device *pdev = to_platform_device(port->dev);
1167 struct resource *uart_resource;
1168 resource_size_t size;
1169
1170 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1171 if (unlikely(!uart_resource))
1172 return;
1173 size = resource_size(uart_resource);
1174
1175 release_mem_region(port->mapbase, size);
1176 iounmap(port->membase);
1177 port->membase = NULL;
1178 }
1179
msm_request_port(struct uart_port * port)1180 static int msm_request_port(struct uart_port *port)
1181 {
1182 struct platform_device *pdev = to_platform_device(port->dev);
1183 struct resource *uart_resource;
1184 resource_size_t size;
1185 int ret;
1186
1187 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1188 if (unlikely(!uart_resource))
1189 return -ENXIO;
1190
1191 size = resource_size(uart_resource);
1192
1193 if (!request_mem_region(port->mapbase, size, "msm_serial"))
1194 return -EBUSY;
1195
1196 port->membase = ioremap(port->mapbase, size);
1197 if (!port->membase) {
1198 ret = -EBUSY;
1199 goto fail_release_port;
1200 }
1201
1202 return 0;
1203
1204 fail_release_port:
1205 release_mem_region(port->mapbase, size);
1206 return ret;
1207 }
1208
msm_config_port(struct uart_port * port,int flags)1209 static void msm_config_port(struct uart_port *port, int flags)
1210 {
1211 int ret;
1212
1213 if (flags & UART_CONFIG_TYPE) {
1214 port->type = PORT_MSM;
1215 ret = msm_request_port(port);
1216 if (ret)
1217 return;
1218 }
1219 }
1220
msm_verify_port(struct uart_port * port,struct serial_struct * ser)1221 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1222 {
1223 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1224 return -EINVAL;
1225 if (unlikely(port->irq != ser->irq))
1226 return -EINVAL;
1227 return 0;
1228 }
1229
msm_power(struct uart_port * port,unsigned int state,unsigned int oldstate)1230 static void msm_power(struct uart_port *port, unsigned int state,
1231 unsigned int oldstate)
1232 {
1233 struct msm_port *msm_port = UART_TO_MSM(port);
1234
1235 switch (state) {
1236 case 0:
1237 clk_prepare_enable(msm_port->clk);
1238 clk_prepare_enable(msm_port->pclk);
1239 break;
1240 case 3:
1241 clk_disable_unprepare(msm_port->clk);
1242 clk_disable_unprepare(msm_port->pclk);
1243 break;
1244 default:
1245 pr_err("msm_serial: Unknown PM state %d\n", state);
1246 }
1247 }
1248
1249 #ifdef CONFIG_CONSOLE_POLL
msm_poll_get_char_single(struct uart_port * port)1250 static int msm_poll_get_char_single(struct uart_port *port)
1251 {
1252 struct msm_port *msm_port = UART_TO_MSM(port);
1253 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1254
1255 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1256 return NO_POLL_CHAR;
1257
1258 return msm_read(port, rf_reg) & 0xff;
1259 }
1260
msm_poll_get_char_dm(struct uart_port * port)1261 static int msm_poll_get_char_dm(struct uart_port *port)
1262 {
1263 int c;
1264 static u32 slop;
1265 static int count;
1266 unsigned char *sp = (unsigned char *)&slop;
1267
1268 /* Check if a previous read had more than one char */
1269 if (count) {
1270 c = sp[sizeof(slop) - count];
1271 count--;
1272 /* Or if FIFO is empty */
1273 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1274 /*
1275 * If RX packing buffer has less than a word, force stale to
1276 * push contents into RX FIFO
1277 */
1278 count = msm_read(port, UARTDM_RXFS);
1279 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1280 if (count) {
1281 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1282 slop = msm_read(port, UARTDM_RF);
1283 c = sp[0];
1284 count--;
1285 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1286 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1287 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1288 UART_CR);
1289 } else {
1290 c = NO_POLL_CHAR;
1291 }
1292 /* FIFO has a word */
1293 } else {
1294 slop = msm_read(port, UARTDM_RF);
1295 c = sp[0];
1296 count = sizeof(slop) - 1;
1297 }
1298
1299 return c;
1300 }
1301
msm_poll_get_char(struct uart_port * port)1302 static int msm_poll_get_char(struct uart_port *port)
1303 {
1304 u32 imr;
1305 int c;
1306 struct msm_port *msm_port = UART_TO_MSM(port);
1307
1308 /* Disable all interrupts */
1309 imr = msm_read(port, UART_IMR);
1310 msm_write(port, 0, UART_IMR);
1311
1312 if (msm_port->is_uartdm)
1313 c = msm_poll_get_char_dm(port);
1314 else
1315 c = msm_poll_get_char_single(port);
1316
1317 /* Enable interrupts */
1318 msm_write(port, imr, UART_IMR);
1319
1320 return c;
1321 }
1322
msm_poll_put_char(struct uart_port * port,unsigned char c)1323 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1324 {
1325 u32 imr;
1326 struct msm_port *msm_port = UART_TO_MSM(port);
1327
1328 /* Disable all interrupts */
1329 imr = msm_read(port, UART_IMR);
1330 msm_write(port, 0, UART_IMR);
1331
1332 if (msm_port->is_uartdm)
1333 msm_reset_dm_count(port, 1);
1334
1335 /* Wait until FIFO is empty */
1336 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1337 cpu_relax();
1338
1339 /* Write a character */
1340 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1341
1342 /* Wait until FIFO is empty */
1343 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1344 cpu_relax();
1345
1346 /* Enable interrupts */
1347 msm_write(port, imr, UART_IMR);
1348 }
1349 #endif
1350
1351 static struct uart_ops msm_uart_pops = {
1352 .tx_empty = msm_tx_empty,
1353 .set_mctrl = msm_set_mctrl,
1354 .get_mctrl = msm_get_mctrl,
1355 .stop_tx = msm_stop_tx,
1356 .start_tx = msm_start_tx,
1357 .stop_rx = msm_stop_rx,
1358 .enable_ms = msm_enable_ms,
1359 .break_ctl = msm_break_ctl,
1360 .startup = msm_startup,
1361 .shutdown = msm_shutdown,
1362 .set_termios = msm_set_termios,
1363 .type = msm_type,
1364 .release_port = msm_release_port,
1365 .request_port = msm_request_port,
1366 .config_port = msm_config_port,
1367 .verify_port = msm_verify_port,
1368 .pm = msm_power,
1369 #ifdef CONFIG_CONSOLE_POLL
1370 .poll_get_char = msm_poll_get_char,
1371 .poll_put_char = msm_poll_put_char,
1372 #endif
1373 };
1374
1375 static struct msm_port msm_uart_ports[] = {
1376 {
1377 .uart = {
1378 .iotype = UPIO_MEM,
1379 .ops = &msm_uart_pops,
1380 .flags = UPF_BOOT_AUTOCONF,
1381 .fifosize = 64,
1382 .line = 0,
1383 },
1384 },
1385 {
1386 .uart = {
1387 .iotype = UPIO_MEM,
1388 .ops = &msm_uart_pops,
1389 .flags = UPF_BOOT_AUTOCONF,
1390 .fifosize = 64,
1391 .line = 1,
1392 },
1393 },
1394 {
1395 .uart = {
1396 .iotype = UPIO_MEM,
1397 .ops = &msm_uart_pops,
1398 .flags = UPF_BOOT_AUTOCONF,
1399 .fifosize = 64,
1400 .line = 2,
1401 },
1402 },
1403 };
1404
1405 #define UART_NR ARRAY_SIZE(msm_uart_ports)
1406
msm_get_port_from_line(unsigned int line)1407 static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1408 {
1409 return &msm_uart_ports[line].uart;
1410 }
1411
1412 #ifdef CONFIG_SERIAL_MSM_CONSOLE
__msm_console_write(struct uart_port * port,const char * s,unsigned int count,bool is_uartdm)1413 static void __msm_console_write(struct uart_port *port, const char *s,
1414 unsigned int count, bool is_uartdm)
1415 {
1416 int i;
1417 int num_newlines = 0;
1418 bool replaced = false;
1419 void __iomem *tf;
1420 int locked = 1;
1421
1422 if (is_uartdm)
1423 tf = port->membase + UARTDM_TF;
1424 else
1425 tf = port->membase + UART_TF;
1426
1427 /* Account for newlines that will get a carriage return added */
1428 for (i = 0; i < count; i++)
1429 if (s[i] == '\n')
1430 num_newlines++;
1431 count += num_newlines;
1432
1433 if (port->sysrq)
1434 locked = 0;
1435 else if (oops_in_progress)
1436 locked = spin_trylock(&port->lock);
1437 else
1438 spin_lock(&port->lock);
1439
1440 if (is_uartdm)
1441 msm_reset_dm_count(port, count);
1442
1443 i = 0;
1444 while (i < count) {
1445 int j;
1446 unsigned int num_chars;
1447 char buf[4] = { 0 };
1448
1449 if (is_uartdm)
1450 num_chars = min(count - i, (unsigned int)sizeof(buf));
1451 else
1452 num_chars = 1;
1453
1454 for (j = 0; j < num_chars; j++) {
1455 char c = *s;
1456
1457 if (c == '\n' && !replaced) {
1458 buf[j] = '\r';
1459 j++;
1460 replaced = true;
1461 }
1462 if (j < num_chars) {
1463 buf[j] = c;
1464 s++;
1465 replaced = false;
1466 }
1467 }
1468
1469 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1470 cpu_relax();
1471
1472 iowrite32_rep(tf, buf, 1);
1473 i += num_chars;
1474 }
1475
1476 if (locked)
1477 spin_unlock(&port->lock);
1478 }
1479
msm_console_write(struct console * co,const char * s,unsigned int count)1480 static void msm_console_write(struct console *co, const char *s,
1481 unsigned int count)
1482 {
1483 struct uart_port *port;
1484 struct msm_port *msm_port;
1485
1486 BUG_ON(co->index < 0 || co->index >= UART_NR);
1487
1488 port = msm_get_port_from_line(co->index);
1489 msm_port = UART_TO_MSM(port);
1490
1491 __msm_console_write(port, s, count, msm_port->is_uartdm);
1492 }
1493
msm_console_setup(struct console * co,char * options)1494 static int __init msm_console_setup(struct console *co, char *options)
1495 {
1496 struct uart_port *port;
1497 int baud = 115200;
1498 int bits = 8;
1499 int parity = 'n';
1500 int flow = 'n';
1501
1502 if (unlikely(co->index >= UART_NR || co->index < 0))
1503 return -ENXIO;
1504
1505 port = msm_get_port_from_line(co->index);
1506
1507 if (unlikely(!port->membase))
1508 return -ENXIO;
1509
1510 msm_init_clock(port);
1511
1512 if (options)
1513 uart_parse_options(options, &baud, &parity, &bits, &flow);
1514
1515 pr_info("msm_serial: console setup on port #%d\n", port->line);
1516
1517 return uart_set_options(port, co, baud, parity, bits, flow);
1518 }
1519
1520 static void
msm_serial_early_write(struct console * con,const char * s,unsigned n)1521 msm_serial_early_write(struct console *con, const char *s, unsigned n)
1522 {
1523 struct earlycon_device *dev = con->data;
1524
1525 __msm_console_write(&dev->port, s, n, false);
1526 }
1527
1528 static int __init
msm_serial_early_console_setup(struct earlycon_device * device,const char * opt)1529 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1530 {
1531 if (!device->port.membase)
1532 return -ENODEV;
1533
1534 device->con->write = msm_serial_early_write;
1535 return 0;
1536 }
1537 EARLYCON_DECLARE(msm_serial, msm_serial_early_console_setup);
1538 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1539 msm_serial_early_console_setup);
1540
1541 static void
msm_serial_early_write_dm(struct console * con,const char * s,unsigned n)1542 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1543 {
1544 struct earlycon_device *dev = con->data;
1545
1546 __msm_console_write(&dev->port, s, n, true);
1547 }
1548
1549 static int __init
msm_serial_early_console_setup_dm(struct earlycon_device * device,const char * opt)1550 msm_serial_early_console_setup_dm(struct earlycon_device *device,
1551 const char *opt)
1552 {
1553 if (!device->port.membase)
1554 return -ENODEV;
1555
1556 device->con->write = msm_serial_early_write_dm;
1557 return 0;
1558 }
1559 EARLYCON_DECLARE(msm_serial_dm, msm_serial_early_console_setup_dm);
1560 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1561 msm_serial_early_console_setup_dm);
1562
1563 static struct uart_driver msm_uart_driver;
1564
1565 static struct console msm_console = {
1566 .name = "ttyMSM",
1567 .write = msm_console_write,
1568 .device = uart_console_device,
1569 .setup = msm_console_setup,
1570 .flags = CON_PRINTBUFFER,
1571 .index = -1,
1572 .data = &msm_uart_driver,
1573 };
1574
1575 #define MSM_CONSOLE (&msm_console)
1576
1577 #else
1578 #define MSM_CONSOLE NULL
1579 #endif
1580
1581 static struct uart_driver msm_uart_driver = {
1582 .owner = THIS_MODULE,
1583 .driver_name = "msm_serial",
1584 .dev_name = "ttyMSM",
1585 .nr = UART_NR,
1586 .cons = MSM_CONSOLE,
1587 };
1588
1589 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1590
1591 static const struct of_device_id msm_uartdm_table[] = {
1592 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1593 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1594 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1595 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1596 { }
1597 };
1598
msm_serial_probe(struct platform_device * pdev)1599 static int msm_serial_probe(struct platform_device *pdev)
1600 {
1601 struct msm_port *msm_port;
1602 struct resource *resource;
1603 struct uart_port *port;
1604 const struct of_device_id *id;
1605 int irq, line;
1606
1607 if (pdev->dev.of_node)
1608 line = of_alias_get_id(pdev->dev.of_node, "serial");
1609 else
1610 line = pdev->id;
1611
1612 if (line < 0)
1613 line = atomic_inc_return(&msm_uart_next_id) - 1;
1614
1615 if (unlikely(line < 0 || line >= UART_NR))
1616 return -ENXIO;
1617
1618 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1619
1620 port = msm_get_port_from_line(line);
1621 port->dev = &pdev->dev;
1622 msm_port = UART_TO_MSM(port);
1623
1624 id = of_match_device(msm_uartdm_table, &pdev->dev);
1625 if (id)
1626 msm_port->is_uartdm = (unsigned long)id->data;
1627 else
1628 msm_port->is_uartdm = 0;
1629
1630 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1631 if (IS_ERR(msm_port->clk))
1632 return PTR_ERR(msm_port->clk);
1633
1634 if (msm_port->is_uartdm) {
1635 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1636 if (IS_ERR(msm_port->pclk))
1637 return PTR_ERR(msm_port->pclk);
1638
1639 clk_set_rate(msm_port->clk, 1843200);
1640 }
1641
1642 port->uartclk = clk_get_rate(msm_port->clk);
1643 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1644
1645 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1646 if (unlikely(!resource))
1647 return -ENXIO;
1648 port->mapbase = resource->start;
1649
1650 irq = platform_get_irq(pdev, 0);
1651 if (unlikely(irq < 0))
1652 return -ENXIO;
1653 port->irq = irq;
1654
1655 platform_set_drvdata(pdev, port);
1656
1657 return uart_add_one_port(&msm_uart_driver, port);
1658 }
1659
msm_serial_remove(struct platform_device * pdev)1660 static int msm_serial_remove(struct platform_device *pdev)
1661 {
1662 struct uart_port *port = platform_get_drvdata(pdev);
1663
1664 uart_remove_one_port(&msm_uart_driver, port);
1665
1666 return 0;
1667 }
1668
1669 static const struct of_device_id msm_match_table[] = {
1670 { .compatible = "qcom,msm-uart" },
1671 { .compatible = "qcom,msm-uartdm" },
1672 {}
1673 };
1674 MODULE_DEVICE_TABLE(of, msm_match_table);
1675
1676 static struct platform_driver msm_platform_driver = {
1677 .remove = msm_serial_remove,
1678 .probe = msm_serial_probe,
1679 .driver = {
1680 .name = "msm_serial",
1681 .of_match_table = msm_match_table,
1682 },
1683 };
1684
msm_serial_init(void)1685 static int __init msm_serial_init(void)
1686 {
1687 int ret;
1688
1689 ret = uart_register_driver(&msm_uart_driver);
1690 if (unlikely(ret))
1691 return ret;
1692
1693 ret = platform_driver_register(&msm_platform_driver);
1694 if (unlikely(ret))
1695 uart_unregister_driver(&msm_uart_driver);
1696
1697 pr_info("msm_serial: driver initialized\n");
1698
1699 return ret;
1700 }
1701
msm_serial_exit(void)1702 static void __exit msm_serial_exit(void)
1703 {
1704 platform_driver_unregister(&msm_platform_driver);
1705 uart_unregister_driver(&msm_uart_driver);
1706 }
1707
1708 module_init(msm_serial_init);
1709 module_exit(msm_serial_exit);
1710
1711 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1712 MODULE_DESCRIPTION("Driver for msm7x serial device");
1713 MODULE_LICENSE("GPL");
1714