1 /*
2 * core_intr.c - DesignWare HS OTG Controller common interrupt handling
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 /*
38 * This file contains the common interrupt handlers
39 */
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/io.h>
47 #include <linux/slab.h>
48 #include <linux/usb.h>
49
50 #include <linux/usb/hcd.h>
51 #include <linux/usb/ch11.h>
52
53 #include "core.h"
54 #include "hcd.h"
55
dwc2_op_state_str(struct dwc2_hsotg * hsotg)56 static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
57 {
58 switch (hsotg->op_state) {
59 case OTG_STATE_A_HOST:
60 return "a_host";
61 case OTG_STATE_A_SUSPEND:
62 return "a_suspend";
63 case OTG_STATE_A_PERIPHERAL:
64 return "a_peripheral";
65 case OTG_STATE_B_PERIPHERAL:
66 return "b_peripheral";
67 case OTG_STATE_B_HOST:
68 return "b_host";
69 default:
70 return "unknown";
71 }
72 }
73
74 /**
75 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
76 * When the PRTINT interrupt fires, there are certain status bits in the Host
77 * Port that needs to get cleared.
78 *
79 * @hsotg: Programming view of DWC_otg controller
80 */
dwc2_handle_usb_port_intr(struct dwc2_hsotg * hsotg)81 static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
82 {
83 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
84
85 if (hprt0 & HPRT0_ENACHG) {
86 hprt0 &= ~HPRT0_ENA;
87 dwc2_writel(hprt0, hsotg->regs + HPRT0);
88 }
89
90 /* Clear interrupt */
91 dwc2_writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS);
92 }
93
94 /**
95 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
96 *
97 * @hsotg: Programming view of DWC_otg controller
98 */
dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg * hsotg)99 static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
100 {
101 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
102 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
103
104 /* Clear interrupt */
105 dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
106 }
107
108 /**
109 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
110 * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
111 *
112 * @hsotg: Programming view of DWC_otg controller
113 */
dwc2_handle_otg_intr(struct dwc2_hsotg * hsotg)114 static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
115 {
116 u32 gotgint;
117 u32 gotgctl;
118 u32 gintmsk;
119
120 gotgint = dwc2_readl(hsotg->regs + GOTGINT);
121 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
122 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
123 dwc2_op_state_str(hsotg));
124
125 if (gotgint & GOTGINT_SES_END_DET) {
126 dev_dbg(hsotg->dev,
127 " ++OTG Interrupt: Session End Detected++ (%s)\n",
128 dwc2_op_state_str(hsotg));
129 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
130
131 if (dwc2_is_device_mode(hsotg))
132 dwc2_hsotg_disconnect(hsotg);
133
134 if (hsotg->op_state == OTG_STATE_B_HOST) {
135 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
136 } else {
137 /*
138 * If not B_HOST and Device HNP still set, HNP did
139 * not succeed!
140 */
141 if (gotgctl & GOTGCTL_DEVHNPEN) {
142 dev_dbg(hsotg->dev, "Session End Detected\n");
143 dev_err(hsotg->dev,
144 "Device Not Connected/Responding!\n");
145 }
146
147 /*
148 * If Session End Detected the B-Cable has been
149 * disconnected
150 */
151 /* Reset to a clean state */
152 hsotg->lx_state = DWC2_L0;
153 }
154
155 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
156 gotgctl &= ~GOTGCTL_DEVHNPEN;
157 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
158 }
159
160 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
161 dev_dbg(hsotg->dev,
162 " ++OTG Interrupt: Session Request Success Status Change++\n");
163 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
164 if (gotgctl & GOTGCTL_SESREQSCS) {
165 if (hsotg->core_params->phy_type ==
166 DWC2_PHY_TYPE_PARAM_FS
167 && hsotg->core_params->i2c_enable > 0) {
168 hsotg->srp_success = 1;
169 } else {
170 /* Clear Session Request */
171 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
172 gotgctl &= ~GOTGCTL_SESREQ;
173 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
174 }
175 }
176 }
177
178 if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
179 /*
180 * Print statements during the HNP interrupt handling
181 * can cause it to fail
182 */
183 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
184 /*
185 * WA for 3.00a- HW is not setting cur_mode, even sometimes
186 * this does not help
187 */
188 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
189 udelay(100);
190 if (gotgctl & GOTGCTL_HSTNEGSCS) {
191 if (dwc2_is_host_mode(hsotg)) {
192 hsotg->op_state = OTG_STATE_B_HOST;
193 /*
194 * Need to disable SOF interrupt immediately.
195 * When switching from device to host, the PCD
196 * interrupt handler won't handle the interrupt
197 * if host mode is already set. The HCD
198 * interrupt handler won't get called if the
199 * HCD state is HALT. This means that the
200 * interrupt does not get handled and Linux
201 * complains loudly.
202 */
203 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
204 gintmsk &= ~GINTSTS_SOF;
205 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
206
207 /*
208 * Call callback function with spin lock
209 * released
210 */
211 spin_unlock(&hsotg->lock);
212
213 /* Initialize the Core for Host mode */
214 dwc2_hcd_start(hsotg);
215 spin_lock(&hsotg->lock);
216 hsotg->op_state = OTG_STATE_B_HOST;
217 }
218 } else {
219 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
220 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
221 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
222 dev_dbg(hsotg->dev, "HNP Failed\n");
223 dev_err(hsotg->dev,
224 "Device Not Connected/Responding\n");
225 }
226 }
227
228 if (gotgint & GOTGINT_HST_NEG_DET) {
229 /*
230 * The disconnect interrupt is set at the same time as
231 * Host Negotiation Detected. During the mode switch all
232 * interrupts are cleared so the disconnect interrupt
233 * handler will not get executed.
234 */
235 dev_dbg(hsotg->dev,
236 " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
237 (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
238 if (dwc2_is_device_mode(hsotg)) {
239 dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
240 hsotg->op_state);
241 spin_unlock(&hsotg->lock);
242 dwc2_hcd_disconnect(hsotg);
243 spin_lock(&hsotg->lock);
244 hsotg->op_state = OTG_STATE_A_PERIPHERAL;
245 } else {
246 /* Need to disable SOF interrupt immediately */
247 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
248 gintmsk &= ~GINTSTS_SOF;
249 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
250 spin_unlock(&hsotg->lock);
251 dwc2_hcd_start(hsotg);
252 spin_lock(&hsotg->lock);
253 hsotg->op_state = OTG_STATE_A_HOST;
254 }
255 }
256
257 if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
258 dev_dbg(hsotg->dev,
259 " ++OTG Interrupt: A-Device Timeout Change++\n");
260 if (gotgint & GOTGINT_DBNCE_DONE)
261 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
262
263 /* Clear GOTGINT */
264 dwc2_writel(gotgint, hsotg->regs + GOTGINT);
265 }
266
267 /**
268 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
269 * Change Interrupt
270 *
271 * @hsotg: Programming view of DWC_otg controller
272 *
273 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
274 * Device to Host Mode transition or a Host to Device Mode transition. This only
275 * occurs when the cable is connected/removed from the PHY connector.
276 */
dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg * hsotg)277 static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
278 {
279 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
280
281 /* Need to disable SOF interrupt immediately */
282 gintmsk &= ~GINTSTS_SOF;
283 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
284
285 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
286 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
287
288 /*
289 * Need to schedule a work, as there are possible DELAY function calls.
290 * Release lock before scheduling workq as it holds spinlock during
291 * scheduling.
292 */
293 if (hsotg->wq_otg) {
294 spin_unlock(&hsotg->lock);
295 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
296 spin_lock(&hsotg->lock);
297 }
298
299 /* Clear interrupt */
300 dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
301 }
302
303 /**
304 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
305 * initiating the Session Request Protocol to request the host to turn on bus
306 * power so a new session can begin
307 *
308 * @hsotg: Programming view of DWC_otg controller
309 *
310 * This handler responds by turning on bus power. If the DWC_otg controller is
311 * in low power mode, this handler brings the controller out of low power mode
312 * before turning on bus power.
313 */
dwc2_handle_session_req_intr(struct dwc2_hsotg * hsotg)314 static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
315 {
316 int ret;
317
318 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
319 hsotg->lx_state);
320
321 /* Clear interrupt */
322 dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
323
324 if (dwc2_is_device_mode(hsotg)) {
325 if (hsotg->lx_state == DWC2_L2) {
326 ret = dwc2_exit_hibernation(hsotg, true);
327 if (ret && (ret != -ENOTSUPP))
328 dev_err(hsotg->dev,
329 "exit hibernation failed\n");
330 }
331
332 /*
333 * Report disconnect if there is any previous session
334 * established
335 */
336 dwc2_hsotg_disconnect(hsotg);
337 }
338 }
339
340 /*
341 * This interrupt indicates that the DWC_otg controller has detected a
342 * resume or remote wakeup sequence. If the DWC_otg controller is in
343 * low power mode, the handler must brings the controller out of low
344 * power mode. The controller automatically begins resume signaling.
345 * The handler schedules a time to stop resume signaling.
346 */
dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg * hsotg)347 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
348 {
349 int ret;
350 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
351 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
352
353 if (dwc2_is_device_mode(hsotg)) {
354 dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
355 dwc2_readl(hsotg->regs + DSTS));
356 if (hsotg->lx_state == DWC2_L2) {
357 u32 dctl = dwc2_readl(hsotg->regs + DCTL);
358
359 /* Clear Remote Wakeup Signaling */
360 dctl &= ~DCTL_RMTWKUPSIG;
361 dwc2_writel(dctl, hsotg->regs + DCTL);
362 ret = dwc2_exit_hibernation(hsotg, true);
363 if (ret && (ret != -ENOTSUPP))
364 dev_err(hsotg->dev, "exit hibernation failed\n");
365
366 /* Change to L0 state */
367 hsotg->lx_state = DWC2_L0;
368 call_gadget(hsotg, resume);
369 } else {
370 /* Change to L0 state */
371 hsotg->lx_state = DWC2_L0;
372 }
373 } else {
374 if (hsotg->core_params->hibernation) {
375 dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
376 return;
377 }
378 if (hsotg->lx_state != DWC2_L1) {
379 u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
380
381 /* Restart the Phy Clock */
382 pcgcctl &= ~PCGCTL_STOPPCLK;
383 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
384 mod_timer(&hsotg->wkp_timer,
385 jiffies + msecs_to_jiffies(71));
386 } else {
387 /* Change to L0 state */
388 hsotg->lx_state = DWC2_L0;
389 }
390 }
391
392 /* Clear interrupt */
393 dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
394 }
395
396 /*
397 * This interrupt indicates that a device has been disconnected from the
398 * root port
399 */
dwc2_handle_disconnect_intr(struct dwc2_hsotg * hsotg)400 static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
401 {
402 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
403 dwc2_is_host_mode(hsotg) ? "Host" : "Device",
404 dwc2_op_state_str(hsotg));
405
406 if (hsotg->op_state == OTG_STATE_A_HOST)
407 dwc2_hcd_disconnect(hsotg);
408
409 dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
410 }
411
412 /*
413 * This interrupt indicates that SUSPEND state has been detected on the USB.
414 *
415 * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
416 * to "a_host".
417 *
418 * When power management is enabled the core will be put in low power mode.
419 */
dwc2_handle_usb_suspend_intr(struct dwc2_hsotg * hsotg)420 static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
421 {
422 u32 dsts;
423 int ret;
424
425 dev_dbg(hsotg->dev, "USB SUSPEND\n");
426
427 if (dwc2_is_device_mode(hsotg)) {
428 /*
429 * Check the Device status register to determine if the Suspend
430 * state is active
431 */
432 dsts = dwc2_readl(hsotg->regs + DSTS);
433 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts);
434 dev_dbg(hsotg->dev,
435 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n",
436 !!(dsts & DSTS_SUSPSTS),
437 hsotg->hw_params.power_optimized);
438 if ((dsts & DSTS_SUSPSTS) && hsotg->hw_params.power_optimized) {
439 /* Ignore suspend request before enumeration */
440 if (!dwc2_is_device_connected(hsotg)) {
441 dev_dbg(hsotg->dev,
442 "ignore suspend request before enumeration\n");
443 goto clear_int;
444 }
445
446 ret = dwc2_enter_hibernation(hsotg);
447 if (ret) {
448 if (ret != -ENOTSUPP)
449 dev_err(hsotg->dev,
450 "enter hibernation failed\n");
451 goto skip_power_saving;
452 }
453
454 udelay(100);
455
456 /* Ask phy to be suspended */
457 if (!IS_ERR_OR_NULL(hsotg->uphy))
458 usb_phy_set_suspend(hsotg->uphy, true);
459 skip_power_saving:
460 /*
461 * Change to L2 (suspend) state before releasing
462 * spinlock
463 */
464 hsotg->lx_state = DWC2_L2;
465
466 /* Call gadget suspend callback */
467 call_gadget(hsotg, suspend);
468 }
469 } else {
470 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
471 dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
472
473 /* Change to L2 (suspend) state */
474 hsotg->lx_state = DWC2_L2;
475 /* Clear the a_peripheral flag, back to a_host */
476 spin_unlock(&hsotg->lock);
477 dwc2_hcd_start(hsotg);
478 spin_lock(&hsotg->lock);
479 hsotg->op_state = OTG_STATE_A_HOST;
480 }
481 }
482
483 clear_int:
484 /* Clear interrupt */
485 dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
486 }
487
488 #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
489 GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \
490 GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \
491 GINTSTS_USBSUSP | GINTSTS_PRTINT)
492
493 /*
494 * This function returns the Core Interrupt register
495 */
dwc2_read_common_intr(struct dwc2_hsotg * hsotg)496 static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
497 {
498 u32 gintsts;
499 u32 gintmsk;
500 u32 gahbcfg;
501 u32 gintmsk_common = GINTMSK_COMMON;
502
503 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
504 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
505 gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
506
507 /* If any common interrupts set */
508 if (gintsts & gintmsk_common)
509 dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n",
510 gintsts, gintmsk);
511
512 if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
513 return gintsts & gintmsk & gintmsk_common;
514 else
515 return 0;
516 }
517
518 /*
519 * Common interrupt handler
520 *
521 * The common interrupts are those that occur in both Host and Device mode.
522 * This handler handles the following interrupts:
523 * - Mode Mismatch Interrupt
524 * - OTG Interrupt
525 * - Connector ID Status Change Interrupt
526 * - Disconnect Interrupt
527 * - Session Request Interrupt
528 * - Resume / Remote Wakeup Detected Interrupt
529 * - Suspend Interrupt
530 */
dwc2_handle_common_intr(int irq,void * dev)531 irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
532 {
533 struct dwc2_hsotg *hsotg = dev;
534 u32 gintsts;
535 irqreturn_t retval = IRQ_NONE;
536
537 spin_lock(&hsotg->lock);
538
539 if (!dwc2_is_controller_alive(hsotg)) {
540 dev_warn(hsotg->dev, "Controller is dead\n");
541 goto out;
542 }
543
544 gintsts = dwc2_read_common_intr(hsotg);
545 if (gintsts & ~GINTSTS_PRTINT)
546 retval = IRQ_HANDLED;
547
548 if (gintsts & GINTSTS_MODEMIS)
549 dwc2_handle_mode_mismatch_intr(hsotg);
550 if (gintsts & GINTSTS_OTGINT)
551 dwc2_handle_otg_intr(hsotg);
552 if (gintsts & GINTSTS_CONIDSTSCHNG)
553 dwc2_handle_conn_id_status_change_intr(hsotg);
554 if (gintsts & GINTSTS_DISCONNINT)
555 dwc2_handle_disconnect_intr(hsotg);
556 if (gintsts & GINTSTS_SESSREQINT)
557 dwc2_handle_session_req_intr(hsotg);
558 if (gintsts & GINTSTS_WKUPINT)
559 dwc2_handle_wakeup_detected_intr(hsotg);
560 if (gintsts & GINTSTS_USBSUSP)
561 dwc2_handle_usb_suspend_intr(hsotg);
562
563 if (gintsts & GINTSTS_PRTINT) {
564 /*
565 * The port interrupt occurs while in device mode with HPRT0
566 * Port Enable/Disable
567 */
568 if (dwc2_is_device_mode(hsotg)) {
569 dev_dbg(hsotg->dev,
570 " --Port interrupt received in Device mode--\n");
571 dwc2_handle_usb_port_intr(hsotg);
572 retval = IRQ_HANDLED;
573 }
574 }
575
576 out:
577 spin_unlock(&hsotg->lock);
578 return retval;
579 }
580