1 /*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/errno.h>
42 #include <linux/list.h>
43 #include <linux/dma-mapping.h>
44
45 #include "musb_core.h"
46 #include "musb_host.h"
47
48 /* MUSB HOST status 22-mar-2006
49 *
50 * - There's still lots of partial code duplication for fault paths, so
51 * they aren't handled as consistently as they need to be.
52 *
53 * - PIO mostly behaved when last tested.
54 * + including ep0, with all usbtest cases 9, 10
55 * + usbtest 14 (ep0out) doesn't seem to run at all
56 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
57 * configurations, but otherwise double buffering passes basic tests.
58 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
59 *
60 * - DMA (CPPI) ... partially behaves, not currently recommended
61 * + about 1/15 the speed of typical EHCI implementations (PCI)
62 * + RX, all too often reqpkt seems to misbehave after tx
63 * + TX, no known issues (other than evident silicon issue)
64 *
65 * - DMA (Mentor/OMAP) ...has at least toggle update problems
66 *
67 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
68 * starvation ... nothing yet for TX, interrupt, or bulk.
69 *
70 * - Not tested with HNP, but some SRP paths seem to behave.
71 *
72 * NOTE 24-August-2006:
73 *
74 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
75 * extra endpoint for periodic use enabling hub + keybd + mouse. That
76 * mostly works, except that with "usbnet" it's easy to trigger cases
77 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
78 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
79 * although ARP RX wins. (That test was done with a full speed link.)
80 */
81
82
83 /*
84 * NOTE on endpoint usage:
85 *
86 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
87 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
88 * (Yes, bulk _could_ use more of the endpoints than that, and would even
89 * benefit from it.)
90 *
91 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
92 * So far that scheduling is both dumb and optimistic: the endpoint will be
93 * "claimed" until its software queue is no longer refilled. No multiplexing
94 * of transfers between endpoints, or anything clever.
95 */
96
hcd_to_musb(struct usb_hcd * hcd)97 struct musb *hcd_to_musb(struct usb_hcd *hcd)
98 {
99 return *(struct musb **) hcd->hcd_priv;
100 }
101
102
103 static void musb_ep_program(struct musb *musb, u8 epnum,
104 struct urb *urb, int is_out,
105 u8 *buf, u32 offset, u32 len);
106
107 /*
108 * Clear TX fifo. Needed to avoid BABBLE errors.
109 */
musb_h_tx_flush_fifo(struct musb_hw_ep * ep)110 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
111 {
112 struct musb *musb = ep->musb;
113 void __iomem *epio = ep->regs;
114 u16 csr;
115 int retries = 1000;
116
117 csr = musb_readw(epio, MUSB_TXCSR);
118 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
119 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY;
120 musb_writew(epio, MUSB_TXCSR, csr);
121 csr = musb_readw(epio, MUSB_TXCSR);
122
123 /*
124 * FIXME: sometimes the tx fifo flush failed, it has been
125 * observed during device disconnect on AM335x.
126 *
127 * To reproduce the issue, ensure tx urb(s) are queued when
128 * unplug the usb device which is connected to AM335x usb
129 * host port.
130 *
131 * I found using a usb-ethernet device and running iperf
132 * (client on AM335x) has very high chance to trigger it.
133 *
134 * Better to turn on dev_dbg() in musb_cleanup_urb() with
135 * CPPI enabled to see the issue when aborting the tx channel.
136 */
137 if (dev_WARN_ONCE(musb->controller, retries-- < 1,
138 "Could not flush host TX%d fifo: csr: %04x\n",
139 ep->epnum, csr))
140 return;
141 mdelay(1);
142 }
143 }
144
musb_h_ep0_flush_fifo(struct musb_hw_ep * ep)145 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
146 {
147 void __iomem *epio = ep->regs;
148 u16 csr;
149 int retries = 5;
150
151 /* scrub any data left in the fifo */
152 do {
153 csr = musb_readw(epio, MUSB_TXCSR);
154 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
155 break;
156 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
157 csr = musb_readw(epio, MUSB_TXCSR);
158 udelay(10);
159 } while (--retries);
160
161 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
162 ep->epnum, csr);
163
164 /* and reset for the next transfer */
165 musb_writew(epio, MUSB_TXCSR, 0);
166 }
167
168 /*
169 * Start transmit. Caller is responsible for locking shared resources.
170 * musb must be locked.
171 */
musb_h_tx_start(struct musb_hw_ep * ep)172 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
173 {
174 u16 txcsr;
175
176 /* NOTE: no locks here; caller should lock and select EP */
177 if (ep->epnum) {
178 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
179 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
180 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
181 } else {
182 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
183 musb_writew(ep->regs, MUSB_CSR0, txcsr);
184 }
185
186 }
187
musb_h_tx_dma_start(struct musb_hw_ep * ep)188 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
189 {
190 u16 txcsr;
191
192 /* NOTE: no locks here; caller should lock and select EP */
193 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
194 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
195 if (is_cppi_enabled(ep->musb))
196 txcsr |= MUSB_TXCSR_DMAMODE;
197 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
198 }
199
musb_ep_set_qh(struct musb_hw_ep * ep,int is_in,struct musb_qh * qh)200 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
201 {
202 if (is_in != 0 || ep->is_shared_fifo)
203 ep->in_qh = qh;
204 if (is_in == 0 || ep->is_shared_fifo)
205 ep->out_qh = qh;
206 }
207
musb_ep_get_qh(struct musb_hw_ep * ep,int is_in)208 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
209 {
210 return is_in ? ep->in_qh : ep->out_qh;
211 }
212
213 /*
214 * Start the URB at the front of an endpoint's queue
215 * end must be claimed from the caller.
216 *
217 * Context: controller locked, irqs blocked
218 */
219 static void
musb_start_urb(struct musb * musb,int is_in,struct musb_qh * qh)220 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
221 {
222 u16 frame;
223 u32 len;
224 void __iomem *mbase = musb->mregs;
225 struct urb *urb = next_urb(qh);
226 void *buf = urb->transfer_buffer;
227 u32 offset = 0;
228 struct musb_hw_ep *hw_ep = qh->hw_ep;
229 unsigned pipe = urb->pipe;
230 u8 address = usb_pipedevice(pipe);
231 int epnum = hw_ep->epnum;
232
233 /* initialize software qh state */
234 qh->offset = 0;
235 qh->segsize = 0;
236
237 /* gather right source of data */
238 switch (qh->type) {
239 case USB_ENDPOINT_XFER_CONTROL:
240 /* control transfers always start with SETUP */
241 is_in = 0;
242 musb->ep0_stage = MUSB_EP0_START;
243 buf = urb->setup_packet;
244 len = 8;
245 break;
246 case USB_ENDPOINT_XFER_ISOC:
247 qh->iso_idx = 0;
248 qh->frame = 0;
249 offset = urb->iso_frame_desc[0].offset;
250 len = urb->iso_frame_desc[0].length;
251 break;
252 default: /* bulk, interrupt */
253 /* actual_length may be nonzero on retry paths */
254 buf = urb->transfer_buffer + urb->actual_length;
255 len = urb->transfer_buffer_length - urb->actual_length;
256 }
257
258 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
259 qh, urb, address, qh->epnum,
260 is_in ? "in" : "out",
261 ({char *s; switch (qh->type) {
262 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
263 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
264 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
265 default: s = "-intr"; break;
266 } s; }),
267 epnum, buf + offset, len);
268
269 /* Configure endpoint */
270 musb_ep_set_qh(hw_ep, is_in, qh);
271 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
272
273 /* transmit may have more work: start it when it is time */
274 if (is_in)
275 return;
276
277 /* determine if the time is right for a periodic transfer */
278 switch (qh->type) {
279 case USB_ENDPOINT_XFER_ISOC:
280 case USB_ENDPOINT_XFER_INT:
281 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
282 frame = musb_readw(mbase, MUSB_FRAME);
283 /* FIXME this doesn't implement that scheduling policy ...
284 * or handle framecounter wrapping
285 */
286 if (1) { /* Always assume URB_ISO_ASAP */
287 /* REVISIT the SOF irq handler shouldn't duplicate
288 * this code; and we don't init urb->start_frame...
289 */
290 qh->frame = 0;
291 goto start;
292 } else {
293 qh->frame = urb->start_frame;
294 /* enable SOF interrupt so we can count down */
295 dev_dbg(musb->controller, "SOF for %d\n", epnum);
296 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
297 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
298 #endif
299 }
300 break;
301 default:
302 start:
303 dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
304 hw_ep->tx_channel ? "dma" : "pio");
305
306 if (!hw_ep->tx_channel)
307 musb_h_tx_start(hw_ep);
308 else if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
309 musb_h_tx_dma_start(hw_ep);
310 }
311 }
312
313 /* Context: caller owns controller lock, IRQs are blocked */
musb_giveback(struct musb * musb,struct urb * urb,int status)314 static void musb_giveback(struct musb *musb, struct urb *urb, int status)
315 __releases(musb->lock)
316 __acquires(musb->lock)
317 {
318 dev_dbg(musb->controller,
319 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
320 urb, urb->complete, status,
321 usb_pipedevice(urb->pipe),
322 usb_pipeendpoint(urb->pipe),
323 usb_pipein(urb->pipe) ? "in" : "out",
324 urb->actual_length, urb->transfer_buffer_length
325 );
326
327 usb_hcd_unlink_urb_from_ep(musb->hcd, urb);
328 spin_unlock(&musb->lock);
329 usb_hcd_giveback_urb(musb->hcd, urb, status);
330 spin_lock(&musb->lock);
331 }
332
333 /* For bulk/interrupt endpoints only */
musb_save_toggle(struct musb_qh * qh,int is_in,struct urb * urb)334 static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
335 struct urb *urb)
336 {
337 void __iomem *epio = qh->hw_ep->regs;
338 u16 csr;
339
340 /*
341 * FIXME: the current Mentor DMA code seems to have
342 * problems getting toggle correct.
343 */
344
345 if (is_in)
346 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
347 else
348 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
349
350 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
351 }
352
353 /*
354 * Advance this hardware endpoint's queue, completing the specified URB and
355 * advancing to either the next URB queued to that qh, or else invalidating
356 * that qh and advancing to the next qh scheduled after the current one.
357 *
358 * Context: caller owns controller lock, IRQs are blocked
359 */
musb_advance_schedule(struct musb * musb,struct urb * urb,struct musb_hw_ep * hw_ep,int is_in)360 static void musb_advance_schedule(struct musb *musb, struct urb *urb,
361 struct musb_hw_ep *hw_ep, int is_in)
362 {
363 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
364 struct musb_hw_ep *ep = qh->hw_ep;
365 int ready = qh->is_ready;
366 int status;
367
368 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
369
370 /* save toggle eagerly, for paranoia */
371 switch (qh->type) {
372 case USB_ENDPOINT_XFER_BULK:
373 case USB_ENDPOINT_XFER_INT:
374 musb_save_toggle(qh, is_in, urb);
375 break;
376 case USB_ENDPOINT_XFER_ISOC:
377 if (status == 0 && urb->error_count)
378 status = -EXDEV;
379 break;
380 }
381
382 qh->is_ready = 0;
383 musb_giveback(musb, urb, status);
384 qh->is_ready = ready;
385
386 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
387 * invalidate qh as soon as list_empty(&hep->urb_list)
388 */
389 if (list_empty(&qh->hep->urb_list)) {
390 struct list_head *head;
391 struct dma_controller *dma = musb->dma_controller;
392
393 if (is_in) {
394 ep->rx_reinit = 1;
395 if (ep->rx_channel) {
396 dma->channel_release(ep->rx_channel);
397 ep->rx_channel = NULL;
398 }
399 } else {
400 ep->tx_reinit = 1;
401 if (ep->tx_channel) {
402 dma->channel_release(ep->tx_channel);
403 ep->tx_channel = NULL;
404 }
405 }
406
407 /* Clobber old pointers to this qh */
408 musb_ep_set_qh(ep, is_in, NULL);
409 qh->hep->hcpriv = NULL;
410
411 switch (qh->type) {
412
413 case USB_ENDPOINT_XFER_CONTROL:
414 case USB_ENDPOINT_XFER_BULK:
415 /* fifo policy for these lists, except that NAKing
416 * should rotate a qh to the end (for fairness).
417 */
418 if (qh->mux == 1) {
419 head = qh->ring.prev;
420 list_del(&qh->ring);
421 kfree(qh);
422 qh = first_qh(head);
423 break;
424 }
425
426 case USB_ENDPOINT_XFER_ISOC:
427 case USB_ENDPOINT_XFER_INT:
428 /* this is where periodic bandwidth should be
429 * de-allocated if it's tracked and allocated;
430 * and where we'd update the schedule tree...
431 */
432 kfree(qh);
433 qh = NULL;
434 break;
435 }
436 }
437
438 if (qh != NULL && qh->is_ready) {
439 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
440 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
441 musb_start_urb(musb, is_in, qh);
442 }
443 }
444
musb_h_flush_rxfifo(struct musb_hw_ep * hw_ep,u16 csr)445 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
446 {
447 /* we don't want fifo to fill itself again;
448 * ignore dma (various models),
449 * leave toggle alone (may not have been saved yet)
450 */
451 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
452 csr &= ~(MUSB_RXCSR_H_REQPKT
453 | MUSB_RXCSR_H_AUTOREQ
454 | MUSB_RXCSR_AUTOCLEAR);
455
456 /* write 2x to allow double buffering */
457 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
458 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
459
460 /* flush writebuffer */
461 return musb_readw(hw_ep->regs, MUSB_RXCSR);
462 }
463
464 /*
465 * PIO RX for a packet (or part of it).
466 */
467 static bool
musb_host_packet_rx(struct musb * musb,struct urb * urb,u8 epnum,u8 iso_err)468 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
469 {
470 u16 rx_count;
471 u8 *buf;
472 u16 csr;
473 bool done = false;
474 u32 length;
475 int do_flush = 0;
476 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
477 void __iomem *epio = hw_ep->regs;
478 struct musb_qh *qh = hw_ep->in_qh;
479 int pipe = urb->pipe;
480 void *buffer = urb->transfer_buffer;
481
482 /* musb_ep_select(mbase, epnum); */
483 rx_count = musb_readw(epio, MUSB_RXCOUNT);
484 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
485 urb->transfer_buffer, qh->offset,
486 urb->transfer_buffer_length);
487
488 /* unload FIFO */
489 if (usb_pipeisoc(pipe)) {
490 int status = 0;
491 struct usb_iso_packet_descriptor *d;
492
493 if (iso_err) {
494 status = -EILSEQ;
495 urb->error_count++;
496 }
497
498 d = urb->iso_frame_desc + qh->iso_idx;
499 buf = buffer + d->offset;
500 length = d->length;
501 if (rx_count > length) {
502 if (status == 0) {
503 status = -EOVERFLOW;
504 urb->error_count++;
505 }
506 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
507 do_flush = 1;
508 } else
509 length = rx_count;
510 urb->actual_length += length;
511 d->actual_length = length;
512
513 d->status = status;
514
515 /* see if we are done */
516 done = (++qh->iso_idx >= urb->number_of_packets);
517 } else {
518 /* non-isoch */
519 buf = buffer + qh->offset;
520 length = urb->transfer_buffer_length - qh->offset;
521 if (rx_count > length) {
522 if (urb->status == -EINPROGRESS)
523 urb->status = -EOVERFLOW;
524 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
525 do_flush = 1;
526 } else
527 length = rx_count;
528 urb->actual_length += length;
529 qh->offset += length;
530
531 /* see if we are done */
532 done = (urb->actual_length == urb->transfer_buffer_length)
533 || (rx_count < qh->maxpacket)
534 || (urb->status != -EINPROGRESS);
535 if (done
536 && (urb->status == -EINPROGRESS)
537 && (urb->transfer_flags & URB_SHORT_NOT_OK)
538 && (urb->actual_length
539 < urb->transfer_buffer_length))
540 urb->status = -EREMOTEIO;
541 }
542
543 musb_read_fifo(hw_ep, length, buf);
544
545 csr = musb_readw(epio, MUSB_RXCSR);
546 csr |= MUSB_RXCSR_H_WZC_BITS;
547 if (unlikely(do_flush))
548 musb_h_flush_rxfifo(hw_ep, csr);
549 else {
550 /* REVISIT this assumes AUTOCLEAR is never set */
551 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
552 if (!done)
553 csr |= MUSB_RXCSR_H_REQPKT;
554 musb_writew(epio, MUSB_RXCSR, csr);
555 }
556
557 return done;
558 }
559
560 /* we don't always need to reinit a given side of an endpoint...
561 * when we do, use tx/rx reinit routine and then construct a new CSR
562 * to address data toggle, NYET, and DMA or PIO.
563 *
564 * it's possible that driver bugs (especially for DMA) or aborting a
565 * transfer might have left the endpoint busier than it should be.
566 * the busy/not-empty tests are basically paranoia.
567 */
568 static void
musb_rx_reinit(struct musb * musb,struct musb_qh * qh,u8 epnum)569 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, u8 epnum)
570 {
571 struct musb_hw_ep *ep = musb->endpoints + epnum;
572 u16 csr;
573
574 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
575 * That always uses tx_reinit since ep0 repurposes TX register
576 * offsets; the initial SETUP packet is also a kind of OUT.
577 */
578
579 /* if programmed for Tx, put it in RX mode */
580 if (ep->is_shared_fifo) {
581 csr = musb_readw(ep->regs, MUSB_TXCSR);
582 if (csr & MUSB_TXCSR_MODE) {
583 musb_h_tx_flush_fifo(ep);
584 csr = musb_readw(ep->regs, MUSB_TXCSR);
585 musb_writew(ep->regs, MUSB_TXCSR,
586 csr | MUSB_TXCSR_FRCDATATOG);
587 }
588
589 /*
590 * Clear the MODE bit (and everything else) to enable Rx.
591 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
592 */
593 if (csr & MUSB_TXCSR_DMAMODE)
594 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
595 musb_writew(ep->regs, MUSB_TXCSR, 0);
596
597 /* scrub all previous state, clearing toggle */
598 }
599 csr = musb_readw(ep->regs, MUSB_RXCSR);
600 if (csr & MUSB_RXCSR_RXPKTRDY)
601 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
602 musb_readw(ep->regs, MUSB_RXCOUNT));
603
604 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
605
606 /* target addr and (for multipoint) hub addr/port */
607 if (musb->is_multipoint) {
608 musb_write_rxfunaddr(musb, epnum, qh->addr_reg);
609 musb_write_rxhubaddr(musb, epnum, qh->h_addr_reg);
610 musb_write_rxhubport(musb, epnum, qh->h_port_reg);
611 } else
612 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
613
614 /* protocol/endpoint, interval/NAKlimit, i/o size */
615 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
616 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
617 /* NOTE: bulk combining rewrites high bits of maxpacket */
618 /* Set RXMAXP with the FIFO size of the endpoint
619 * to disable double buffer mode.
620 */
621 if (musb->double_buffer_not_ok)
622 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
623 else
624 musb_writew(ep->regs, MUSB_RXMAXP,
625 qh->maxpacket | ((qh->hb_mult - 1) << 11));
626
627 ep->rx_reinit = 0;
628 }
629
musb_tx_dma_set_mode_mentor(struct dma_controller * dma,struct musb_hw_ep * hw_ep,struct musb_qh * qh,struct urb * urb,u32 offset,u32 * length,u8 * mode)630 static int musb_tx_dma_set_mode_mentor(struct dma_controller *dma,
631 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
632 struct urb *urb, u32 offset,
633 u32 *length, u8 *mode)
634 {
635 struct dma_channel *channel = hw_ep->tx_channel;
636 void __iomem *epio = hw_ep->regs;
637 u16 pkt_size = qh->maxpacket;
638 u16 csr;
639
640 if (*length > channel->max_len)
641 *length = channel->max_len;
642
643 csr = musb_readw(epio, MUSB_TXCSR);
644 if (*length > pkt_size) {
645 *mode = 1;
646 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
647 /* autoset shouldn't be set in high bandwidth */
648 /*
649 * Enable Autoset according to table
650 * below
651 * bulk_split hb_mult Autoset_Enable
652 * 0 1 Yes(Normal)
653 * 0 >1 No(High BW ISO)
654 * 1 1 Yes(HS bulk)
655 * 1 >1 Yes(FS bulk)
656 */
657 if (qh->hb_mult == 1 || (qh->hb_mult > 1 &&
658 can_bulk_split(hw_ep->musb, qh->type)))
659 csr |= MUSB_TXCSR_AUTOSET;
660 } else {
661 *mode = 0;
662 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
663 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
664 }
665 channel->desired_mode = *mode;
666 musb_writew(epio, MUSB_TXCSR, csr);
667
668 return 0;
669 }
670
musb_tx_dma_set_mode_cppi_tusb(struct dma_controller * dma,struct musb_hw_ep * hw_ep,struct musb_qh * qh,struct urb * urb,u32 offset,u32 * length,u8 * mode)671 static int musb_tx_dma_set_mode_cppi_tusb(struct dma_controller *dma,
672 struct musb_hw_ep *hw_ep,
673 struct musb_qh *qh,
674 struct urb *urb,
675 u32 offset,
676 u32 *length,
677 u8 *mode)
678 {
679 struct dma_channel *channel = hw_ep->tx_channel;
680
681 if (!is_cppi_enabled(hw_ep->musb) && !tusb_dma_omap(hw_ep->musb))
682 return -ENODEV;
683
684 channel->actual_len = 0;
685
686 /*
687 * TX uses "RNDIS" mode automatically but needs help
688 * to identify the zero-length-final-packet case.
689 */
690 *mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
691
692 return 0;
693 }
694
musb_tx_dma_program(struct dma_controller * dma,struct musb_hw_ep * hw_ep,struct musb_qh * qh,struct urb * urb,u32 offset,u32 length)695 static bool musb_tx_dma_program(struct dma_controller *dma,
696 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
697 struct urb *urb, u32 offset, u32 length)
698 {
699 struct dma_channel *channel = hw_ep->tx_channel;
700 u16 pkt_size = qh->maxpacket;
701 u8 mode;
702 int res;
703
704 if (musb_dma_inventra(hw_ep->musb) || musb_dma_ux500(hw_ep->musb))
705 res = musb_tx_dma_set_mode_mentor(dma, hw_ep, qh, urb,
706 offset, &length, &mode);
707 else
708 res = musb_tx_dma_set_mode_cppi_tusb(dma, hw_ep, qh, urb,
709 offset, &length, &mode);
710 if (res)
711 return false;
712
713 qh->segsize = length;
714
715 /*
716 * Ensure the data reaches to main memory before starting
717 * DMA transfer
718 */
719 wmb();
720
721 if (!dma->channel_program(channel, pkt_size, mode,
722 urb->transfer_dma + offset, length)) {
723 void __iomem *epio = hw_ep->regs;
724 u16 csr;
725
726 dma->channel_release(channel);
727 hw_ep->tx_channel = NULL;
728
729 csr = musb_readw(epio, MUSB_TXCSR);
730 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
731 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
732 return false;
733 }
734 return true;
735 }
736
737 /*
738 * Program an HDRC endpoint as per the given URB
739 * Context: irqs blocked, controller lock held
740 */
musb_ep_program(struct musb * musb,u8 epnum,struct urb * urb,int is_out,u8 * buf,u32 offset,u32 len)741 static void musb_ep_program(struct musb *musb, u8 epnum,
742 struct urb *urb, int is_out,
743 u8 *buf, u32 offset, u32 len)
744 {
745 struct dma_controller *dma_controller;
746 struct dma_channel *dma_channel;
747 u8 dma_ok;
748 void __iomem *mbase = musb->mregs;
749 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
750 void __iomem *epio = hw_ep->regs;
751 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
752 u16 packet_sz = qh->maxpacket;
753 u8 use_dma = 1;
754 u16 csr;
755
756 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
757 "h_addr%02x h_port%02x bytes %d\n",
758 is_out ? "-->" : "<--",
759 epnum, urb, urb->dev->speed,
760 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
761 qh->h_addr_reg, qh->h_port_reg,
762 len);
763
764 musb_ep_select(mbase, epnum);
765
766 if (is_out && !len) {
767 use_dma = 0;
768 csr = musb_readw(epio, MUSB_TXCSR);
769 csr &= ~MUSB_TXCSR_DMAENAB;
770 musb_writew(epio, MUSB_TXCSR, csr);
771 hw_ep->tx_channel = NULL;
772 }
773
774 /* candidate for DMA? */
775 dma_controller = musb->dma_controller;
776 if (use_dma && is_dma_capable() && epnum && dma_controller) {
777 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
778 if (!dma_channel) {
779 dma_channel = dma_controller->channel_alloc(
780 dma_controller, hw_ep, is_out);
781 if (is_out)
782 hw_ep->tx_channel = dma_channel;
783 else
784 hw_ep->rx_channel = dma_channel;
785 }
786 } else
787 dma_channel = NULL;
788
789 /* make sure we clear DMAEnab, autoSet bits from previous run */
790
791 /* OUT/transmit/EP0 or IN/receive? */
792 if (is_out) {
793 u16 csr;
794 u16 int_txe;
795 u16 load_count;
796
797 csr = musb_readw(epio, MUSB_TXCSR);
798
799 /* disable interrupt in case we flush */
800 int_txe = musb->intrtxe;
801 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
802
803 /* general endpoint setup */
804 if (epnum) {
805 /* flush all old state, set default */
806 /*
807 * We could be flushing valid
808 * packets in double buffering
809 * case
810 */
811 if (!hw_ep->tx_double_buffered)
812 musb_h_tx_flush_fifo(hw_ep);
813
814 /*
815 * We must not clear the DMAMODE bit before or in
816 * the same cycle with the DMAENAB bit, so we clear
817 * the latter first...
818 */
819 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
820 | MUSB_TXCSR_AUTOSET
821 | MUSB_TXCSR_DMAENAB
822 | MUSB_TXCSR_FRCDATATOG
823 | MUSB_TXCSR_H_RXSTALL
824 | MUSB_TXCSR_H_ERROR
825 | MUSB_TXCSR_TXPKTRDY
826 );
827 csr |= MUSB_TXCSR_MODE;
828
829 if (!hw_ep->tx_double_buffered) {
830 if (usb_gettoggle(urb->dev, qh->epnum, 1))
831 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
832 | MUSB_TXCSR_H_DATATOGGLE;
833 else
834 csr |= MUSB_TXCSR_CLRDATATOG;
835 }
836
837 musb_writew(epio, MUSB_TXCSR, csr);
838 /* REVISIT may need to clear FLUSHFIFO ... */
839 csr &= ~MUSB_TXCSR_DMAMODE;
840 musb_writew(epio, MUSB_TXCSR, csr);
841 csr = musb_readw(epio, MUSB_TXCSR);
842 } else {
843 /* endpoint 0: just flush */
844 musb_h_ep0_flush_fifo(hw_ep);
845 }
846
847 /* target addr and (for multipoint) hub addr/port */
848 if (musb->is_multipoint) {
849 musb_write_txfunaddr(musb, epnum, qh->addr_reg);
850 musb_write_txhubaddr(musb, epnum, qh->h_addr_reg);
851 musb_write_txhubport(musb, epnum, qh->h_port_reg);
852 /* FIXME if !epnum, do the same for RX ... */
853 } else
854 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
855
856 /* protocol/endpoint/interval/NAKlimit */
857 if (epnum) {
858 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
859 if (musb->double_buffer_not_ok) {
860 musb_writew(epio, MUSB_TXMAXP,
861 hw_ep->max_packet_sz_tx);
862 } else if (can_bulk_split(musb, qh->type)) {
863 qh->hb_mult = hw_ep->max_packet_sz_tx
864 / packet_sz;
865 musb_writew(epio, MUSB_TXMAXP, packet_sz
866 | ((qh->hb_mult) - 1) << 11);
867 } else {
868 musb_writew(epio, MUSB_TXMAXP,
869 qh->maxpacket |
870 ((qh->hb_mult - 1) << 11));
871 }
872 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
873 } else {
874 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
875 if (musb->is_multipoint)
876 musb_writeb(epio, MUSB_TYPE0,
877 qh->type_reg);
878 }
879
880 if (can_bulk_split(musb, qh->type))
881 load_count = min((u32) hw_ep->max_packet_sz_tx,
882 len);
883 else
884 load_count = min((u32) packet_sz, len);
885
886 if (dma_channel && musb_tx_dma_program(dma_controller,
887 hw_ep, qh, urb, offset, len))
888 load_count = 0;
889
890 if (load_count) {
891 /* PIO to load FIFO */
892 qh->segsize = load_count;
893 if (!buf) {
894 sg_miter_start(&qh->sg_miter, urb->sg, 1,
895 SG_MITER_ATOMIC
896 | SG_MITER_FROM_SG);
897 if (!sg_miter_next(&qh->sg_miter)) {
898 dev_err(musb->controller,
899 "error: sg"
900 "list empty\n");
901 sg_miter_stop(&qh->sg_miter);
902 goto finish;
903 }
904 buf = qh->sg_miter.addr + urb->sg->offset +
905 urb->actual_length;
906 load_count = min_t(u32, load_count,
907 qh->sg_miter.length);
908 musb_write_fifo(hw_ep, load_count, buf);
909 qh->sg_miter.consumed = load_count;
910 sg_miter_stop(&qh->sg_miter);
911 } else
912 musb_write_fifo(hw_ep, load_count, buf);
913 }
914 finish:
915 /* re-enable interrupt */
916 musb_writew(mbase, MUSB_INTRTXE, int_txe);
917
918 /* IN/receive */
919 } else {
920 u16 csr;
921
922 if (hw_ep->rx_reinit) {
923 musb_rx_reinit(musb, qh, epnum);
924
925 /* init new state: toggle and NYET, maybe DMA later */
926 if (usb_gettoggle(urb->dev, qh->epnum, 0))
927 csr = MUSB_RXCSR_H_WR_DATATOGGLE
928 | MUSB_RXCSR_H_DATATOGGLE;
929 else
930 csr = 0;
931 if (qh->type == USB_ENDPOINT_XFER_INT)
932 csr |= MUSB_RXCSR_DISNYET;
933
934 } else {
935 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
936
937 if (csr & (MUSB_RXCSR_RXPKTRDY
938 | MUSB_RXCSR_DMAENAB
939 | MUSB_RXCSR_H_REQPKT))
940 ERR("broken !rx_reinit, ep%d csr %04x\n",
941 hw_ep->epnum, csr);
942
943 /* scrub any stale state, leaving toggle alone */
944 csr &= MUSB_RXCSR_DISNYET;
945 }
946
947 /* kick things off */
948
949 if ((is_cppi_enabled(musb) || tusb_dma_omap(musb)) && dma_channel) {
950 /* Candidate for DMA */
951 dma_channel->actual_len = 0L;
952 qh->segsize = len;
953
954 /* AUTOREQ is in a DMA register */
955 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
956 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
957
958 /*
959 * Unless caller treats short RX transfers as
960 * errors, we dare not queue multiple transfers.
961 */
962 dma_ok = dma_controller->channel_program(dma_channel,
963 packet_sz, !(urb->transfer_flags &
964 URB_SHORT_NOT_OK),
965 urb->transfer_dma + offset,
966 qh->segsize);
967 if (!dma_ok) {
968 dma_controller->channel_release(dma_channel);
969 hw_ep->rx_channel = dma_channel = NULL;
970 } else
971 csr |= MUSB_RXCSR_DMAENAB;
972 }
973
974 csr |= MUSB_RXCSR_H_REQPKT;
975 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
976 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
977 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
978 }
979 }
980
981 /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to
982 * the end; avoids starvation for other endpoints.
983 */
musb_bulk_nak_timeout(struct musb * musb,struct musb_hw_ep * ep,int is_in)984 static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep,
985 int is_in)
986 {
987 struct dma_channel *dma;
988 struct urb *urb;
989 void __iomem *mbase = musb->mregs;
990 void __iomem *epio = ep->regs;
991 struct musb_qh *cur_qh, *next_qh;
992 u16 rx_csr, tx_csr;
993
994 musb_ep_select(mbase, ep->epnum);
995 if (is_in) {
996 dma = is_dma_capable() ? ep->rx_channel : NULL;
997
998 /*
999 * Need to stop the transaction by clearing REQPKT first
1000 * then the NAK Timeout bit ref MUSBMHDRC USB 2.0 HIGH-SPEED
1001 * DUAL-ROLE CONTROLLER Programmer's Guide, section 9.2.2
1002 */
1003 rx_csr = musb_readw(epio, MUSB_RXCSR);
1004 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1005 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1006 musb_writew(epio, MUSB_RXCSR, rx_csr);
1007 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1008 musb_writew(epio, MUSB_RXCSR, rx_csr);
1009
1010 cur_qh = first_qh(&musb->in_bulk);
1011 } else {
1012 dma = is_dma_capable() ? ep->tx_channel : NULL;
1013
1014 /* clear nak timeout bit */
1015 tx_csr = musb_readw(epio, MUSB_TXCSR);
1016 tx_csr |= MUSB_TXCSR_H_WZC_BITS;
1017 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;
1018 musb_writew(epio, MUSB_TXCSR, tx_csr);
1019
1020 cur_qh = first_qh(&musb->out_bulk);
1021 }
1022 if (cur_qh) {
1023 urb = next_urb(cur_qh);
1024 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1025 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1026 musb->dma_controller->channel_abort(dma);
1027 urb->actual_length += dma->actual_len;
1028 dma->actual_len = 0L;
1029 }
1030 musb_save_toggle(cur_qh, is_in, urb);
1031
1032 if (is_in) {
1033 /* move cur_qh to end of queue */
1034 list_move_tail(&cur_qh->ring, &musb->in_bulk);
1035
1036 /* get the next qh from musb->in_bulk */
1037 next_qh = first_qh(&musb->in_bulk);
1038
1039 /* set rx_reinit and schedule the next qh */
1040 ep->rx_reinit = 1;
1041 } else {
1042 /* move cur_qh to end of queue */
1043 list_move_tail(&cur_qh->ring, &musb->out_bulk);
1044
1045 /* get the next qh from musb->out_bulk */
1046 next_qh = first_qh(&musb->out_bulk);
1047
1048 /* set tx_reinit and schedule the next qh */
1049 ep->tx_reinit = 1;
1050 }
1051
1052 if (next_qh)
1053 musb_start_urb(musb, is_in, next_qh);
1054 }
1055 }
1056
1057 /*
1058 * Service the default endpoint (ep0) as host.
1059 * Return true until it's time to start the status stage.
1060 */
musb_h_ep0_continue(struct musb * musb,u16 len,struct urb * urb)1061 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
1062 {
1063 bool more = false;
1064 u8 *fifo_dest = NULL;
1065 u16 fifo_count = 0;
1066 struct musb_hw_ep *hw_ep = musb->control_ep;
1067 struct musb_qh *qh = hw_ep->in_qh;
1068 struct usb_ctrlrequest *request;
1069
1070 switch (musb->ep0_stage) {
1071 case MUSB_EP0_IN:
1072 fifo_dest = urb->transfer_buffer + urb->actual_length;
1073 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
1074 urb->actual_length);
1075 if (fifo_count < len)
1076 urb->status = -EOVERFLOW;
1077
1078 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
1079
1080 urb->actual_length += fifo_count;
1081 if (len < qh->maxpacket) {
1082 /* always terminate on short read; it's
1083 * rarely reported as an error.
1084 */
1085 } else if (urb->actual_length <
1086 urb->transfer_buffer_length)
1087 more = true;
1088 break;
1089 case MUSB_EP0_START:
1090 request = (struct usb_ctrlrequest *) urb->setup_packet;
1091
1092 if (!request->wLength) {
1093 dev_dbg(musb->controller, "start no-DATA\n");
1094 break;
1095 } else if (request->bRequestType & USB_DIR_IN) {
1096 dev_dbg(musb->controller, "start IN-DATA\n");
1097 musb->ep0_stage = MUSB_EP0_IN;
1098 more = true;
1099 break;
1100 } else {
1101 dev_dbg(musb->controller, "start OUT-DATA\n");
1102 musb->ep0_stage = MUSB_EP0_OUT;
1103 more = true;
1104 }
1105 /* FALLTHROUGH */
1106 case MUSB_EP0_OUT:
1107 fifo_count = min_t(size_t, qh->maxpacket,
1108 urb->transfer_buffer_length -
1109 urb->actual_length);
1110 if (fifo_count) {
1111 fifo_dest = (u8 *) (urb->transfer_buffer
1112 + urb->actual_length);
1113 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
1114 fifo_count,
1115 (fifo_count == 1) ? "" : "s",
1116 fifo_dest);
1117 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
1118
1119 urb->actual_length += fifo_count;
1120 more = true;
1121 }
1122 break;
1123 default:
1124 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
1125 break;
1126 }
1127
1128 return more;
1129 }
1130
1131 /*
1132 * Handle default endpoint interrupt as host. Only called in IRQ time
1133 * from musb_interrupt().
1134 *
1135 * called with controller irqlocked
1136 */
musb_h_ep0_irq(struct musb * musb)1137 irqreturn_t musb_h_ep0_irq(struct musb *musb)
1138 {
1139 struct urb *urb;
1140 u16 csr, len;
1141 int status = 0;
1142 void __iomem *mbase = musb->mregs;
1143 struct musb_hw_ep *hw_ep = musb->control_ep;
1144 void __iomem *epio = hw_ep->regs;
1145 struct musb_qh *qh = hw_ep->in_qh;
1146 bool complete = false;
1147 irqreturn_t retval = IRQ_NONE;
1148
1149 /* ep0 only has one queue, "in" */
1150 urb = next_urb(qh);
1151
1152 musb_ep_select(mbase, 0);
1153 csr = musb_readw(epio, MUSB_CSR0);
1154 len = (csr & MUSB_CSR0_RXPKTRDY)
1155 ? musb_readb(epio, MUSB_COUNT0)
1156 : 0;
1157
1158 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1159 csr, qh, len, urb, musb->ep0_stage);
1160
1161 /* if we just did status stage, we are done */
1162 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1163 retval = IRQ_HANDLED;
1164 complete = true;
1165 }
1166
1167 /* prepare status */
1168 if (csr & MUSB_CSR0_H_RXSTALL) {
1169 dev_dbg(musb->controller, "STALLING ENDPOINT\n");
1170 status = -EPIPE;
1171
1172 } else if (csr & MUSB_CSR0_H_ERROR) {
1173 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
1174 status = -EPROTO;
1175
1176 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1177 dev_dbg(musb->controller, "control NAK timeout\n");
1178
1179 /* NOTE: this code path would be a good place to PAUSE a
1180 * control transfer, if another one is queued, so that
1181 * ep0 is more likely to stay busy. That's already done
1182 * for bulk RX transfers.
1183 *
1184 * if (qh->ring.next != &musb->control), then
1185 * we have a candidate... NAKing is *NOT* an error
1186 */
1187 musb_writew(epio, MUSB_CSR0, 0);
1188 retval = IRQ_HANDLED;
1189 }
1190
1191 if (status) {
1192 dev_dbg(musb->controller, "aborting\n");
1193 retval = IRQ_HANDLED;
1194 if (urb)
1195 urb->status = status;
1196 complete = true;
1197
1198 /* use the proper sequence to abort the transfer */
1199 if (csr & MUSB_CSR0_H_REQPKT) {
1200 csr &= ~MUSB_CSR0_H_REQPKT;
1201 musb_writew(epio, MUSB_CSR0, csr);
1202 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1203 musb_writew(epio, MUSB_CSR0, csr);
1204 } else {
1205 musb_h_ep0_flush_fifo(hw_ep);
1206 }
1207
1208 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1209
1210 /* clear it */
1211 musb_writew(epio, MUSB_CSR0, 0);
1212 }
1213
1214 if (unlikely(!urb)) {
1215 /* stop endpoint since we have no place for its data, this
1216 * SHOULD NEVER HAPPEN! */
1217 ERR("no URB for end 0\n");
1218
1219 musb_h_ep0_flush_fifo(hw_ep);
1220 goto done;
1221 }
1222
1223 if (!complete) {
1224 /* call common logic and prepare response */
1225 if (musb_h_ep0_continue(musb, len, urb)) {
1226 /* more packets required */
1227 csr = (MUSB_EP0_IN == musb->ep0_stage)
1228 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1229 } else {
1230 /* data transfer complete; perform status phase */
1231 if (usb_pipeout(urb->pipe)
1232 || !urb->transfer_buffer_length)
1233 csr = MUSB_CSR0_H_STATUSPKT
1234 | MUSB_CSR0_H_REQPKT;
1235 else
1236 csr = MUSB_CSR0_H_STATUSPKT
1237 | MUSB_CSR0_TXPKTRDY;
1238
1239 /* disable ping token in status phase */
1240 csr |= MUSB_CSR0_H_DIS_PING;
1241
1242 /* flag status stage */
1243 musb->ep0_stage = MUSB_EP0_STATUS;
1244
1245 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
1246
1247 }
1248 musb_writew(epio, MUSB_CSR0, csr);
1249 retval = IRQ_HANDLED;
1250 } else
1251 musb->ep0_stage = MUSB_EP0_IDLE;
1252
1253 /* call completion handler if done */
1254 if (complete)
1255 musb_advance_schedule(musb, urb, hw_ep, 1);
1256 done:
1257 return retval;
1258 }
1259
1260
1261 #ifdef CONFIG_USB_INVENTRA_DMA
1262
1263 /* Host side TX (OUT) using Mentor DMA works as follows:
1264 submit_urb ->
1265 - if queue was empty, Program Endpoint
1266 - ... which starts DMA to fifo in mode 1 or 0
1267
1268 DMA Isr (transfer complete) -> TxAvail()
1269 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1270 only in musb_cleanup_urb)
1271 - TxPktRdy has to be set in mode 0 or for
1272 short packets in mode 1.
1273 */
1274
1275 #endif
1276
1277 /* Service a Tx-Available or dma completion irq for the endpoint */
musb_host_tx(struct musb * musb,u8 epnum)1278 void musb_host_tx(struct musb *musb, u8 epnum)
1279 {
1280 int pipe;
1281 bool done = false;
1282 u16 tx_csr;
1283 size_t length = 0;
1284 size_t offset = 0;
1285 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1286 void __iomem *epio = hw_ep->regs;
1287 struct musb_qh *qh = hw_ep->out_qh;
1288 struct urb *urb = next_urb(qh);
1289 u32 status = 0;
1290 void __iomem *mbase = musb->mregs;
1291 struct dma_channel *dma;
1292 bool transfer_pending = false;
1293
1294 musb_ep_select(mbase, epnum);
1295 tx_csr = musb_readw(epio, MUSB_TXCSR);
1296
1297 /* with CPPI, DMA sometimes triggers "extra" irqs */
1298 if (!urb) {
1299 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1300 return;
1301 }
1302
1303 pipe = urb->pipe;
1304 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1305 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1306 dma ? ", dma" : "");
1307
1308 /* check for errors */
1309 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1310 /* dma was disabled, fifo flushed */
1311 dev_dbg(musb->controller, "TX end %d stall\n", epnum);
1312
1313 /* stall; record URB status */
1314 status = -EPIPE;
1315
1316 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1317 /* (NON-ISO) dma was disabled, fifo flushed */
1318 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
1319
1320 status = -ETIMEDOUT;
1321
1322 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1323 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1
1324 && !list_is_singular(&musb->out_bulk)) {
1325 dev_dbg(musb->controller,
1326 "NAK timeout on TX%d ep\n", epnum);
1327 musb_bulk_nak_timeout(musb, hw_ep, 0);
1328 } else {
1329 dev_dbg(musb->controller,
1330 "TX end=%d device not responding\n", epnum);
1331 /* NOTE: this code path would be a good place to PAUSE a
1332 * transfer, if there's some other (nonperiodic) tx urb
1333 * that could use this fifo. (dma complicates it...)
1334 * That's already done for bulk RX transfers.
1335 *
1336 * if (bulk && qh->ring.next != &musb->out_bulk), then
1337 * we have a candidate... NAKing is *NOT* an error
1338 */
1339 musb_ep_select(mbase, epnum);
1340 musb_writew(epio, MUSB_TXCSR,
1341 MUSB_TXCSR_H_WZC_BITS
1342 | MUSB_TXCSR_TXPKTRDY);
1343 }
1344 return;
1345 }
1346
1347 done:
1348 if (status) {
1349 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1350 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1351 musb->dma_controller->channel_abort(dma);
1352 }
1353
1354 /* do the proper sequence to abort the transfer in the
1355 * usb core; the dma engine should already be stopped.
1356 */
1357 musb_h_tx_flush_fifo(hw_ep);
1358 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1359 | MUSB_TXCSR_DMAENAB
1360 | MUSB_TXCSR_H_ERROR
1361 | MUSB_TXCSR_H_RXSTALL
1362 | MUSB_TXCSR_H_NAKTIMEOUT
1363 );
1364
1365 musb_ep_select(mbase, epnum);
1366 musb_writew(epio, MUSB_TXCSR, tx_csr);
1367 /* REVISIT may need to clear FLUSHFIFO ... */
1368 musb_writew(epio, MUSB_TXCSR, tx_csr);
1369 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1370
1371 done = true;
1372 }
1373
1374 /* second cppi case */
1375 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1376 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1377 return;
1378 }
1379
1380 if (is_dma_capable() && dma && !status) {
1381 /*
1382 * DMA has completed. But if we're using DMA mode 1 (multi
1383 * packet DMA), we need a terminal TXPKTRDY interrupt before
1384 * we can consider this transfer completed, lest we trash
1385 * its last packet when writing the next URB's data. So we
1386 * switch back to mode 0 to get that interrupt; we'll come
1387 * back here once it happens.
1388 */
1389 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1390 /*
1391 * We shouldn't clear DMAMODE with DMAENAB set; so
1392 * clear them in a safe order. That should be OK
1393 * once TXPKTRDY has been set (and I've never seen
1394 * it being 0 at this moment -- DMA interrupt latency
1395 * is significant) but if it hasn't been then we have
1396 * no choice but to stop being polite and ignore the
1397 * programmer's guide... :-)
1398 *
1399 * Note that we must write TXCSR with TXPKTRDY cleared
1400 * in order not to re-trigger the packet send (this bit
1401 * can't be cleared by CPU), and there's another caveat:
1402 * TXPKTRDY may be set shortly and then cleared in the
1403 * double-buffered FIFO mode, so we do an extra TXCSR
1404 * read for debouncing...
1405 */
1406 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1407 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1408 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1409 MUSB_TXCSR_TXPKTRDY);
1410 musb_writew(epio, MUSB_TXCSR,
1411 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1412 }
1413 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1414 MUSB_TXCSR_TXPKTRDY);
1415 musb_writew(epio, MUSB_TXCSR,
1416 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1417
1418 /*
1419 * There is no guarantee that we'll get an interrupt
1420 * after clearing DMAMODE as we might have done this
1421 * too late (after TXPKTRDY was cleared by controller).
1422 * Re-read TXCSR as we have spoiled its previous value.
1423 */
1424 tx_csr = musb_readw(epio, MUSB_TXCSR);
1425 }
1426
1427 /*
1428 * We may get here from a DMA completion or TXPKTRDY interrupt.
1429 * In any case, we must check the FIFO status here and bail out
1430 * only if the FIFO still has data -- that should prevent the
1431 * "missed" TXPKTRDY interrupts and deal with double-buffered
1432 * FIFO mode too...
1433 */
1434 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1435 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
1436 "CSR %04x\n", tx_csr);
1437 return;
1438 }
1439 }
1440
1441 if (!status || dma || usb_pipeisoc(pipe)) {
1442 if (dma)
1443 length = dma->actual_len;
1444 else
1445 length = qh->segsize;
1446 qh->offset += length;
1447
1448 if (usb_pipeisoc(pipe)) {
1449 struct usb_iso_packet_descriptor *d;
1450
1451 d = urb->iso_frame_desc + qh->iso_idx;
1452 d->actual_length = length;
1453 d->status = status;
1454 if (++qh->iso_idx >= urb->number_of_packets) {
1455 done = true;
1456 } else {
1457 d++;
1458 offset = d->offset;
1459 length = d->length;
1460 }
1461 } else if (dma && urb->transfer_buffer_length == qh->offset) {
1462 done = true;
1463 } else {
1464 /* see if we need to send more data, or ZLP */
1465 if (qh->segsize < qh->maxpacket)
1466 done = true;
1467 else if (qh->offset == urb->transfer_buffer_length
1468 && !(urb->transfer_flags
1469 & URB_ZERO_PACKET))
1470 done = true;
1471 if (!done) {
1472 offset = qh->offset;
1473 length = urb->transfer_buffer_length - offset;
1474 transfer_pending = true;
1475 }
1476 }
1477 }
1478
1479 /* urb->status != -EINPROGRESS means request has been faulted,
1480 * so we must abort this transfer after cleanup
1481 */
1482 if (urb->status != -EINPROGRESS) {
1483 done = true;
1484 if (status == 0)
1485 status = urb->status;
1486 }
1487
1488 if (done) {
1489 /* set status */
1490 urb->status = status;
1491 urb->actual_length = qh->offset;
1492 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1493 return;
1494 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
1495 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1496 offset, length)) {
1497 if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
1498 musb_h_tx_dma_start(hw_ep);
1499 return;
1500 }
1501 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1502 dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
1503 return;
1504 }
1505
1506 /*
1507 * PIO: start next packet in this URB.
1508 *
1509 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1510 * (and presumably, FIFO is not half-full) we should write *two*
1511 * packets before updating TXCSR; other docs disagree...
1512 */
1513 if (length > qh->maxpacket)
1514 length = qh->maxpacket;
1515 /* Unmap the buffer so that CPU can use it */
1516 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1517
1518 /*
1519 * We need to map sg if the transfer_buffer is
1520 * NULL.
1521 */
1522 if (!urb->transfer_buffer) {
1523 /* sg_miter_start is already done in musb_ep_program */
1524 if (!sg_miter_next(&qh->sg_miter)) {
1525 dev_err(musb->controller, "error: sg list empty\n");
1526 sg_miter_stop(&qh->sg_miter);
1527 status = -EINVAL;
1528 goto done;
1529 }
1530 length = min_t(u32, length, qh->sg_miter.length);
1531 musb_write_fifo(hw_ep, length, qh->sg_miter.addr);
1532 qh->sg_miter.consumed = length;
1533 sg_miter_stop(&qh->sg_miter);
1534 } else {
1535 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1536 }
1537
1538 qh->segsize = length;
1539
1540 musb_ep_select(mbase, epnum);
1541 musb_writew(epio, MUSB_TXCSR,
1542 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1543 }
1544
1545 #ifdef CONFIG_USB_TI_CPPI41_DMA
1546 /* Seems to set up ISO for cppi41 and not advance len. See commit c57c41d */
musb_rx_dma_iso_cppi41(struct dma_controller * dma,struct musb_hw_ep * hw_ep,struct musb_qh * qh,struct urb * urb,size_t len)1547 static int musb_rx_dma_iso_cppi41(struct dma_controller *dma,
1548 struct musb_hw_ep *hw_ep,
1549 struct musb_qh *qh,
1550 struct urb *urb,
1551 size_t len)
1552 {
1553 struct dma_channel *channel = hw_ep->rx_channel;
1554 void __iomem *epio = hw_ep->regs;
1555 dma_addr_t *buf;
1556 u32 length, res;
1557 u16 val;
1558
1559 buf = (void *)urb->iso_frame_desc[qh->iso_idx].offset +
1560 (u32)urb->transfer_dma;
1561
1562 length = urb->iso_frame_desc[qh->iso_idx].length;
1563
1564 val = musb_readw(epio, MUSB_RXCSR);
1565 val |= MUSB_RXCSR_DMAENAB;
1566 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1567
1568 res = dma->channel_program(channel, qh->maxpacket, 0,
1569 (u32)buf, length);
1570
1571 return res;
1572 }
1573 #else
musb_rx_dma_iso_cppi41(struct dma_controller * dma,struct musb_hw_ep * hw_ep,struct musb_qh * qh,struct urb * urb,size_t len)1574 static inline int musb_rx_dma_iso_cppi41(struct dma_controller *dma,
1575 struct musb_hw_ep *hw_ep,
1576 struct musb_qh *qh,
1577 struct urb *urb,
1578 size_t len)
1579 {
1580 return false;
1581 }
1582 #endif
1583
1584 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) || \
1585 defined(CONFIG_USB_TI_CPPI41_DMA)
1586 /* Host side RX (IN) using Mentor DMA works as follows:
1587 submit_urb ->
1588 - if queue was empty, ProgramEndpoint
1589 - first IN token is sent out (by setting ReqPkt)
1590 LinuxIsr -> RxReady()
1591 /\ => first packet is received
1592 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1593 | -> DMA Isr (transfer complete) -> RxReady()
1594 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1595 | - if urb not complete, send next IN token (ReqPkt)
1596 | | else complete urb.
1597 | |
1598 ---------------------------
1599 *
1600 * Nuances of mode 1:
1601 * For short packets, no ack (+RxPktRdy) is sent automatically
1602 * (even if AutoClear is ON)
1603 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1604 * automatically => major problem, as collecting the next packet becomes
1605 * difficult. Hence mode 1 is not used.
1606 *
1607 * REVISIT
1608 * All we care about at this driver level is that
1609 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1610 * (b) termination conditions are: short RX, or buffer full;
1611 * (c) fault modes include
1612 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1613 * (and that endpoint's dma queue stops immediately)
1614 * - overflow (full, PLUS more bytes in the terminal packet)
1615 *
1616 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1617 * thus be a great candidate for using mode 1 ... for all but the
1618 * last packet of one URB's transfer.
1619 */
musb_rx_dma_inventra_cppi41(struct dma_controller * dma,struct musb_hw_ep * hw_ep,struct musb_qh * qh,struct urb * urb,size_t len)1620 static int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
1621 struct musb_hw_ep *hw_ep,
1622 struct musb_qh *qh,
1623 struct urb *urb,
1624 size_t len)
1625 {
1626 struct dma_channel *channel = hw_ep->rx_channel;
1627 void __iomem *epio = hw_ep->regs;
1628 u16 val;
1629 int pipe;
1630 bool done;
1631
1632 pipe = urb->pipe;
1633
1634 if (usb_pipeisoc(pipe)) {
1635 struct usb_iso_packet_descriptor *d;
1636
1637 d = urb->iso_frame_desc + qh->iso_idx;
1638 d->actual_length = len;
1639
1640 /* even if there was an error, we did the dma
1641 * for iso_frame_desc->length
1642 */
1643 if (d->status != -EILSEQ && d->status != -EOVERFLOW)
1644 d->status = 0;
1645
1646 if (++qh->iso_idx >= urb->number_of_packets) {
1647 done = true;
1648 } else {
1649 /* REVISIT: Why ignore return value here? */
1650 if (musb_dma_cppi41(hw_ep->musb))
1651 done = musb_rx_dma_iso_cppi41(dma, hw_ep, qh,
1652 urb, len);
1653 done = false;
1654 }
1655
1656 } else {
1657 /* done if urb buffer is full or short packet is recd */
1658 done = (urb->actual_length + len >=
1659 urb->transfer_buffer_length
1660 || channel->actual_len < qh->maxpacket
1661 || channel->rx_packet_done);
1662 }
1663
1664 /* send IN token for next packet, without AUTOREQ */
1665 if (!done) {
1666 val = musb_readw(epio, MUSB_RXCSR);
1667 val |= MUSB_RXCSR_H_REQPKT;
1668 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val);
1669 }
1670
1671 return done;
1672 }
1673
1674 /* Disadvantage of using mode 1:
1675 * It's basically usable only for mass storage class; essentially all
1676 * other protocols also terminate transfers on short packets.
1677 *
1678 * Details:
1679 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1680 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1681 * to use the extra IN token to grab the last packet using mode 0, then
1682 * the problem is that you cannot be sure when the device will send the
1683 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1684 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1685 * transfer, while sometimes it is recd just a little late so that if you
1686 * try to configure for mode 0 soon after the mode 1 transfer is
1687 * completed, you will find rxcount 0. Okay, so you might think why not
1688 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1689 */
musb_rx_dma_in_inventra_cppi41(struct dma_controller * dma,struct musb_hw_ep * hw_ep,struct musb_qh * qh,struct urb * urb,size_t len,u8 iso_err)1690 static int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma,
1691 struct musb_hw_ep *hw_ep,
1692 struct musb_qh *qh,
1693 struct urb *urb,
1694 size_t len,
1695 u8 iso_err)
1696 {
1697 struct musb *musb = hw_ep->musb;
1698 void __iomem *epio = hw_ep->regs;
1699 struct dma_channel *channel = hw_ep->rx_channel;
1700 u16 rx_count, val;
1701 int length, pipe, done;
1702 dma_addr_t buf;
1703
1704 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1705 pipe = urb->pipe;
1706
1707 if (usb_pipeisoc(pipe)) {
1708 int d_status = 0;
1709 struct usb_iso_packet_descriptor *d;
1710
1711 d = urb->iso_frame_desc + qh->iso_idx;
1712
1713 if (iso_err) {
1714 d_status = -EILSEQ;
1715 urb->error_count++;
1716 }
1717 if (rx_count > d->length) {
1718 if (d_status == 0) {
1719 d_status = -EOVERFLOW;
1720 urb->error_count++;
1721 }
1722 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",
1723 rx_count, d->length);
1724
1725 length = d->length;
1726 } else
1727 length = rx_count;
1728 d->status = d_status;
1729 buf = urb->transfer_dma + d->offset;
1730 } else {
1731 length = rx_count;
1732 buf = urb->transfer_dma + urb->actual_length;
1733 }
1734
1735 channel->desired_mode = 0;
1736 #ifdef USE_MODE1
1737 /* because of the issue below, mode 1 will
1738 * only rarely behave with correct semantics.
1739 */
1740 if ((urb->transfer_flags & URB_SHORT_NOT_OK)
1741 && (urb->transfer_buffer_length - urb->actual_length)
1742 > qh->maxpacket)
1743 channel->desired_mode = 1;
1744 if (rx_count < hw_ep->max_packet_sz_rx) {
1745 length = rx_count;
1746 channel->desired_mode = 0;
1747 } else {
1748 length = urb->transfer_buffer_length;
1749 }
1750 #endif
1751
1752 /* See comments above on disadvantages of using mode 1 */
1753 val = musb_readw(epio, MUSB_RXCSR);
1754 val &= ~MUSB_RXCSR_H_REQPKT;
1755
1756 if (channel->desired_mode == 0)
1757 val &= ~MUSB_RXCSR_H_AUTOREQ;
1758 else
1759 val |= MUSB_RXCSR_H_AUTOREQ;
1760 val |= MUSB_RXCSR_DMAENAB;
1761
1762 /* autoclear shouldn't be set in high bandwidth */
1763 if (qh->hb_mult == 1)
1764 val |= MUSB_RXCSR_AUTOCLEAR;
1765
1766 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val);
1767
1768 /* REVISIT if when actual_length != 0,
1769 * transfer_buffer_length needs to be
1770 * adjusted first...
1771 */
1772 done = dma->channel_program(channel, qh->maxpacket,
1773 channel->desired_mode,
1774 buf, length);
1775
1776 if (!done) {
1777 dma->channel_release(channel);
1778 hw_ep->rx_channel = NULL;
1779 channel = NULL;
1780 val = musb_readw(epio, MUSB_RXCSR);
1781 val &= ~(MUSB_RXCSR_DMAENAB
1782 | MUSB_RXCSR_H_AUTOREQ
1783 | MUSB_RXCSR_AUTOCLEAR);
1784 musb_writew(epio, MUSB_RXCSR, val);
1785 }
1786
1787 return done;
1788 }
1789 #else
musb_rx_dma_inventra_cppi41(struct dma_controller * dma,struct musb_hw_ep * hw_ep,struct musb_qh * qh,struct urb * urb,size_t len)1790 static inline int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
1791 struct musb_hw_ep *hw_ep,
1792 struct musb_qh *qh,
1793 struct urb *urb,
1794 size_t len)
1795 {
1796 return false;
1797 }
1798
musb_rx_dma_in_inventra_cppi41(struct dma_controller * dma,struct musb_hw_ep * hw_ep,struct musb_qh * qh,struct urb * urb,size_t len,u8 iso_err)1799 static inline int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma,
1800 struct musb_hw_ep *hw_ep,
1801 struct musb_qh *qh,
1802 struct urb *urb,
1803 size_t len,
1804 u8 iso_err)
1805 {
1806 return false;
1807 }
1808 #endif
1809
1810 /*
1811 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1812 * and high-bandwidth IN transfer cases.
1813 */
musb_host_rx(struct musb * musb,u8 epnum)1814 void musb_host_rx(struct musb *musb, u8 epnum)
1815 {
1816 struct urb *urb;
1817 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1818 struct dma_controller *c = musb->dma_controller;
1819 void __iomem *epio = hw_ep->regs;
1820 struct musb_qh *qh = hw_ep->in_qh;
1821 size_t xfer_len;
1822 void __iomem *mbase = musb->mregs;
1823 int pipe;
1824 u16 rx_csr, val;
1825 bool iso_err = false;
1826 bool done = false;
1827 u32 status;
1828 struct dma_channel *dma;
1829 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG;
1830
1831 musb_ep_select(mbase, epnum);
1832
1833 urb = next_urb(qh);
1834 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1835 status = 0;
1836 xfer_len = 0;
1837
1838 rx_csr = musb_readw(epio, MUSB_RXCSR);
1839 val = rx_csr;
1840
1841 if (unlikely(!urb)) {
1842 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1843 * usbtest #11 (unlinks) triggers it regularly, sometimes
1844 * with fifo full. (Only with DMA??)
1845 */
1846 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1847 musb_readw(epio, MUSB_RXCOUNT));
1848 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1849 return;
1850 }
1851
1852 pipe = urb->pipe;
1853
1854 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1855 epnum, rx_csr, urb->actual_length,
1856 dma ? dma->actual_len : 0);
1857
1858 /* check for errors, concurrent stall & unlink is not really
1859 * handled yet! */
1860 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1861 dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
1862
1863 /* stall; record URB status */
1864 status = -EPIPE;
1865
1866 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1867 dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
1868
1869 status = -EPROTO;
1870 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1871
1872 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1873
1874 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1875 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
1876
1877 /* NOTE: NAKing is *NOT* an error, so we want to
1878 * continue. Except ... if there's a request for
1879 * another QH, use that instead of starving it.
1880 *
1881 * Devices like Ethernet and serial adapters keep
1882 * reads posted at all times, which will starve
1883 * other devices without this logic.
1884 */
1885 if (usb_pipebulk(urb->pipe)
1886 && qh->mux == 1
1887 && !list_is_singular(&musb->in_bulk)) {
1888 musb_bulk_nak_timeout(musb, hw_ep, 1);
1889 return;
1890 }
1891 musb_ep_select(mbase, epnum);
1892 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1893 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1894 musb_writew(epio, MUSB_RXCSR, rx_csr);
1895
1896 goto finish;
1897 } else {
1898 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
1899 /* packet error reported later */
1900 iso_err = true;
1901 }
1902 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1903 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
1904 epnum);
1905 status = -EPROTO;
1906 }
1907
1908 /* faults abort the transfer */
1909 if (status) {
1910 /* clean up dma and collect transfer count */
1911 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1912 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1913 musb->dma_controller->channel_abort(dma);
1914 xfer_len = dma->actual_len;
1915 }
1916 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1917 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1918 done = true;
1919 goto finish;
1920 }
1921
1922 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1923 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1924 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1925 goto finish;
1926 }
1927
1928 /* thorough shutdown for now ... given more precise fault handling
1929 * and better queueing support, we might keep a DMA pipeline going
1930 * while processing this irq for earlier completions.
1931 */
1932
1933 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1934 if (!musb_dma_inventra(musb) && !musb_dma_ux500(musb) &&
1935 (rx_csr & MUSB_RXCSR_H_REQPKT)) {
1936 /* REVISIT this happened for a while on some short reads...
1937 * the cleanup still needs investigation... looks bad...
1938 * and also duplicates dma cleanup code above ... plus,
1939 * shouldn't this be the "half full" double buffer case?
1940 */
1941 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1942 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1943 musb->dma_controller->channel_abort(dma);
1944 xfer_len = dma->actual_len;
1945 done = true;
1946 }
1947
1948 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1949 xfer_len, dma ? ", dma" : "");
1950 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1951
1952 musb_ep_select(mbase, epnum);
1953 musb_writew(epio, MUSB_RXCSR,
1954 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1955 }
1956
1957 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1958 xfer_len = dma->actual_len;
1959
1960 val &= ~(MUSB_RXCSR_DMAENAB
1961 | MUSB_RXCSR_H_AUTOREQ
1962 | MUSB_RXCSR_AUTOCLEAR
1963 | MUSB_RXCSR_RXPKTRDY);
1964 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1965
1966 if (musb_dma_inventra(musb) || musb_dma_ux500(musb) ||
1967 musb_dma_cppi41(musb)) {
1968 done = musb_rx_dma_inventra_cppi41(c, hw_ep, qh, urb, xfer_len);
1969 dev_dbg(hw_ep->musb->controller,
1970 "ep %d dma %s, rxcsr %04x, rxcount %d\n",
1971 epnum, done ? "off" : "reset",
1972 musb_readw(epio, MUSB_RXCSR),
1973 musb_readw(epio, MUSB_RXCOUNT));
1974 } else {
1975 done = true;
1976 }
1977
1978 } else if (urb->status == -EINPROGRESS) {
1979 /* if no errors, be sure a packet is ready for unloading */
1980 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1981 status = -EPROTO;
1982 ERR("Rx interrupt with no errors or packet!\n");
1983
1984 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1985
1986 /* SCRUB (RX) */
1987 /* do the proper sequence to abort the transfer */
1988 musb_ep_select(mbase, epnum);
1989 val &= ~MUSB_RXCSR_H_REQPKT;
1990 musb_writew(epio, MUSB_RXCSR, val);
1991 goto finish;
1992 }
1993
1994 /* we are expecting IN packets */
1995 if ((musb_dma_inventra(musb) || musb_dma_ux500(musb) ||
1996 musb_dma_cppi41(musb)) && dma) {
1997 dev_dbg(hw_ep->musb->controller,
1998 "RX%d count %d, buffer 0x%llx len %d/%d\n",
1999 epnum, musb_readw(epio, MUSB_RXCOUNT),
2000 (unsigned long long) urb->transfer_dma
2001 + urb->actual_length,
2002 qh->offset,
2003 urb->transfer_buffer_length);
2004
2005 if (musb_rx_dma_in_inventra_cppi41(c, hw_ep, qh, urb,
2006 xfer_len, iso_err))
2007 goto finish;
2008 else
2009 dev_err(musb->controller, "error: rx_dma failed\n");
2010 }
2011
2012 if (!dma) {
2013 unsigned int received_len;
2014
2015 /* Unmap the buffer so that CPU can use it */
2016 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
2017
2018 /*
2019 * We need to map sg if the transfer_buffer is
2020 * NULL.
2021 */
2022 if (!urb->transfer_buffer) {
2023 qh->use_sg = true;
2024 sg_miter_start(&qh->sg_miter, urb->sg, 1,
2025 sg_flags);
2026 }
2027
2028 if (qh->use_sg) {
2029 if (!sg_miter_next(&qh->sg_miter)) {
2030 dev_err(musb->controller, "error: sg list empty\n");
2031 sg_miter_stop(&qh->sg_miter);
2032 status = -EINVAL;
2033 done = true;
2034 goto finish;
2035 }
2036 urb->transfer_buffer = qh->sg_miter.addr;
2037 received_len = urb->actual_length;
2038 qh->offset = 0x0;
2039 done = musb_host_packet_rx(musb, urb, epnum,
2040 iso_err);
2041 /* Calculate the number of bytes received */
2042 received_len = urb->actual_length -
2043 received_len;
2044 qh->sg_miter.consumed = received_len;
2045 sg_miter_stop(&qh->sg_miter);
2046 } else {
2047 done = musb_host_packet_rx(musb, urb,
2048 epnum, iso_err);
2049 }
2050 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
2051 }
2052 }
2053
2054 finish:
2055 urb->actual_length += xfer_len;
2056 qh->offset += xfer_len;
2057 if (done) {
2058 if (qh->use_sg) {
2059 qh->use_sg = false;
2060 urb->transfer_buffer = NULL;
2061 }
2062
2063 if (urb->status == -EINPROGRESS)
2064 urb->status = status;
2065 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
2066 }
2067 }
2068
2069 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
2070 * the software schedule associates multiple such nodes with a given
2071 * host side hardware endpoint + direction; scheduling may activate
2072 * that hardware endpoint.
2073 */
musb_schedule(struct musb * musb,struct musb_qh * qh,int is_in)2074 static int musb_schedule(
2075 struct musb *musb,
2076 struct musb_qh *qh,
2077 int is_in)
2078 {
2079 int idle = 0;
2080 int best_diff;
2081 int best_end, epnum;
2082 struct musb_hw_ep *hw_ep = NULL;
2083 struct list_head *head = NULL;
2084 u8 toggle;
2085 u8 txtype;
2086 struct urb *urb = next_urb(qh);
2087
2088 /* use fixed hardware for control and bulk */
2089 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
2090 head = &musb->control;
2091 hw_ep = musb->control_ep;
2092 goto success;
2093 }
2094
2095 /* else, periodic transfers get muxed to other endpoints */
2096
2097 /*
2098 * We know this qh hasn't been scheduled, so all we need to do
2099 * is choose which hardware endpoint to put it on ...
2100 *
2101 * REVISIT what we really want here is a regular schedule tree
2102 * like e.g. OHCI uses.
2103 */
2104 best_diff = 4096;
2105 best_end = -1;
2106
2107 for (epnum = 1, hw_ep = musb->endpoints + 1;
2108 epnum < musb->nr_endpoints;
2109 epnum++, hw_ep++) {
2110 int diff;
2111
2112 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
2113 continue;
2114
2115 if (hw_ep == musb->bulk_ep)
2116 continue;
2117
2118 if (is_in)
2119 diff = hw_ep->max_packet_sz_rx;
2120 else
2121 diff = hw_ep->max_packet_sz_tx;
2122 diff -= (qh->maxpacket * qh->hb_mult);
2123
2124 if (diff >= 0 && best_diff > diff) {
2125
2126 /*
2127 * Mentor controller has a bug in that if we schedule
2128 * a BULK Tx transfer on an endpoint that had earlier
2129 * handled ISOC then the BULK transfer has to start on
2130 * a zero toggle. If the BULK transfer starts on a 1
2131 * toggle then this transfer will fail as the mentor
2132 * controller starts the Bulk transfer on a 0 toggle
2133 * irrespective of the programming of the toggle bits
2134 * in the TXCSR register. Check for this condition
2135 * while allocating the EP for a Tx Bulk transfer. If
2136 * so skip this EP.
2137 */
2138 hw_ep = musb->endpoints + epnum;
2139 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
2140 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
2141 >> 4) & 0x3;
2142 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
2143 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
2144 continue;
2145
2146 best_diff = diff;
2147 best_end = epnum;
2148 }
2149 }
2150 /* use bulk reserved ep1 if no other ep is free */
2151 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
2152 hw_ep = musb->bulk_ep;
2153 if (is_in)
2154 head = &musb->in_bulk;
2155 else
2156 head = &musb->out_bulk;
2157
2158 /* Enable bulk RX/TX NAK timeout scheme when bulk requests are
2159 * multiplexed. This scheme does not work in high speed to full
2160 * speed scenario as NAK interrupts are not coming from a
2161 * full speed device connected to a high speed device.
2162 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
2163 * 4 (8 frame or 8ms) for FS device.
2164 */
2165 if (qh->dev)
2166 qh->intv_reg =
2167 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
2168 goto success;
2169 } else if (best_end < 0) {
2170 return -ENOSPC;
2171 }
2172
2173 idle = 1;
2174 qh->mux = 0;
2175 hw_ep = musb->endpoints + best_end;
2176 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
2177 success:
2178 if (head) {
2179 idle = list_empty(head);
2180 list_add_tail(&qh->ring, head);
2181 qh->mux = 1;
2182 }
2183 qh->hw_ep = hw_ep;
2184 qh->hep->hcpriv = qh;
2185 if (idle)
2186 musb_start_urb(musb, is_in, qh);
2187 return 0;
2188 }
2189
musb_urb_enqueue(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)2190 static int musb_urb_enqueue(
2191 struct usb_hcd *hcd,
2192 struct urb *urb,
2193 gfp_t mem_flags)
2194 {
2195 unsigned long flags;
2196 struct musb *musb = hcd_to_musb(hcd);
2197 struct usb_host_endpoint *hep = urb->ep;
2198 struct musb_qh *qh;
2199 struct usb_endpoint_descriptor *epd = &hep->desc;
2200 int ret;
2201 unsigned type_reg;
2202 unsigned interval;
2203
2204 /* host role must be active */
2205 if (!is_host_active(musb) || !musb->is_active)
2206 return -ENODEV;
2207
2208 spin_lock_irqsave(&musb->lock, flags);
2209 ret = usb_hcd_link_urb_to_ep(hcd, urb);
2210 qh = ret ? NULL : hep->hcpriv;
2211 if (qh)
2212 urb->hcpriv = qh;
2213 spin_unlock_irqrestore(&musb->lock, flags);
2214
2215 /* DMA mapping was already done, if needed, and this urb is on
2216 * hep->urb_list now ... so we're done, unless hep wasn't yet
2217 * scheduled onto a live qh.
2218 *
2219 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
2220 * disabled, testing for empty qh->ring and avoiding qh setup costs
2221 * except for the first urb queued after a config change.
2222 */
2223 if (qh || ret)
2224 return ret;
2225
2226 /* Allocate and initialize qh, minimizing the work done each time
2227 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
2228 *
2229 * REVISIT consider a dedicated qh kmem_cache, so it's harder
2230 * for bugs in other kernel code to break this driver...
2231 */
2232 qh = kzalloc(sizeof *qh, mem_flags);
2233 if (!qh) {
2234 spin_lock_irqsave(&musb->lock, flags);
2235 usb_hcd_unlink_urb_from_ep(hcd, urb);
2236 spin_unlock_irqrestore(&musb->lock, flags);
2237 return -ENOMEM;
2238 }
2239
2240 qh->hep = hep;
2241 qh->dev = urb->dev;
2242 INIT_LIST_HEAD(&qh->ring);
2243 qh->is_ready = 1;
2244
2245 qh->maxpacket = usb_endpoint_maxp(epd);
2246 qh->type = usb_endpoint_type(epd);
2247
2248 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
2249 * Some musb cores don't support high bandwidth ISO transfers; and
2250 * we don't (yet!) support high bandwidth interrupt transfers.
2251 */
2252 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
2253 if (qh->hb_mult > 1) {
2254 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
2255
2256 if (ok)
2257 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
2258 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
2259 if (!ok) {
2260 ret = -EMSGSIZE;
2261 goto done;
2262 }
2263 qh->maxpacket &= 0x7ff;
2264 }
2265
2266 qh->epnum = usb_endpoint_num(epd);
2267
2268 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
2269 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
2270
2271 /* precompute rxtype/txtype/type0 register */
2272 type_reg = (qh->type << 4) | qh->epnum;
2273 switch (urb->dev->speed) {
2274 case USB_SPEED_LOW:
2275 type_reg |= 0xc0;
2276 break;
2277 case USB_SPEED_FULL:
2278 type_reg |= 0x80;
2279 break;
2280 default:
2281 type_reg |= 0x40;
2282 }
2283 qh->type_reg = type_reg;
2284
2285 /* Precompute RXINTERVAL/TXINTERVAL register */
2286 switch (qh->type) {
2287 case USB_ENDPOINT_XFER_INT:
2288 /*
2289 * Full/low speeds use the linear encoding,
2290 * high speed uses the logarithmic encoding.
2291 */
2292 if (urb->dev->speed <= USB_SPEED_FULL) {
2293 interval = max_t(u8, epd->bInterval, 1);
2294 break;
2295 }
2296 /* FALLTHROUGH */
2297 case USB_ENDPOINT_XFER_ISOC:
2298 /* ISO always uses logarithmic encoding */
2299 interval = min_t(u8, epd->bInterval, 16);
2300 break;
2301 default:
2302 /* REVISIT we actually want to use NAK limits, hinting to the
2303 * transfer scheduling logic to try some other qh, e.g. try
2304 * for 2 msec first:
2305 *
2306 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2307 *
2308 * The downside of disabling this is that transfer scheduling
2309 * gets VERY unfair for nonperiodic transfers; a misbehaving
2310 * peripheral could make that hurt. That's perfectly normal
2311 * for reads from network or serial adapters ... so we have
2312 * partial NAKlimit support for bulk RX.
2313 *
2314 * The upside of disabling it is simpler transfer scheduling.
2315 */
2316 interval = 0;
2317 }
2318 qh->intv_reg = interval;
2319
2320 /* precompute addressing for external hub/tt ports */
2321 if (musb->is_multipoint) {
2322 struct usb_device *parent = urb->dev->parent;
2323
2324 if (parent != hcd->self.root_hub) {
2325 qh->h_addr_reg = (u8) parent->devnum;
2326
2327 /* set up tt info if needed */
2328 if (urb->dev->tt) {
2329 qh->h_port_reg = (u8) urb->dev->ttport;
2330 if (urb->dev->tt->hub)
2331 qh->h_addr_reg =
2332 (u8) urb->dev->tt->hub->devnum;
2333 if (urb->dev->tt->multi)
2334 qh->h_addr_reg |= 0x80;
2335 }
2336 }
2337 }
2338
2339 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2340 * until we get real dma queues (with an entry for each urb/buffer),
2341 * we only have work to do in the former case.
2342 */
2343 spin_lock_irqsave(&musb->lock, flags);
2344 if (hep->hcpriv || !next_urb(qh)) {
2345 /* some concurrent activity submitted another urb to hep...
2346 * odd, rare, error prone, but legal.
2347 */
2348 kfree(qh);
2349 qh = NULL;
2350 ret = 0;
2351 } else
2352 ret = musb_schedule(musb, qh,
2353 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2354
2355 if (ret == 0) {
2356 urb->hcpriv = qh;
2357 /* FIXME set urb->start_frame for iso/intr, it's tested in
2358 * musb_start_urb(), but otherwise only konicawc cares ...
2359 */
2360 }
2361 spin_unlock_irqrestore(&musb->lock, flags);
2362
2363 done:
2364 if (ret != 0) {
2365 spin_lock_irqsave(&musb->lock, flags);
2366 usb_hcd_unlink_urb_from_ep(hcd, urb);
2367 spin_unlock_irqrestore(&musb->lock, flags);
2368 kfree(qh);
2369 }
2370 return ret;
2371 }
2372
2373
2374 /*
2375 * abort a transfer that's at the head of a hardware queue.
2376 * called with controller locked, irqs blocked
2377 * that hardware queue advances to the next transfer, unless prevented
2378 */
musb_cleanup_urb(struct urb * urb,struct musb_qh * qh)2379 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2380 {
2381 struct musb_hw_ep *ep = qh->hw_ep;
2382 struct musb *musb = ep->musb;
2383 void __iomem *epio = ep->regs;
2384 unsigned hw_end = ep->epnum;
2385 void __iomem *regs = ep->musb->mregs;
2386 int is_in = usb_pipein(urb->pipe);
2387 int status = 0;
2388 u16 csr;
2389 struct dma_channel *dma = NULL;
2390
2391 musb_ep_select(regs, hw_end);
2392
2393 if (is_dma_capable()) {
2394 dma = is_in ? ep->rx_channel : ep->tx_channel;
2395 if (dma) {
2396 status = ep->musb->dma_controller->channel_abort(dma);
2397 dev_dbg(musb->controller,
2398 "abort %cX%d DMA for urb %p --> %d\n",
2399 is_in ? 'R' : 'T', ep->epnum,
2400 urb, status);
2401 urb->actual_length += dma->actual_len;
2402 }
2403 }
2404
2405 /* turn off DMA requests, discard state, stop polling ... */
2406 if (ep->epnum && is_in) {
2407 /* giveback saves bulk toggle */
2408 csr = musb_h_flush_rxfifo(ep, 0);
2409
2410 /* clear the endpoint's irq status here to avoid bogus irqs */
2411 if (is_dma_capable() && dma)
2412 musb_platform_clear_ep_rxintr(musb, ep->epnum);
2413 } else if (ep->epnum) {
2414 musb_h_tx_flush_fifo(ep);
2415 csr = musb_readw(epio, MUSB_TXCSR);
2416 csr &= ~(MUSB_TXCSR_AUTOSET
2417 | MUSB_TXCSR_DMAENAB
2418 | MUSB_TXCSR_H_RXSTALL
2419 | MUSB_TXCSR_H_NAKTIMEOUT
2420 | MUSB_TXCSR_H_ERROR
2421 | MUSB_TXCSR_TXPKTRDY);
2422 musb_writew(epio, MUSB_TXCSR, csr);
2423 /* REVISIT may need to clear FLUSHFIFO ... */
2424 musb_writew(epio, MUSB_TXCSR, csr);
2425 /* flush cpu writebuffer */
2426 csr = musb_readw(epio, MUSB_TXCSR);
2427 } else {
2428 musb_h_ep0_flush_fifo(ep);
2429 }
2430 if (status == 0)
2431 musb_advance_schedule(ep->musb, urb, ep, is_in);
2432 return status;
2433 }
2434
musb_urb_dequeue(struct usb_hcd * hcd,struct urb * urb,int status)2435 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2436 {
2437 struct musb *musb = hcd_to_musb(hcd);
2438 struct musb_qh *qh;
2439 unsigned long flags;
2440 int is_in = usb_pipein(urb->pipe);
2441 int ret;
2442
2443 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
2444 usb_pipedevice(urb->pipe),
2445 usb_pipeendpoint(urb->pipe),
2446 is_in ? "in" : "out");
2447
2448 spin_lock_irqsave(&musb->lock, flags);
2449 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2450 if (ret)
2451 goto done;
2452
2453 qh = urb->hcpriv;
2454 if (!qh)
2455 goto done;
2456
2457 /*
2458 * Any URB not actively programmed into endpoint hardware can be
2459 * immediately given back; that's any URB not at the head of an
2460 * endpoint queue, unless someday we get real DMA queues. And even
2461 * if it's at the head, it might not be known to the hardware...
2462 *
2463 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2464 * has already been updated. This is a synchronous abort; it'd be
2465 * OK to hold off until after some IRQ, though.
2466 *
2467 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2468 */
2469 if (!qh->is_ready
2470 || urb->urb_list.prev != &qh->hep->urb_list
2471 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2472 int ready = qh->is_ready;
2473
2474 qh->is_ready = 0;
2475 musb_giveback(musb, urb, 0);
2476 qh->is_ready = ready;
2477
2478 /* If nothing else (usually musb_giveback) is using it
2479 * and its URB list has emptied, recycle this qh.
2480 */
2481 if (ready && list_empty(&qh->hep->urb_list)) {
2482 qh->hep->hcpriv = NULL;
2483 list_del(&qh->ring);
2484 kfree(qh);
2485 }
2486 } else
2487 ret = musb_cleanup_urb(urb, qh);
2488 done:
2489 spin_unlock_irqrestore(&musb->lock, flags);
2490 return ret;
2491 }
2492
2493 /* disable an endpoint */
2494 static void
musb_h_disable(struct usb_hcd * hcd,struct usb_host_endpoint * hep)2495 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2496 {
2497 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2498 unsigned long flags;
2499 struct musb *musb = hcd_to_musb(hcd);
2500 struct musb_qh *qh;
2501 struct urb *urb;
2502
2503 spin_lock_irqsave(&musb->lock, flags);
2504
2505 qh = hep->hcpriv;
2506 if (qh == NULL)
2507 goto exit;
2508
2509 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2510
2511 /* Kick the first URB off the hardware, if needed */
2512 qh->is_ready = 0;
2513 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2514 urb = next_urb(qh);
2515
2516 /* make software (then hardware) stop ASAP */
2517 if (!urb->unlinked)
2518 urb->status = -ESHUTDOWN;
2519
2520 /* cleanup */
2521 musb_cleanup_urb(urb, qh);
2522
2523 /* Then nuke all the others ... and advance the
2524 * queue on hw_ep (e.g. bulk ring) when we're done.
2525 */
2526 while (!list_empty(&hep->urb_list)) {
2527 urb = next_urb(qh);
2528 urb->status = -ESHUTDOWN;
2529 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2530 }
2531 } else {
2532 /* Just empty the queue; the hardware is busy with
2533 * other transfers, and since !qh->is_ready nothing
2534 * will activate any of these as it advances.
2535 */
2536 while (!list_empty(&hep->urb_list))
2537 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2538
2539 hep->hcpriv = NULL;
2540 list_del(&qh->ring);
2541 kfree(qh);
2542 }
2543 exit:
2544 spin_unlock_irqrestore(&musb->lock, flags);
2545 }
2546
musb_h_get_frame_number(struct usb_hcd * hcd)2547 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2548 {
2549 struct musb *musb = hcd_to_musb(hcd);
2550
2551 return musb_readw(musb->mregs, MUSB_FRAME);
2552 }
2553
musb_h_start(struct usb_hcd * hcd)2554 static int musb_h_start(struct usb_hcd *hcd)
2555 {
2556 struct musb *musb = hcd_to_musb(hcd);
2557
2558 /* NOTE: musb_start() is called when the hub driver turns
2559 * on port power, or when (OTG) peripheral starts.
2560 */
2561 hcd->state = HC_STATE_RUNNING;
2562 musb->port1_status = 0;
2563 return 0;
2564 }
2565
musb_h_stop(struct usb_hcd * hcd)2566 static void musb_h_stop(struct usb_hcd *hcd)
2567 {
2568 musb_stop(hcd_to_musb(hcd));
2569 hcd->state = HC_STATE_HALT;
2570 }
2571
musb_bus_suspend(struct usb_hcd * hcd)2572 static int musb_bus_suspend(struct usb_hcd *hcd)
2573 {
2574 struct musb *musb = hcd_to_musb(hcd);
2575 u8 devctl;
2576 int ret;
2577
2578 ret = musb_port_suspend(musb, true);
2579 if (ret)
2580 return ret;
2581
2582 if (!is_host_active(musb))
2583 return 0;
2584
2585 switch (musb->xceiv->otg->state) {
2586 case OTG_STATE_A_SUSPEND:
2587 return 0;
2588 case OTG_STATE_A_WAIT_VRISE:
2589 /* ID could be grounded even if there's no device
2590 * on the other end of the cable. NOTE that the
2591 * A_WAIT_VRISE timers are messy with MUSB...
2592 */
2593 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2594 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2595 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
2596 break;
2597 default:
2598 break;
2599 }
2600
2601 if (musb->is_active) {
2602 WARNING("trying to suspend as %s while active\n",
2603 usb_otg_state_string(musb->xceiv->otg->state));
2604 return -EBUSY;
2605 } else
2606 return 0;
2607 }
2608
musb_bus_resume(struct usb_hcd * hcd)2609 static int musb_bus_resume(struct usb_hcd *hcd)
2610 {
2611 struct musb *musb = hcd_to_musb(hcd);
2612
2613 if (musb->config &&
2614 musb->config->host_port_deassert_reset_at_resume)
2615 musb_port_reset(musb, false);
2616
2617 return 0;
2618 }
2619
2620 #ifndef CONFIG_MUSB_PIO_ONLY
2621
2622 #define MUSB_USB_DMA_ALIGN 4
2623
2624 struct musb_temp_buffer {
2625 void *kmalloc_ptr;
2626 void *old_xfer_buffer;
2627 u8 data[0];
2628 };
2629
musb_free_temp_buffer(struct urb * urb)2630 static void musb_free_temp_buffer(struct urb *urb)
2631 {
2632 enum dma_data_direction dir;
2633 struct musb_temp_buffer *temp;
2634 size_t length;
2635
2636 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2637 return;
2638
2639 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2640
2641 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer,
2642 data);
2643
2644 if (dir == DMA_FROM_DEVICE) {
2645 if (usb_pipeisoc(urb->pipe))
2646 length = urb->transfer_buffer_length;
2647 else
2648 length = urb->actual_length;
2649
2650 memcpy(temp->old_xfer_buffer, temp->data, length);
2651 }
2652 urb->transfer_buffer = temp->old_xfer_buffer;
2653 kfree(temp->kmalloc_ptr);
2654
2655 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2656 }
2657
musb_alloc_temp_buffer(struct urb * urb,gfp_t mem_flags)2658 static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
2659 {
2660 enum dma_data_direction dir;
2661 struct musb_temp_buffer *temp;
2662 void *kmalloc_ptr;
2663 size_t kmalloc_size;
2664
2665 if (urb->num_sgs || urb->sg ||
2666 urb->transfer_buffer_length == 0 ||
2667 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1)))
2668 return 0;
2669
2670 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2671
2672 /* Allocate a buffer with enough padding for alignment */
2673 kmalloc_size = urb->transfer_buffer_length +
2674 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1;
2675
2676 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2677 if (!kmalloc_ptr)
2678 return -ENOMEM;
2679
2680 /* Position our struct temp_buffer such that data is aligned */
2681 temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN);
2682
2683
2684 temp->kmalloc_ptr = kmalloc_ptr;
2685 temp->old_xfer_buffer = urb->transfer_buffer;
2686 if (dir == DMA_TO_DEVICE)
2687 memcpy(temp->data, urb->transfer_buffer,
2688 urb->transfer_buffer_length);
2689 urb->transfer_buffer = temp->data;
2690
2691 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2692
2693 return 0;
2694 }
2695
musb_map_urb_for_dma(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)2696 static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2697 gfp_t mem_flags)
2698 {
2699 struct musb *musb = hcd_to_musb(hcd);
2700 int ret;
2701
2702 /*
2703 * The DMA engine in RTL1.8 and above cannot handle
2704 * DMA addresses that are not aligned to a 4 byte boundary.
2705 * For such engine implemented (un)map_urb_for_dma hooks.
2706 * Do not use these hooks for RTL<1.8
2707 */
2708 if (musb->hwvers < MUSB_HWVERS_1800)
2709 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2710
2711 ret = musb_alloc_temp_buffer(urb, mem_flags);
2712 if (ret)
2713 return ret;
2714
2715 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2716 if (ret)
2717 musb_free_temp_buffer(urb);
2718
2719 return ret;
2720 }
2721
musb_unmap_urb_for_dma(struct usb_hcd * hcd,struct urb * urb)2722 static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2723 {
2724 struct musb *musb = hcd_to_musb(hcd);
2725
2726 usb_hcd_unmap_urb_for_dma(hcd, urb);
2727
2728 /* Do not use this hook for RTL<1.8 (see description above) */
2729 if (musb->hwvers < MUSB_HWVERS_1800)
2730 return;
2731
2732 musb_free_temp_buffer(urb);
2733 }
2734 #endif /* !CONFIG_MUSB_PIO_ONLY */
2735
2736 static const struct hc_driver musb_hc_driver = {
2737 .description = "musb-hcd",
2738 .product_desc = "MUSB HDRC host driver",
2739 .hcd_priv_size = sizeof(struct musb *),
2740 .flags = HCD_USB2 | HCD_MEMORY | HCD_BH,
2741
2742 /* not using irq handler or reset hooks from usbcore, since
2743 * those must be shared with peripheral code for OTG configs
2744 */
2745
2746 .start = musb_h_start,
2747 .stop = musb_h_stop,
2748
2749 .get_frame_number = musb_h_get_frame_number,
2750
2751 .urb_enqueue = musb_urb_enqueue,
2752 .urb_dequeue = musb_urb_dequeue,
2753 .endpoint_disable = musb_h_disable,
2754
2755 #ifndef CONFIG_MUSB_PIO_ONLY
2756 .map_urb_for_dma = musb_map_urb_for_dma,
2757 .unmap_urb_for_dma = musb_unmap_urb_for_dma,
2758 #endif
2759
2760 .hub_status_data = musb_hub_status_data,
2761 .hub_control = musb_hub_control,
2762 .bus_suspend = musb_bus_suspend,
2763 .bus_resume = musb_bus_resume,
2764 /* .start_port_reset = NULL, */
2765 /* .hub_irq_enable = NULL, */
2766 };
2767
musb_host_alloc(struct musb * musb)2768 int musb_host_alloc(struct musb *musb)
2769 {
2770 struct device *dev = musb->controller;
2771
2772 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
2773 musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2774 if (!musb->hcd)
2775 return -EINVAL;
2776
2777 *musb->hcd->hcd_priv = (unsigned long) musb;
2778 musb->hcd->self.uses_pio_for_control = 1;
2779 musb->hcd->uses_new_polling = 1;
2780 musb->hcd->has_tt = 1;
2781
2782 return 0;
2783 }
2784
musb_host_cleanup(struct musb * musb)2785 void musb_host_cleanup(struct musb *musb)
2786 {
2787 if (musb->port_mode == MUSB_PORT_MODE_GADGET)
2788 return;
2789 usb_remove_hcd(musb->hcd);
2790 }
2791
musb_host_free(struct musb * musb)2792 void musb_host_free(struct musb *musb)
2793 {
2794 usb_put_hcd(musb->hcd);
2795 }
2796
musb_host_setup(struct musb * musb,int power_budget)2797 int musb_host_setup(struct musb *musb, int power_budget)
2798 {
2799 int ret;
2800 struct usb_hcd *hcd = musb->hcd;
2801
2802 MUSB_HST_MODE(musb);
2803 musb->xceiv->otg->default_a = 1;
2804 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2805
2806 otg_set_host(musb->xceiv->otg, &hcd->self);
2807 hcd->self.otg_port = 1;
2808 musb->xceiv->otg->host = &hcd->self;
2809 hcd->power_budget = 2 * (power_budget ? : 250);
2810
2811 ret = usb_add_hcd(hcd, 0, 0);
2812 if (ret < 0)
2813 return ret;
2814
2815 device_wakeup_enable(hcd->self.controller);
2816 return 0;
2817 }
2818
musb_host_resume_root_hub(struct musb * musb)2819 void musb_host_resume_root_hub(struct musb *musb)
2820 {
2821 usb_hcd_resume_root_hub(musb->hcd);
2822 }
2823
musb_host_poke_root_hub(struct musb * musb)2824 void musb_host_poke_root_hub(struct musb *musb)
2825 {
2826 MUSB_HST_MODE(musb);
2827 if (musb->hcd->status_urb)
2828 usb_hcd_poll_rh_status(musb->hcd);
2829 else
2830 usb_hcd_resume_root_hub(musb->hcd);
2831 }
2832