1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 #ifndef __LINUX_ARM_SMCCC_H 15 #define __LINUX_ARM_SMCCC_H 16 17 #include <linux/linkage.h> 18 #include <linux/types.h> 19 #include <uapi/linux/const.h> 20 21 /* 22 * This file provides common defines for ARM SMC Calling Convention as 23 * specified in 24 * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html 25 */ 26 27 #define ARM_SMCCC_STD_CALL _AC(0,U) 28 #define ARM_SMCCC_FAST_CALL _AC(1,U) 29 #define ARM_SMCCC_TYPE_SHIFT 31 30 31 #define ARM_SMCCC_SMC_32 0 32 #define ARM_SMCCC_SMC_64 1 33 #define ARM_SMCCC_CALL_CONV_SHIFT 30 34 35 #define ARM_SMCCC_OWNER_MASK 0x3F 36 #define ARM_SMCCC_OWNER_SHIFT 24 37 38 #define ARM_SMCCC_FUNC_MASK 0xFFFF 39 40 #define ARM_SMCCC_IS_FAST_CALL(smc_val) \ 41 ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) 42 #define ARM_SMCCC_IS_64(smc_val) \ 43 ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) 44 #define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK) 45 #define ARM_SMCCC_OWNER_NUM(smc_val) \ 46 (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) 47 48 #define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ 49 (((type) << ARM_SMCCC_TYPE_SHIFT) | \ 50 ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ 51 (((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ 52 ((func_num) & ARM_SMCCC_FUNC_MASK)) 53 54 #define ARM_SMCCC_OWNER_ARCH 0 55 #define ARM_SMCCC_OWNER_CPU 1 56 #define ARM_SMCCC_OWNER_SIP 2 57 #define ARM_SMCCC_OWNER_OEM 3 58 #define ARM_SMCCC_OWNER_STANDARD 4 59 #define ARM_SMCCC_OWNER_TRUSTED_APP 48 60 #define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 61 #define ARM_SMCCC_OWNER_TRUSTED_OS 50 62 #define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 63 64 #define ARM_SMCCC_VERSION_1_0 0x10000 65 #define ARM_SMCCC_VERSION_1_1 0x10001 66 67 #define ARM_SMCCC_VERSION_FUNC_ID \ 68 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ 69 ARM_SMCCC_SMC_32, \ 70 0, 0) 71 72 #define ARM_SMCCC_ARCH_FEATURES_FUNC_ID \ 73 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ 74 ARM_SMCCC_SMC_32, \ 75 0, 1) 76 77 #define ARM_SMCCC_ARCH_WORKAROUND_1 \ 78 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ 79 ARM_SMCCC_SMC_32, \ 80 0, 0x8000) 81 82 #ifndef __ASSEMBLY__ 83 84 #include <linux/linkage.h> 85 #include <linux/types.h> 86 87 /** 88 * struct arm_smccc_res - Result from SMC/HVC call 89 * @a0-a3 result values from registers 0 to 3 90 */ 91 struct arm_smccc_res { 92 unsigned long a0; 93 unsigned long a1; 94 unsigned long a2; 95 unsigned long a3; 96 }; 97 98 /** 99 * arm_smccc_smc() - make SMC calls 100 * @a0-a7: arguments passed in registers 0 to 7 101 * @res: result values from registers 0 to 3 102 * 103 * This function is used to make SMC calls following SMC Calling Convention. 104 * The content of the supplied param are copied to registers 0 to 7 prior 105 * to the SMC instruction. The return values are updated with the content 106 * from register 0 to 3 on return from the SMC instruction. 107 */ 108 asmlinkage void arm_smccc_smc(unsigned long a0, unsigned long a1, 109 unsigned long a2, unsigned long a3, unsigned long a4, 110 unsigned long a5, unsigned long a6, unsigned long a7, 111 struct arm_smccc_res *res); 112 113 /** 114 * arm_smccc_hvc() - make HVC calls 115 * @a0-a7: arguments passed in registers 0 to 7 116 * @res: result values from registers 0 to 3 117 * 118 * This function is used to make HVC calls following SMC Calling 119 * Convention. The content of the supplied param are copied to registers 0 120 * to 7 prior to the HVC instruction. The return values are updated with 121 * the content from register 0 to 3 on return from the HVC instruction. 122 */ 123 asmlinkage void arm_smccc_hvc(unsigned long a0, unsigned long a1, 124 unsigned long a2, unsigned long a3, unsigned long a4, 125 unsigned long a5, unsigned long a6, unsigned long a7, 126 struct arm_smccc_res *res); 127 128 /* SMCCC v1.1 implementation madness follows */ 129 #ifdef CONFIG_ARM64 130 131 #define SMCCC_SMC_INST "smc #0" 132 #define SMCCC_HVC_INST "hvc #0" 133 134 #elif defined(CONFIG_ARM) 135 #include <asm/opcodes-sec.h> 136 #include <asm/opcodes-virt.h> 137 138 #define SMCCC_SMC_INST __SMC(0) 139 #define SMCCC_HVC_INST __HVC(0) 140 141 #endif 142 143 #define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x 144 145 #define __count_args(...) \ 146 ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) 147 148 #define __constraint_write_0 \ 149 "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) 150 #define __constraint_write_1 \ 151 "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) 152 #define __constraint_write_2 \ 153 "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) 154 #define __constraint_write_3 \ 155 "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) 156 #define __constraint_write_4 __constraint_write_3 157 #define __constraint_write_5 __constraint_write_4 158 #define __constraint_write_6 __constraint_write_5 159 #define __constraint_write_7 __constraint_write_6 160 161 #define __constraint_read_0 162 #define __constraint_read_1 163 #define __constraint_read_2 164 #define __constraint_read_3 165 #define __constraint_read_4 "r" (r4) 166 #define __constraint_read_5 __constraint_read_4, "r" (r5) 167 #define __constraint_read_6 __constraint_read_5, "r" (r6) 168 #define __constraint_read_7 __constraint_read_6, "r" (r7) 169 170 #define __declare_arg_0(a0, res) \ 171 struct arm_smccc_res *___res = res; \ 172 register unsigned long r0 asm("r0") = (u32)a0; \ 173 register unsigned long r1 asm("r1"); \ 174 register unsigned long r2 asm("r2"); \ 175 register unsigned long r3 asm("r3") 176 177 #define __declare_arg_1(a0, a1, res) \ 178 typeof(a1) __a1 = a1; \ 179 struct arm_smccc_res *___res = res; \ 180 register unsigned long r0 asm("r0") = (u32)a0; \ 181 register unsigned long r1 asm("r1") = __a1; \ 182 register unsigned long r2 asm("r2"); \ 183 register unsigned long r3 asm("r3") 184 185 #define __declare_arg_2(a0, a1, a2, res) \ 186 typeof(a1) __a1 = a1; \ 187 typeof(a2) __a2 = a2; \ 188 struct arm_smccc_res *___res = res; \ 189 register unsigned long r0 asm("r0") = (u32)a0; \ 190 register unsigned long r1 asm("r1") = __a1; \ 191 register unsigned long r2 asm("r2") = __a2; \ 192 register unsigned long r3 asm("r3") 193 194 #define __declare_arg_3(a0, a1, a2, a3, res) \ 195 typeof(a1) __a1 = a1; \ 196 typeof(a2) __a2 = a2; \ 197 typeof(a3) __a3 = a3; \ 198 struct arm_smccc_res *___res = res; \ 199 register unsigned long r0 asm("r0") = (u32)a0; \ 200 register unsigned long r1 asm("r1") = __a1; \ 201 register unsigned long r2 asm("r2") = __a2; \ 202 register unsigned long r3 asm("r3") = __a3 203 204 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ 205 typeof(a4) __a4 = a4; \ 206 __declare_arg_3(a0, a1, a2, a3, res); \ 207 register unsigned long r4 asm("r4") = __a4 208 209 #define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ 210 typeof(a5) __a5 = a5; \ 211 __declare_arg_4(a0, a1, a2, a3, a4, res); \ 212 register unsigned long r5 asm("r5") = __a5 213 214 #define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ 215 typeof(a6) __a6 = a6; \ 216 __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ 217 register unsigned long r6 asm("r6") = __a6 218 219 #define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ 220 typeof(a7) __a7 = a7; \ 221 __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ 222 register unsigned long r7 asm("r7") = __a7 223 224 #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) 225 #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) 226 227 #define ___constraints(count) \ 228 : __constraint_write_ ## count \ 229 : __constraint_read_ ## count \ 230 : "memory" 231 #define __constraints(count) ___constraints(count) 232 233 /* 234 * We have an output list that is not necessarily used, and GCC feels 235 * entitled to optimise the whole sequence away. "volatile" is what 236 * makes it stick. 237 */ 238 #define __arm_smccc_1_1(inst, ...) \ 239 do { \ 240 __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ 241 asm volatile(inst "\n" \ 242 __constraints(__count_args(__VA_ARGS__))); \ 243 if (___res) \ 244 *___res = (typeof(*___res)){r0, r1, r2, r3}; \ 245 } while (0) 246 247 /* 248 * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call 249 * 250 * This is a variadic macro taking one to eight source arguments, and 251 * an optional return structure. 252 * 253 * @a0-a7: arguments passed in registers 0 to 7 254 * @res: result values from registers 0 to 3 255 * 256 * This macro is used to make SMC calls following SMC Calling Convention v1.1. 257 * The content of the supplied param are copied to registers 0 to 7 prior 258 * to the SMC instruction. The return values are updated with the content 259 * from register 0 to 3 on return from the SMC instruction if not NULL. 260 */ 261 #define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__) 262 263 /* 264 * arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call 265 * 266 * This is a variadic macro taking one to eight source arguments, and 267 * an optional return structure. 268 * 269 * @a0-a7: arguments passed in registers 0 to 7 270 * @res: result values from registers 0 to 3 271 * 272 * This macro is used to make HVC calls following SMC Calling Convention v1.1. 273 * The content of the supplied param are copied to registers 0 to 7 prior 274 * to the HVC instruction. The return values are updated with the content 275 * from register 0 to 3 on return from the HVC instruction if not NULL. 276 */ 277 #define arm_smccc_1_1_hvc(...) __arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__) 278 279 /* Return codes defined in ARM DEN 0070A */ 280 #define SMCCC_RET_SUCCESS 0 281 #define SMCCC_RET_NOT_SUPPORTED -1 282 #define SMCCC_RET_NOT_REQUIRED -2 283 284 #endif /*__ASSEMBLY__*/ 285 #endif /*__LINUX_ARM_SMCCC_H*/ 286