1 #ifndef _LINUX_DMA_MAPPING_H
2 #define _LINUX_DMA_MAPPING_H
3
4 #include <linux/sizes.h>
5 #include <linux/string.h>
6 #include <linux/device.h>
7 #include <linux/err.h>
8 #include <linux/dma-attrs.h>
9 #include <linux/dma-direction.h>
10 #include <linux/scatterlist.h>
11
12 /*
13 * A dma_addr_t can hold any valid DMA or bus address for the platform.
14 * It can be given to a device to use as a DMA source or target. A CPU cannot
15 * reference a dma_addr_t directly because there may be translation between
16 * its physical address space and the bus address space.
17 */
18 struct dma_map_ops {
19 void* (*alloc)(struct device *dev, size_t size,
20 dma_addr_t *dma_handle, gfp_t gfp,
21 struct dma_attrs *attrs);
22 void (*free)(struct device *dev, size_t size,
23 void *vaddr, dma_addr_t dma_handle,
24 struct dma_attrs *attrs);
25 int (*mmap)(struct device *, struct vm_area_struct *,
26 void *, dma_addr_t, size_t, struct dma_attrs *attrs);
27
28 int (*get_sgtable)(struct device *dev, struct sg_table *sgt, void *,
29 dma_addr_t, size_t, struct dma_attrs *attrs);
30
31 dma_addr_t (*map_page)(struct device *dev, struct page *page,
32 unsigned long offset, size_t size,
33 enum dma_data_direction dir,
34 struct dma_attrs *attrs);
35 void (*unmap_page)(struct device *dev, dma_addr_t dma_handle,
36 size_t size, enum dma_data_direction dir,
37 struct dma_attrs *attrs);
38 /*
39 * map_sg returns 0 on error and a value > 0 on success.
40 * It should never return a value < 0.
41 */
42 int (*map_sg)(struct device *dev, struct scatterlist *sg,
43 int nents, enum dma_data_direction dir,
44 struct dma_attrs *attrs);
45 void (*unmap_sg)(struct device *dev,
46 struct scatterlist *sg, int nents,
47 enum dma_data_direction dir,
48 struct dma_attrs *attrs);
49 void (*sync_single_for_cpu)(struct device *dev,
50 dma_addr_t dma_handle, size_t size,
51 enum dma_data_direction dir);
52 void (*sync_single_for_device)(struct device *dev,
53 dma_addr_t dma_handle, size_t size,
54 enum dma_data_direction dir);
55 void (*sync_sg_for_cpu)(struct device *dev,
56 struct scatterlist *sg, int nents,
57 enum dma_data_direction dir);
58 void (*sync_sg_for_device)(struct device *dev,
59 struct scatterlist *sg, int nents,
60 enum dma_data_direction dir);
61 int (*mapping_error)(struct device *dev, dma_addr_t dma_addr);
62 int (*dma_supported)(struct device *dev, u64 mask);
63 int (*set_dma_mask)(struct device *dev, u64 mask);
64 #ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
65 u64 (*get_required_mask)(struct device *dev);
66 #endif
67 int is_phys;
68 };
69
70 #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
71
72 #define DMA_MASK_NONE 0x0ULL
73
valid_dma_direction(int dma_direction)74 static inline int valid_dma_direction(int dma_direction)
75 {
76 return ((dma_direction == DMA_BIDIRECTIONAL) ||
77 (dma_direction == DMA_TO_DEVICE) ||
78 (dma_direction == DMA_FROM_DEVICE));
79 }
80
is_device_dma_capable(struct device * dev)81 static inline int is_device_dma_capable(struct device *dev)
82 {
83 return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
84 }
85
86 #ifdef CONFIG_HAS_DMA
87 #include <asm/dma-mapping.h>
88 #else
89 #include <asm-generic/dma-mapping-broken.h>
90 #endif
91
dma_get_mask(struct device * dev)92 static inline u64 dma_get_mask(struct device *dev)
93 {
94 if (dev && dev->dma_mask && *dev->dma_mask)
95 return *dev->dma_mask;
96 return DMA_BIT_MASK(32);
97 }
98
99 #ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
100 int dma_set_coherent_mask(struct device *dev, u64 mask);
101 #else
dma_set_coherent_mask(struct device * dev,u64 mask)102 static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
103 {
104 if (!dma_supported(dev, mask))
105 return -EIO;
106 dev->coherent_dma_mask = mask;
107 return 0;
108 }
109 #endif
110
111 /*
112 * Set both the DMA mask and the coherent DMA mask to the same thing.
113 * Note that we don't check the return value from dma_set_coherent_mask()
114 * as the DMA API guarantees that the coherent DMA mask can be set to
115 * the same or smaller than the streaming DMA mask.
116 */
dma_set_mask_and_coherent(struct device * dev,u64 mask)117 static inline int dma_set_mask_and_coherent(struct device *dev, u64 mask)
118 {
119 int rc = dma_set_mask(dev, mask);
120 if (rc == 0)
121 dma_set_coherent_mask(dev, mask);
122 return rc;
123 }
124
125 /*
126 * Similar to the above, except it deals with the case where the device
127 * does not have dev->dma_mask appropriately setup.
128 */
dma_coerce_mask_and_coherent(struct device * dev,u64 mask)129 static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask)
130 {
131 dev->dma_mask = &dev->coherent_dma_mask;
132 return dma_set_mask_and_coherent(dev, mask);
133 }
134
135 extern u64 dma_get_required_mask(struct device *dev);
136
137 #ifndef arch_setup_dma_ops
arch_setup_dma_ops(struct device * dev,u64 dma_base,u64 size,struct iommu_ops * iommu,bool coherent)138 static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base,
139 u64 size, struct iommu_ops *iommu,
140 bool coherent) { }
141 #endif
142
143 #ifndef arch_teardown_dma_ops
arch_teardown_dma_ops(struct device * dev)144 static inline void arch_teardown_dma_ops(struct device *dev) { }
145 #endif
146
dma_get_max_seg_size(struct device * dev)147 static inline unsigned int dma_get_max_seg_size(struct device *dev)
148 {
149 if (dev->dma_parms && dev->dma_parms->max_segment_size)
150 return dev->dma_parms->max_segment_size;
151 return SZ_64K;
152 }
153
dma_set_max_seg_size(struct device * dev,unsigned int size)154 static inline int dma_set_max_seg_size(struct device *dev, unsigned int size)
155 {
156 if (dev->dma_parms) {
157 dev->dma_parms->max_segment_size = size;
158 return 0;
159 }
160 return -EIO;
161 }
162
dma_get_seg_boundary(struct device * dev)163 static inline unsigned long dma_get_seg_boundary(struct device *dev)
164 {
165 if (dev->dma_parms && dev->dma_parms->segment_boundary_mask)
166 return dev->dma_parms->segment_boundary_mask;
167 return DMA_BIT_MASK(32);
168 }
169
dma_set_seg_boundary(struct device * dev,unsigned long mask)170 static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
171 {
172 if (dev->dma_parms) {
173 dev->dma_parms->segment_boundary_mask = mask;
174 return 0;
175 }
176 return -EIO;
177 }
178
179 #ifndef dma_max_pfn
dma_max_pfn(struct device * dev)180 static inline unsigned long dma_max_pfn(struct device *dev)
181 {
182 return *dev->dma_mask >> PAGE_SHIFT;
183 }
184 #endif
185
dma_zalloc_coherent(struct device * dev,size_t size,dma_addr_t * dma_handle,gfp_t flag)186 static inline void *dma_zalloc_coherent(struct device *dev, size_t size,
187 dma_addr_t *dma_handle, gfp_t flag)
188 {
189 void *ret = dma_alloc_coherent(dev, size, dma_handle,
190 flag | __GFP_ZERO);
191 return ret;
192 }
193
194 #ifdef CONFIG_HAS_DMA
dma_get_cache_alignment(void)195 static inline int dma_get_cache_alignment(void)
196 {
197 #ifdef ARCH_DMA_MINALIGN
198 return ARCH_DMA_MINALIGN;
199 #endif
200 return 1;
201 }
202 #endif
203
204 /* flags for the coherent memory api */
205 #define DMA_MEMORY_MAP 0x01
206 #define DMA_MEMORY_IO 0x02
207 #define DMA_MEMORY_INCLUDES_CHILDREN 0x04
208 #define DMA_MEMORY_EXCLUSIVE 0x08
209
210 #ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
211 static inline int
dma_declare_coherent_memory(struct device * dev,phys_addr_t phys_addr,dma_addr_t device_addr,size_t size,int flags)212 dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
213 dma_addr_t device_addr, size_t size, int flags)
214 {
215 return 0;
216 }
217
218 static inline void
dma_release_declared_memory(struct device * dev)219 dma_release_declared_memory(struct device *dev)
220 {
221 }
222
223 static inline void *
dma_mark_declared_memory_occupied(struct device * dev,dma_addr_t device_addr,size_t size)224 dma_mark_declared_memory_occupied(struct device *dev,
225 dma_addr_t device_addr, size_t size)
226 {
227 return ERR_PTR(-EBUSY);
228 }
229 #endif
230
231 /*
232 * Managed DMA API
233 */
234 extern void *dmam_alloc_coherent(struct device *dev, size_t size,
235 dma_addr_t *dma_handle, gfp_t gfp);
236 extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
237 dma_addr_t dma_handle);
238 extern void *dmam_alloc_noncoherent(struct device *dev, size_t size,
239 dma_addr_t *dma_handle, gfp_t gfp);
240 extern void dmam_free_noncoherent(struct device *dev, size_t size, void *vaddr,
241 dma_addr_t dma_handle);
242 #ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
243 extern int dmam_declare_coherent_memory(struct device *dev,
244 phys_addr_t phys_addr,
245 dma_addr_t device_addr, size_t size,
246 int flags);
247 extern void dmam_release_declared_memory(struct device *dev);
248 #else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
dmam_declare_coherent_memory(struct device * dev,phys_addr_t phys_addr,dma_addr_t device_addr,size_t size,gfp_t gfp)249 static inline int dmam_declare_coherent_memory(struct device *dev,
250 phys_addr_t phys_addr, dma_addr_t device_addr,
251 size_t size, gfp_t gfp)
252 {
253 return 0;
254 }
255
dmam_release_declared_memory(struct device * dev)256 static inline void dmam_release_declared_memory(struct device *dev)
257 {
258 }
259 #endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
260
261 #ifndef CONFIG_HAVE_DMA_ATTRS
262 struct dma_attrs;
263
264 #define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \
265 dma_map_single(dev, cpu_addr, size, dir)
266
267 #define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \
268 dma_unmap_single(dev, dma_addr, size, dir)
269
270 #define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \
271 dma_map_sg(dev, sgl, nents, dir)
272
273 #define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \
274 dma_unmap_sg(dev, sgl, nents, dir)
275
276 #else
dma_alloc_writecombine(struct device * dev,size_t size,dma_addr_t * dma_addr,gfp_t gfp)277 static inline void *dma_alloc_writecombine(struct device *dev, size_t size,
278 dma_addr_t *dma_addr, gfp_t gfp)
279 {
280 DEFINE_DMA_ATTRS(attrs);
281 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
282 return dma_alloc_attrs(dev, size, dma_addr, gfp, &attrs);
283 }
284
dma_free_writecombine(struct device * dev,size_t size,void * cpu_addr,dma_addr_t dma_addr)285 static inline void dma_free_writecombine(struct device *dev, size_t size,
286 void *cpu_addr, dma_addr_t dma_addr)
287 {
288 DEFINE_DMA_ATTRS(attrs);
289 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
290 return dma_free_attrs(dev, size, cpu_addr, dma_addr, &attrs);
291 }
292
dma_mmap_writecombine(struct device * dev,struct vm_area_struct * vma,void * cpu_addr,dma_addr_t dma_addr,size_t size)293 static inline int dma_mmap_writecombine(struct device *dev,
294 struct vm_area_struct *vma,
295 void *cpu_addr, dma_addr_t dma_addr,
296 size_t size)
297 {
298 DEFINE_DMA_ATTRS(attrs);
299 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
300 return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
301 }
302 #endif /* CONFIG_HAVE_DMA_ATTRS */
303
304 #ifdef CONFIG_NEED_DMA_MAP_STATE
305 #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME
306 #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME
307 #define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
308 #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
309 #define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
310 #define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
311 #else
312 #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)
313 #define DEFINE_DMA_UNMAP_LEN(LEN_NAME)
314 #define dma_unmap_addr(PTR, ADDR_NAME) (0)
315 #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
316 #define dma_unmap_len(PTR, LEN_NAME) (0)
317 #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
318 #endif
319
320 #endif
321