1 /* 2 * Definitions for the NVM Express interface 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef _LINUX_NVME_H 16 #define _LINUX_NVME_H 17 18 #include <linux/types.h> 19 20 struct nvme_bar { 21 __u64 cap; /* Controller Capabilities */ 22 __u32 vs; /* Version */ 23 __u32 intms; /* Interrupt Mask Set */ 24 __u32 intmc; /* Interrupt Mask Clear */ 25 __u32 cc; /* Controller Configuration */ 26 __u32 rsvd1; /* Reserved */ 27 __u32 csts; /* Controller Status */ 28 __u32 nssr; /* Subsystem Reset */ 29 __u32 aqa; /* Admin Queue Attributes */ 30 __u64 asq; /* Admin SQ Base Address */ 31 __u64 acq; /* Admin CQ Base Address */ 32 __u32 cmbloc; /* Controller Memory Buffer Location */ 33 __u32 cmbsz; /* Controller Memory Buffer Size */ 34 }; 35 36 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 37 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 38 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 39 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 40 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 41 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 42 43 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 44 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 45 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff) 46 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf) 47 48 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10) 49 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8) 50 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4) 51 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2) 52 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1) 53 54 enum { 55 NVME_CC_ENABLE = 1 << 0, 56 NVME_CC_CSS_NVM = 0 << 4, 57 NVME_CC_MPS_SHIFT = 7, 58 NVME_CC_ARB_RR = 0 << 11, 59 NVME_CC_ARB_WRRU = 1 << 11, 60 NVME_CC_ARB_VS = 7 << 11, 61 NVME_CC_SHN_NONE = 0 << 14, 62 NVME_CC_SHN_NORMAL = 1 << 14, 63 NVME_CC_SHN_ABRUPT = 2 << 14, 64 NVME_CC_SHN_MASK = 3 << 14, 65 NVME_CC_IOSQES = 6 << 16, 66 NVME_CC_IOCQES = 4 << 20, 67 NVME_CSTS_RDY = 1 << 0, 68 NVME_CSTS_CFS = 1 << 1, 69 NVME_CSTS_NSSRO = 1 << 4, 70 NVME_CSTS_SHST_NORMAL = 0 << 2, 71 NVME_CSTS_SHST_OCCUR = 1 << 2, 72 NVME_CSTS_SHST_CMPLT = 2 << 2, 73 NVME_CSTS_SHST_MASK = 3 << 2, 74 }; 75 76 struct nvme_id_power_state { 77 __le16 max_power; /* centiwatts */ 78 __u8 rsvd2; 79 __u8 flags; 80 __le32 entry_lat; /* microseconds */ 81 __le32 exit_lat; /* microseconds */ 82 __u8 read_tput; 83 __u8 read_lat; 84 __u8 write_tput; 85 __u8 write_lat; 86 __le16 idle_power; 87 __u8 idle_scale; 88 __u8 rsvd19; 89 __le16 active_power; 90 __u8 active_work_scale; 91 __u8 rsvd23[9]; 92 }; 93 94 enum { 95 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 96 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 97 }; 98 99 struct nvme_id_ctrl { 100 __le16 vid; 101 __le16 ssvid; 102 char sn[20]; 103 char mn[40]; 104 char fr[8]; 105 __u8 rab; 106 __u8 ieee[3]; 107 __u8 mic; 108 __u8 mdts; 109 __le16 cntlid; 110 __le32 ver; 111 __u8 rsvd84[172]; 112 __le16 oacs; 113 __u8 acl; 114 __u8 aerl; 115 __u8 frmw; 116 __u8 lpa; 117 __u8 elpe; 118 __u8 npss; 119 __u8 avscc; 120 __u8 apsta; 121 __le16 wctemp; 122 __le16 cctemp; 123 __u8 rsvd270[242]; 124 __u8 sqes; 125 __u8 cqes; 126 __u8 rsvd514[2]; 127 __le32 nn; 128 __le16 oncs; 129 __le16 fuses; 130 __u8 fna; 131 __u8 vwc; 132 __le16 awun; 133 __le16 awupf; 134 __u8 nvscc; 135 __u8 rsvd531; 136 __le16 acwu; 137 __u8 rsvd534[2]; 138 __le32 sgls; 139 __u8 rsvd540[1508]; 140 struct nvme_id_power_state psd[32]; 141 __u8 vs[1024]; 142 }; 143 144 enum { 145 NVME_CTRL_ONCS_COMPARE = 1 << 0, 146 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 147 NVME_CTRL_ONCS_DSM = 1 << 2, 148 NVME_CTRL_VWC_PRESENT = 1 << 0, 149 }; 150 151 struct nvme_lbaf { 152 __le16 ms; 153 __u8 ds; 154 __u8 rp; 155 }; 156 157 struct nvme_id_ns { 158 __le64 nsze; 159 __le64 ncap; 160 __le64 nuse; 161 __u8 nsfeat; 162 __u8 nlbaf; 163 __u8 flbas; 164 __u8 mc; 165 __u8 dpc; 166 __u8 dps; 167 __u8 nmic; 168 __u8 rescap; 169 __u8 fpi; 170 __u8 rsvd33; 171 __le16 nawun; 172 __le16 nawupf; 173 __le16 nacwu; 174 __le16 nabsn; 175 __le16 nabo; 176 __le16 nabspf; 177 __u16 rsvd46; 178 __le64 nvmcap[2]; 179 __u8 rsvd64[40]; 180 __u8 nguid[16]; 181 __u8 eui64[8]; 182 struct nvme_lbaf lbaf[16]; 183 __u8 rsvd192[192]; 184 __u8 vs[3712]; 185 }; 186 187 enum { 188 NVME_NS_FEAT_THIN = 1 << 0, 189 NVME_NS_FLBAS_LBA_MASK = 0xf, 190 NVME_NS_FLBAS_META_EXT = 0x10, 191 NVME_LBAF_RP_BEST = 0, 192 NVME_LBAF_RP_BETTER = 1, 193 NVME_LBAF_RP_GOOD = 2, 194 NVME_LBAF_RP_DEGRADED = 3, 195 NVME_NS_DPC_PI_LAST = 1 << 4, 196 NVME_NS_DPC_PI_FIRST = 1 << 3, 197 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 198 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 199 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 200 NVME_NS_DPS_PI_FIRST = 1 << 3, 201 NVME_NS_DPS_PI_MASK = 0x7, 202 NVME_NS_DPS_PI_TYPE1 = 1, 203 NVME_NS_DPS_PI_TYPE2 = 2, 204 NVME_NS_DPS_PI_TYPE3 = 3, 205 }; 206 207 struct nvme_smart_log { 208 __u8 critical_warning; 209 __u8 temperature[2]; 210 __u8 avail_spare; 211 __u8 spare_thresh; 212 __u8 percent_used; 213 __u8 rsvd6[26]; 214 __u8 data_units_read[16]; 215 __u8 data_units_written[16]; 216 __u8 host_reads[16]; 217 __u8 host_writes[16]; 218 __u8 ctrl_busy_time[16]; 219 __u8 power_cycles[16]; 220 __u8 power_on_hours[16]; 221 __u8 unsafe_shutdowns[16]; 222 __u8 media_errors[16]; 223 __u8 num_err_log_entries[16]; 224 __le32 warning_temp_time; 225 __le32 critical_comp_time; 226 __le16 temp_sensor[8]; 227 __u8 rsvd216[296]; 228 }; 229 230 enum { 231 NVME_SMART_CRIT_SPARE = 1 << 0, 232 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 233 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 234 NVME_SMART_CRIT_MEDIA = 1 << 3, 235 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 236 }; 237 238 enum { 239 NVME_AER_NOTICE_NS_CHANGED = 0x0002, 240 }; 241 242 struct nvme_lba_range_type { 243 __u8 type; 244 __u8 attributes; 245 __u8 rsvd2[14]; 246 __u64 slba; 247 __u64 nlb; 248 __u8 guid[16]; 249 __u8 rsvd48[16]; 250 }; 251 252 enum { 253 NVME_LBART_TYPE_FS = 0x01, 254 NVME_LBART_TYPE_RAID = 0x02, 255 NVME_LBART_TYPE_CACHE = 0x03, 256 NVME_LBART_TYPE_SWAP = 0x04, 257 258 NVME_LBART_ATTRIB_TEMP = 1 << 0, 259 NVME_LBART_ATTRIB_HIDE = 1 << 1, 260 }; 261 262 struct nvme_reservation_status { 263 __le32 gen; 264 __u8 rtype; 265 __u8 regctl[2]; 266 __u8 resv5[2]; 267 __u8 ptpls; 268 __u8 resv10[13]; 269 struct { 270 __le16 cntlid; 271 __u8 rcsts; 272 __u8 resv3[5]; 273 __le64 hostid; 274 __le64 rkey; 275 } regctl_ds[]; 276 }; 277 278 /* I/O commands */ 279 280 enum nvme_opcode { 281 nvme_cmd_flush = 0x00, 282 nvme_cmd_write = 0x01, 283 nvme_cmd_read = 0x02, 284 nvme_cmd_write_uncor = 0x04, 285 nvme_cmd_compare = 0x05, 286 nvme_cmd_write_zeroes = 0x08, 287 nvme_cmd_dsm = 0x09, 288 nvme_cmd_resv_register = 0x0d, 289 nvme_cmd_resv_report = 0x0e, 290 nvme_cmd_resv_acquire = 0x11, 291 nvme_cmd_resv_release = 0x15, 292 }; 293 294 struct nvme_common_command { 295 __u8 opcode; 296 __u8 flags; 297 __u16 command_id; 298 __le32 nsid; 299 __le32 cdw2[2]; 300 __le64 metadata; 301 __le64 prp1; 302 __le64 prp2; 303 __le32 cdw10[6]; 304 }; 305 306 struct nvme_rw_command { 307 __u8 opcode; 308 __u8 flags; 309 __u16 command_id; 310 __le32 nsid; 311 __u64 rsvd2; 312 __le64 metadata; 313 __le64 prp1; 314 __le64 prp2; 315 __le64 slba; 316 __le16 length; 317 __le16 control; 318 __le32 dsmgmt; 319 __le32 reftag; 320 __le16 apptag; 321 __le16 appmask; 322 }; 323 324 enum { 325 NVME_RW_LR = 1 << 15, 326 NVME_RW_FUA = 1 << 14, 327 NVME_RW_DSM_FREQ_UNSPEC = 0, 328 NVME_RW_DSM_FREQ_TYPICAL = 1, 329 NVME_RW_DSM_FREQ_RARE = 2, 330 NVME_RW_DSM_FREQ_READS = 3, 331 NVME_RW_DSM_FREQ_WRITES = 4, 332 NVME_RW_DSM_FREQ_RW = 5, 333 NVME_RW_DSM_FREQ_ONCE = 6, 334 NVME_RW_DSM_FREQ_PREFETCH = 7, 335 NVME_RW_DSM_FREQ_TEMP = 8, 336 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 337 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 338 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 339 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 340 NVME_RW_DSM_SEQ_REQ = 1 << 6, 341 NVME_RW_DSM_COMPRESSED = 1 << 7, 342 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 343 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 344 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 345 NVME_RW_PRINFO_PRACT = 1 << 13, 346 }; 347 348 struct nvme_dsm_cmd { 349 __u8 opcode; 350 __u8 flags; 351 __u16 command_id; 352 __le32 nsid; 353 __u64 rsvd2[2]; 354 __le64 prp1; 355 __le64 prp2; 356 __le32 nr; 357 __le32 attributes; 358 __u32 rsvd12[4]; 359 }; 360 361 enum { 362 NVME_DSMGMT_IDR = 1 << 0, 363 NVME_DSMGMT_IDW = 1 << 1, 364 NVME_DSMGMT_AD = 1 << 2, 365 }; 366 367 struct nvme_dsm_range { 368 __le32 cattr; 369 __le32 nlb; 370 __le64 slba; 371 }; 372 373 /* Admin commands */ 374 375 enum nvme_admin_opcode { 376 nvme_admin_delete_sq = 0x00, 377 nvme_admin_create_sq = 0x01, 378 nvme_admin_get_log_page = 0x02, 379 nvme_admin_delete_cq = 0x04, 380 nvme_admin_create_cq = 0x05, 381 nvme_admin_identify = 0x06, 382 nvme_admin_abort_cmd = 0x08, 383 nvme_admin_set_features = 0x09, 384 nvme_admin_get_features = 0x0a, 385 nvme_admin_async_event = 0x0c, 386 nvme_admin_activate_fw = 0x10, 387 nvme_admin_download_fw = 0x11, 388 nvme_admin_format_nvm = 0x80, 389 nvme_admin_security_send = 0x81, 390 nvme_admin_security_recv = 0x82, 391 }; 392 393 enum { 394 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 395 NVME_CQ_IRQ_ENABLED = (1 << 1), 396 NVME_SQ_PRIO_URGENT = (0 << 1), 397 NVME_SQ_PRIO_HIGH = (1 << 1), 398 NVME_SQ_PRIO_MEDIUM = (2 << 1), 399 NVME_SQ_PRIO_LOW = (3 << 1), 400 NVME_FEAT_ARBITRATION = 0x01, 401 NVME_FEAT_POWER_MGMT = 0x02, 402 NVME_FEAT_LBA_RANGE = 0x03, 403 NVME_FEAT_TEMP_THRESH = 0x04, 404 NVME_FEAT_ERR_RECOVERY = 0x05, 405 NVME_FEAT_VOLATILE_WC = 0x06, 406 NVME_FEAT_NUM_QUEUES = 0x07, 407 NVME_FEAT_IRQ_COALESCE = 0x08, 408 NVME_FEAT_IRQ_CONFIG = 0x09, 409 NVME_FEAT_WRITE_ATOMIC = 0x0a, 410 NVME_FEAT_ASYNC_EVENT = 0x0b, 411 NVME_FEAT_AUTO_PST = 0x0c, 412 NVME_FEAT_SW_PROGRESS = 0x80, 413 NVME_FEAT_HOST_ID = 0x81, 414 NVME_FEAT_RESV_MASK = 0x82, 415 NVME_FEAT_RESV_PERSIST = 0x83, 416 NVME_LOG_ERROR = 0x01, 417 NVME_LOG_SMART = 0x02, 418 NVME_LOG_FW_SLOT = 0x03, 419 NVME_LOG_RESERVATION = 0x80, 420 NVME_FWACT_REPL = (0 << 3), 421 NVME_FWACT_REPL_ACTV = (1 << 3), 422 NVME_FWACT_ACTV = (2 << 3), 423 }; 424 425 struct nvme_identify { 426 __u8 opcode; 427 __u8 flags; 428 __u16 command_id; 429 __le32 nsid; 430 __u64 rsvd2[2]; 431 __le64 prp1; 432 __le64 prp2; 433 __le32 cns; 434 __u32 rsvd11[5]; 435 }; 436 437 struct nvme_features { 438 __u8 opcode; 439 __u8 flags; 440 __u16 command_id; 441 __le32 nsid; 442 __u64 rsvd2[2]; 443 __le64 prp1; 444 __le64 prp2; 445 __le32 fid; 446 __le32 dword11; 447 __u32 rsvd12[4]; 448 }; 449 450 struct nvme_create_cq { 451 __u8 opcode; 452 __u8 flags; 453 __u16 command_id; 454 __u32 rsvd1[5]; 455 __le64 prp1; 456 __u64 rsvd8; 457 __le16 cqid; 458 __le16 qsize; 459 __le16 cq_flags; 460 __le16 irq_vector; 461 __u32 rsvd12[4]; 462 }; 463 464 struct nvme_create_sq { 465 __u8 opcode; 466 __u8 flags; 467 __u16 command_id; 468 __u32 rsvd1[5]; 469 __le64 prp1; 470 __u64 rsvd8; 471 __le16 sqid; 472 __le16 qsize; 473 __le16 sq_flags; 474 __le16 cqid; 475 __u32 rsvd12[4]; 476 }; 477 478 struct nvme_delete_queue { 479 __u8 opcode; 480 __u8 flags; 481 __u16 command_id; 482 __u32 rsvd1[9]; 483 __le16 qid; 484 __u16 rsvd10; 485 __u32 rsvd11[5]; 486 }; 487 488 struct nvme_abort_cmd { 489 __u8 opcode; 490 __u8 flags; 491 __u16 command_id; 492 __u32 rsvd1[9]; 493 __le16 sqid; 494 __u16 cid; 495 __u32 rsvd11[5]; 496 }; 497 498 struct nvme_download_firmware { 499 __u8 opcode; 500 __u8 flags; 501 __u16 command_id; 502 __u32 rsvd1[5]; 503 __le64 prp1; 504 __le64 prp2; 505 __le32 numd; 506 __le32 offset; 507 __u32 rsvd12[4]; 508 }; 509 510 struct nvme_format_cmd { 511 __u8 opcode; 512 __u8 flags; 513 __u16 command_id; 514 __le32 nsid; 515 __u64 rsvd2[4]; 516 __le32 cdw10; 517 __u32 rsvd11[5]; 518 }; 519 520 struct nvme_command { 521 union { 522 struct nvme_common_command common; 523 struct nvme_rw_command rw; 524 struct nvme_identify identify; 525 struct nvme_features features; 526 struct nvme_create_cq create_cq; 527 struct nvme_create_sq create_sq; 528 struct nvme_delete_queue delete_queue; 529 struct nvme_download_firmware dlfw; 530 struct nvme_format_cmd format; 531 struct nvme_dsm_cmd dsm; 532 struct nvme_abort_cmd abort; 533 }; 534 }; 535 536 enum { 537 NVME_SC_SUCCESS = 0x0, 538 NVME_SC_INVALID_OPCODE = 0x1, 539 NVME_SC_INVALID_FIELD = 0x2, 540 NVME_SC_CMDID_CONFLICT = 0x3, 541 NVME_SC_DATA_XFER_ERROR = 0x4, 542 NVME_SC_POWER_LOSS = 0x5, 543 NVME_SC_INTERNAL = 0x6, 544 NVME_SC_ABORT_REQ = 0x7, 545 NVME_SC_ABORT_QUEUE = 0x8, 546 NVME_SC_FUSED_FAIL = 0x9, 547 NVME_SC_FUSED_MISSING = 0xa, 548 NVME_SC_INVALID_NS = 0xb, 549 NVME_SC_CMD_SEQ_ERROR = 0xc, 550 NVME_SC_SGL_INVALID_LAST = 0xd, 551 NVME_SC_SGL_INVALID_COUNT = 0xe, 552 NVME_SC_SGL_INVALID_DATA = 0xf, 553 NVME_SC_SGL_INVALID_METADATA = 0x10, 554 NVME_SC_SGL_INVALID_TYPE = 0x11, 555 NVME_SC_LBA_RANGE = 0x80, 556 NVME_SC_CAP_EXCEEDED = 0x81, 557 NVME_SC_NS_NOT_READY = 0x82, 558 NVME_SC_RESERVATION_CONFLICT = 0x83, 559 NVME_SC_CQ_INVALID = 0x100, 560 NVME_SC_QID_INVALID = 0x101, 561 NVME_SC_QUEUE_SIZE = 0x102, 562 NVME_SC_ABORT_LIMIT = 0x103, 563 NVME_SC_ABORT_MISSING = 0x104, 564 NVME_SC_ASYNC_LIMIT = 0x105, 565 NVME_SC_FIRMWARE_SLOT = 0x106, 566 NVME_SC_FIRMWARE_IMAGE = 0x107, 567 NVME_SC_INVALID_VECTOR = 0x108, 568 NVME_SC_INVALID_LOG_PAGE = 0x109, 569 NVME_SC_INVALID_FORMAT = 0x10a, 570 NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b, 571 NVME_SC_INVALID_QUEUE = 0x10c, 572 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 573 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 574 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 575 NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110, 576 NVME_SC_BAD_ATTRIBUTES = 0x180, 577 NVME_SC_INVALID_PI = 0x181, 578 NVME_SC_READ_ONLY = 0x182, 579 NVME_SC_WRITE_FAULT = 0x280, 580 NVME_SC_READ_ERROR = 0x281, 581 NVME_SC_GUARD_CHECK = 0x282, 582 NVME_SC_APPTAG_CHECK = 0x283, 583 NVME_SC_REFTAG_CHECK = 0x284, 584 NVME_SC_COMPARE_FAILED = 0x285, 585 NVME_SC_ACCESS_DENIED = 0x286, 586 NVME_SC_DNR = 0x4000, 587 }; 588 589 struct nvme_completion { 590 __le32 result; /* Used by admin commands to return data */ 591 __u32 rsvd; 592 __le16 sq_head; /* how much of this queue may be reclaimed */ 593 __le16 sq_id; /* submission queue that generated this entry */ 594 __u16 command_id; /* of the command which completed */ 595 __le16 status; /* did the command fail, and if so, why? */ 596 }; 597 598 #define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8)) 599 600 #endif /* _LINUX_NVME_H */ 601