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1 /*
2  * rt286.c  --  RT286 ALSA SoC audio codec driver
3  *
4  * Copyright 2013 Realtek Semiconductor Corp.
5  * Author: Bard Liao <bardliao@realtek.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/dmi.h>
21 #include <linux/acpi.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/jack.h>
30 #include <linux/workqueue.h>
31 #include <sound/rt286.h>
32 
33 #include "rl6347a.h"
34 #include "rt286.h"
35 
36 #define RT286_VENDOR_ID 0x10ec0286
37 #define RT288_VENDOR_ID 0x10ec0288
38 
39 struct rt286_priv {
40 	struct reg_default *index_cache;
41 	int index_cache_size;
42 	struct regmap *regmap;
43 	struct snd_soc_codec *codec;
44 	struct rt286_platform_data pdata;
45 	struct i2c_client *i2c;
46 	struct snd_soc_jack *jack;
47 	struct delayed_work jack_detect_work;
48 	int sys_clk;
49 	int clk_id;
50 };
51 
52 static const struct reg_default rt286_index_def[] = {
53 	{ 0x01, 0xaaaa },
54 	{ 0x02, 0x8aaa },
55 	{ 0x03, 0x0002 },
56 	{ 0x04, 0xaf01 },
57 	{ 0x08, 0x000d },
58 	{ 0x09, 0xd810 },
59 	{ 0x0a, 0x0120 },
60 	{ 0x0b, 0x0000 },
61 	{ 0x0d, 0x2800 },
62 	{ 0x0f, 0x0000 },
63 	{ 0x19, 0x0a17 },
64 	{ 0x20, 0x0020 },
65 	{ 0x33, 0x0208 },
66 	{ 0x49, 0x0004 },
67 	{ 0x4f, 0x50e9 },
68 	{ 0x50, 0x2000 },
69 	{ 0x63, 0x2902 },
70 	{ 0x67, 0x1111 },
71 	{ 0x68, 0x1016 },
72 	{ 0x69, 0x273f },
73 };
74 #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
75 
76 static const struct reg_default rt286_reg[] = {
77 	{ 0x00170500, 0x00000400 },
78 	{ 0x00220000, 0x00000031 },
79 	{ 0x00239000, 0x0000007f },
80 	{ 0x0023a000, 0x0000007f },
81 	{ 0x00270500, 0x00000400 },
82 	{ 0x00370500, 0x00000400 },
83 	{ 0x00870500, 0x00000400 },
84 	{ 0x00920000, 0x00000031 },
85 	{ 0x00935000, 0x000000c3 },
86 	{ 0x00936000, 0x000000c3 },
87 	{ 0x00970500, 0x00000400 },
88 	{ 0x00b37000, 0x00000097 },
89 	{ 0x00b37200, 0x00000097 },
90 	{ 0x00b37300, 0x00000097 },
91 	{ 0x00c37000, 0x00000000 },
92 	{ 0x00c37100, 0x00000080 },
93 	{ 0x01270500, 0x00000400 },
94 	{ 0x01370500, 0x00000400 },
95 	{ 0x01371f00, 0x411111f0 },
96 	{ 0x01439000, 0x00000080 },
97 	{ 0x0143a000, 0x00000080 },
98 	{ 0x01470700, 0x00000000 },
99 	{ 0x01470500, 0x00000400 },
100 	{ 0x01470c00, 0x00000000 },
101 	{ 0x01470100, 0x00000000 },
102 	{ 0x01837000, 0x00000000 },
103 	{ 0x01870500, 0x00000400 },
104 	{ 0x02050000, 0x00000000 },
105 	{ 0x02139000, 0x00000080 },
106 	{ 0x0213a000, 0x00000080 },
107 	{ 0x02170100, 0x00000000 },
108 	{ 0x02170500, 0x00000400 },
109 	{ 0x02170700, 0x00000000 },
110 	{ 0x02270100, 0x00000000 },
111 	{ 0x02370100, 0x00000000 },
112 	{ 0x01870700, 0x00000020 },
113 	{ 0x00830000, 0x000000c3 },
114 	{ 0x00930000, 0x000000c3 },
115 	{ 0x01270700, 0x00000000 },
116 };
117 
rt286_volatile_register(struct device * dev,unsigned int reg)118 static bool rt286_volatile_register(struct device *dev, unsigned int reg)
119 {
120 	switch (reg) {
121 	case 0 ... 0xff:
122 	case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
123 	case RT286_GET_HP_SENSE:
124 	case RT286_GET_MIC1_SENSE:
125 	case RT286_PROC_COEF:
126 		return true;
127 	default:
128 		return false;
129 	}
130 
131 
132 }
133 
rt286_readable_register(struct device * dev,unsigned int reg)134 static bool rt286_readable_register(struct device *dev, unsigned int reg)
135 {
136 	switch (reg) {
137 	case 0 ... 0xff:
138 	case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
139 	case RT286_GET_HP_SENSE:
140 	case RT286_GET_MIC1_SENSE:
141 	case RT286_SET_AUDIO_POWER:
142 	case RT286_SET_HPO_POWER:
143 	case RT286_SET_SPK_POWER:
144 	case RT286_SET_DMIC1_POWER:
145 	case RT286_SPK_MUX:
146 	case RT286_HPO_MUX:
147 	case RT286_ADC0_MUX:
148 	case RT286_ADC1_MUX:
149 	case RT286_SET_MIC1:
150 	case RT286_SET_PIN_HPO:
151 	case RT286_SET_PIN_SPK:
152 	case RT286_SET_PIN_DMIC1:
153 	case RT286_SPK_EAPD:
154 	case RT286_SET_AMP_GAIN_HPO:
155 	case RT286_SET_DMIC2_DEFAULT:
156 	case RT286_DACL_GAIN:
157 	case RT286_DACR_GAIN:
158 	case RT286_ADCL_GAIN:
159 	case RT286_ADCR_GAIN:
160 	case RT286_MIC_GAIN:
161 	case RT286_SPOL_GAIN:
162 	case RT286_SPOR_GAIN:
163 	case RT286_HPOL_GAIN:
164 	case RT286_HPOR_GAIN:
165 	case RT286_F_DAC_SWITCH:
166 	case RT286_F_RECMIX_SWITCH:
167 	case RT286_REC_MIC_SWITCH:
168 	case RT286_REC_I2S_SWITCH:
169 	case RT286_REC_LINE_SWITCH:
170 	case RT286_REC_BEEP_SWITCH:
171 	case RT286_DAC_FORMAT:
172 	case RT286_ADC_FORMAT:
173 	case RT286_COEF_INDEX:
174 	case RT286_PROC_COEF:
175 	case RT286_SET_AMP_GAIN_ADC_IN1:
176 	case RT286_SET_AMP_GAIN_ADC_IN2:
177 	case RT286_SET_GPIO_MASK:
178 	case RT286_SET_GPIO_DIRECTION:
179 	case RT286_SET_GPIO_DATA:
180 	case RT286_SET_POWER(RT286_DAC_OUT1):
181 	case RT286_SET_POWER(RT286_DAC_OUT2):
182 	case RT286_SET_POWER(RT286_ADC_IN1):
183 	case RT286_SET_POWER(RT286_ADC_IN2):
184 	case RT286_SET_POWER(RT286_DMIC2):
185 	case RT286_SET_POWER(RT286_MIC1):
186 		return true;
187 	default:
188 		return false;
189 	}
190 }
191 
192 #ifdef CONFIG_PM
rt286_index_sync(struct snd_soc_codec * codec)193 static void rt286_index_sync(struct snd_soc_codec *codec)
194 {
195 	struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
196 	int i;
197 
198 	for (i = 0; i < INDEX_CACHE_SIZE; i++) {
199 		snd_soc_write(codec, rt286->index_cache[i].reg,
200 				  rt286->index_cache[i].def);
201 	}
202 }
203 #endif
204 
205 static int rt286_support_power_controls[] = {
206 	RT286_DAC_OUT1,
207 	RT286_DAC_OUT2,
208 	RT286_ADC_IN1,
209 	RT286_ADC_IN2,
210 	RT286_MIC1,
211 	RT286_DMIC1,
212 	RT286_DMIC2,
213 	RT286_SPK_OUT,
214 	RT286_HP_OUT,
215 };
216 #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
217 
rt286_jack_detect(struct rt286_priv * rt286,bool * hp,bool * mic)218 static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
219 {
220 	struct snd_soc_dapm_context *dapm;
221 	unsigned int val, buf;
222 
223 	*hp = false;
224 	*mic = false;
225 
226 	if (!rt286->codec)
227 		return -EINVAL;
228 
229 	dapm = snd_soc_codec_get_dapm(rt286->codec);
230 
231 	if (rt286->pdata.cbj_en) {
232 		regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
233 		*hp = buf & 0x80000000;
234 		if (*hp) {
235 			/* power on HV,VERF */
236 			regmap_update_bits(rt286->regmap,
237 				RT286_DC_GAIN, 0x200, 0x200);
238 
239 			snd_soc_dapm_force_enable_pin(dapm, "HV");
240 			snd_soc_dapm_force_enable_pin(dapm, "VREF");
241 			/* power LDO1 */
242 			snd_soc_dapm_force_enable_pin(dapm, "LDO1");
243 			snd_soc_dapm_sync(dapm);
244 
245 			regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
246 			msleep(50);
247 
248 			regmap_update_bits(rt286->regmap,
249 				RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
250 			msleep(300);
251 			regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
252 
253 			if (0x0070 == (val & 0x0070)) {
254 				*mic = true;
255 			} else {
256 				regmap_update_bits(rt286->regmap,
257 					RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
258 				msleep(300);
259 				regmap_read(rt286->regmap,
260 					RT286_CBJ_CTRL2, &val);
261 				if (0x0070 == (val & 0x0070))
262 					*mic = true;
263 				else
264 					*mic = false;
265 			}
266 			regmap_update_bits(rt286->regmap,
267 				RT286_DC_GAIN, 0x200, 0x0);
268 
269 		} else {
270 			*mic = false;
271 			regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
272 		}
273 	} else {
274 		regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
275 		*hp = buf & 0x80000000;
276 		regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
277 		*mic = buf & 0x80000000;
278 	}
279 
280 	snd_soc_dapm_disable_pin(dapm, "HV");
281 	snd_soc_dapm_disable_pin(dapm, "VREF");
282 	if (!*hp)
283 		snd_soc_dapm_disable_pin(dapm, "LDO1");
284 	snd_soc_dapm_sync(dapm);
285 
286 	return 0;
287 }
288 
rt286_jack_detect_work(struct work_struct * work)289 static void rt286_jack_detect_work(struct work_struct *work)
290 {
291 	struct rt286_priv *rt286 =
292 		container_of(work, struct rt286_priv, jack_detect_work.work);
293 	int status = 0;
294 	bool hp = false;
295 	bool mic = false;
296 
297 	rt286_jack_detect(rt286, &hp, &mic);
298 
299 	if (hp == true)
300 		status |= SND_JACK_HEADPHONE;
301 
302 	if (mic == true)
303 		status |= SND_JACK_MICROPHONE;
304 
305 	snd_soc_jack_report(rt286->jack, status,
306 		SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
307 }
308 
rt286_mic_detect(struct snd_soc_codec * codec,struct snd_soc_jack * jack)309 int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
310 {
311 	struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
312 	struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
313 
314 	rt286->jack = jack;
315 
316 	if (jack) {
317 		/* enable IRQ */
318 		if (rt286->jack->status & SND_JACK_HEADPHONE)
319 			snd_soc_dapm_force_enable_pin(dapm, "LDO1");
320 		regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
321 		/* Send an initial empty report */
322 		snd_soc_jack_report(rt286->jack, rt286->jack->status,
323 			SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
324 	} else {
325 		/* disable IRQ */
326 		regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
327 		snd_soc_dapm_disable_pin(dapm, "LDO1");
328 	}
329 	snd_soc_dapm_sync(dapm);
330 
331 	return 0;
332 }
333 EXPORT_SYMBOL_GPL(rt286_mic_detect);
334 
is_mclk_mode(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)335 static int is_mclk_mode(struct snd_soc_dapm_widget *source,
336 			 struct snd_soc_dapm_widget *sink)
337 {
338 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
339 	struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
340 
341 	if (rt286->clk_id == RT286_SCLK_S_MCLK)
342 		return 1;
343 	else
344 		return 0;
345 }
346 
347 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
348 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
349 
350 static const struct snd_kcontrol_new rt286_snd_controls[] = {
351 	SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
352 			    RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
353 	SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
354 			    RT286_ADCR_GAIN, 7, 1, 1),
355 	SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
356 			    RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
357 	SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
358 			    0, 0x3, 0, mic_vol_tlv),
359 	SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
360 			    RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
361 };
362 
363 /* Digital Mixer */
364 static const struct snd_kcontrol_new rt286_front_mix[] = {
365 	SOC_DAPM_SINGLE("DAC Switch",  RT286_F_DAC_SWITCH,
366 			RT286_MUTE_SFT, 1, 1),
367 	SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
368 			RT286_MUTE_SFT, 1, 1),
369 };
370 
371 /* Analog Input Mixer */
372 static const struct snd_kcontrol_new rt286_rec_mix[] = {
373 	SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
374 			RT286_MUTE_SFT, 1, 1),
375 	SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
376 			RT286_MUTE_SFT, 1, 1),
377 	SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
378 			RT286_MUTE_SFT, 1, 1),
379 	SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
380 			RT286_MUTE_SFT, 1, 1),
381 };
382 
383 static const struct snd_kcontrol_new spo_enable_control =
384 	SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
385 			RT286_SET_PIN_SFT, 1, 0);
386 
387 static const struct snd_kcontrol_new hpol_enable_control =
388 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
389 			RT286_MUTE_SFT, 1, 1);
390 
391 static const struct snd_kcontrol_new hpor_enable_control =
392 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
393 			RT286_MUTE_SFT, 1, 1);
394 
395 /* ADC0 source */
396 static const char * const rt286_adc_src[] = {
397 	"Mic", "RECMIX", "Dmic"
398 };
399 
400 static const int rt286_adc_values[] = {
401 	0, 4, 5,
402 };
403 
404 static SOC_VALUE_ENUM_SINGLE_DECL(
405 	rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
406 	RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
407 
408 static const struct snd_kcontrol_new rt286_adc0_mux =
409 	SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
410 
411 static SOC_VALUE_ENUM_SINGLE_DECL(
412 	rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
413 	RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
414 
415 static const struct snd_kcontrol_new rt286_adc1_mux =
416 	SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
417 
418 static const char * const rt286_dac_src[] = {
419 	"Front", "Surround"
420 };
421 /* HP-OUT source */
422 static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
423 				0, rt286_dac_src);
424 
425 static const struct snd_kcontrol_new rt286_hpo_mux =
426 SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
427 
428 /* SPK-OUT source */
429 static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
430 				0, rt286_dac_src);
431 
432 static const struct snd_kcontrol_new rt286_spo_mux =
433 SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
434 
rt286_spk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)435 static int rt286_spk_event(struct snd_soc_dapm_widget *w,
436 			    struct snd_kcontrol *kcontrol, int event)
437 {
438 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
439 
440 	switch (event) {
441 	case SND_SOC_DAPM_POST_PMU:
442 		snd_soc_write(codec,
443 			RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
444 		break;
445 	case SND_SOC_DAPM_PRE_PMD:
446 		snd_soc_write(codec,
447 			RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
448 		break;
449 
450 	default:
451 		return 0;
452 	}
453 
454 	return 0;
455 }
456 
rt286_set_dmic1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)457 static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
458 				  struct snd_kcontrol *kcontrol, int event)
459 {
460 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
461 
462 	switch (event) {
463 	case SND_SOC_DAPM_POST_PMU:
464 		snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
465 		break;
466 	case SND_SOC_DAPM_PRE_PMD:
467 		snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
468 		break;
469 	default:
470 		return 0;
471 	}
472 
473 	return 0;
474 }
475 
rt286_vref_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)476 static int rt286_vref_event(struct snd_soc_dapm_widget *w,
477 			     struct snd_kcontrol *kcontrol, int event)
478 {
479 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
480 
481 	switch (event) {
482 	case SND_SOC_DAPM_PRE_PMU:
483 		snd_soc_update_bits(codec,
484 			RT286_CBJ_CTRL1, 0x0400, 0x0000);
485 		mdelay(50);
486 		break;
487 	default:
488 		return 0;
489 	}
490 
491 	return 0;
492 }
493 
rt286_ldo2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)494 static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
495 			     struct snd_kcontrol *kcontrol, int event)
496 {
497 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
498 
499 	switch (event) {
500 	case SND_SOC_DAPM_POST_PMU:
501 		snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08);
502 		break;
503 	case SND_SOC_DAPM_PRE_PMD:
504 		snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30);
505 		break;
506 	default:
507 		return 0;
508 	}
509 
510 	return 0;
511 }
512 
rt286_mic1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)513 static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
514 			     struct snd_kcontrol *kcontrol, int event)
515 {
516 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
517 
518 	switch (event) {
519 	case SND_SOC_DAPM_PRE_PMU:
520 		snd_soc_update_bits(codec,
521 			RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
522 		snd_soc_update_bits(codec,
523 			RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
524 		break;
525 	case SND_SOC_DAPM_POST_PMD:
526 		snd_soc_update_bits(codec,
527 			RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
528 		snd_soc_update_bits(codec,
529 			RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
530 		break;
531 	default:
532 		return 0;
533 	}
534 
535 	return 0;
536 }
537 
538 static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
539 	SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
540 		12, 1, NULL, 0),
541 	SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
542 		0, 1, rt286_vref_event, SND_SOC_DAPM_PRE_PMU),
543 	SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
544 		2, 0, NULL, 0),
545 	SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
546 		13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
547 		SND_SOC_DAPM_POST_PMU),
548 	SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
549 		5, 0, NULL, 0),
550 	SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
551 		0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
552 		SND_SOC_DAPM_POST_PMD),
553 
554 	/* Input Lines */
555 	SND_SOC_DAPM_INPUT("DMIC1 Pin"),
556 	SND_SOC_DAPM_INPUT("DMIC2 Pin"),
557 	SND_SOC_DAPM_INPUT("MIC1"),
558 	SND_SOC_DAPM_INPUT("LINE1"),
559 	SND_SOC_DAPM_INPUT("Beep"),
560 
561 	/* DMIC */
562 	SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
563 		NULL, 0, rt286_set_dmic1_event,
564 		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
565 	SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
566 		NULL, 0),
567 	SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
568 		0, 0, NULL, 0),
569 
570 	/* REC Mixer */
571 	SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
572 		rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
573 
574 	/* ADCs */
575 	SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
576 	SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
577 
578 	/* ADC Mux */
579 	SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
580 		&rt286_adc0_mux),
581 	SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
582 		&rt286_adc1_mux),
583 
584 	/* Audio Interface */
585 	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
586 	SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
587 	SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
588 	SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
589 
590 	/* Output Side */
591 	/* DACs */
592 	SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
593 	SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
594 
595 	/* Output Mux */
596 	SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
597 	SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
598 
599 	SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
600 		RT286_SET_PIN_SFT, 0, NULL, 0),
601 
602 	/* Output Mixer */
603 	SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
604 			rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
605 	SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
606 			NULL, 0),
607 
608 	/* Output Pga */
609 	SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
610 		&spo_enable_control, rt286_spk_event,
611 		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
612 	SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
613 		&hpol_enable_control),
614 	SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
615 		&hpor_enable_control),
616 
617 	/* Output Lines */
618 	SND_SOC_DAPM_OUTPUT("SPOL"),
619 	SND_SOC_DAPM_OUTPUT("SPOR"),
620 	SND_SOC_DAPM_OUTPUT("HPO Pin"),
621 	SND_SOC_DAPM_OUTPUT("SPDIF"),
622 };
623 
624 static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
625 	{"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
626 	{"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
627 	{"Front", NULL, "MCLK MODE", is_mclk_mode},
628 	{"Surround", NULL, "MCLK MODE", is_mclk_mode},
629 
630 	{"HP Power", NULL, "LDO1"},
631 	{"HP Power", NULL, "LDO2"},
632 
633 	{"MIC1", NULL, "LDO1"},
634 	{"MIC1", NULL, "LDO2"},
635 	{"MIC1", NULL, "HV"},
636 	{"MIC1", NULL, "VREF"},
637 	{"MIC1", NULL, "MIC1 Input Buffer"},
638 
639 	{"SPO", NULL, "LDO1"},
640 	{"SPO", NULL, "LDO2"},
641 	{"SPO", NULL, "HV"},
642 	{"SPO", NULL, "VREF"},
643 
644 	{"DMIC1", NULL, "DMIC1 Pin"},
645 	{"DMIC2", NULL, "DMIC2 Pin"},
646 	{"DMIC1", NULL, "DMIC Receiver"},
647 	{"DMIC2", NULL, "DMIC Receiver"},
648 
649 	{"RECMIX", "Beep Switch", "Beep"},
650 	{"RECMIX", "Line1 Switch", "LINE1"},
651 	{"RECMIX", "Mic1 Switch", "MIC1"},
652 
653 	{"ADC 0 Mux", "Dmic", "DMIC1"},
654 	{"ADC 0 Mux", "RECMIX", "RECMIX"},
655 	{"ADC 0 Mux", "Mic", "MIC1"},
656 	{"ADC 1 Mux", "Dmic", "DMIC2"},
657 	{"ADC 1 Mux", "RECMIX", "RECMIX"},
658 	{"ADC 1 Mux", "Mic", "MIC1"},
659 
660 	{"ADC 0", NULL, "ADC 0 Mux"},
661 	{"ADC 1", NULL, "ADC 1 Mux"},
662 
663 	{"AIF1TX", NULL, "ADC 0"},
664 	{"AIF2TX", NULL, "ADC 1"},
665 
666 	{"DAC 0", NULL, "AIF1RX"},
667 	{"DAC 1", NULL, "AIF2RX"},
668 
669 	{"Front", "DAC Switch", "DAC 0"},
670 	{"Front", "RECMIX Switch", "RECMIX"},
671 
672 	{"Surround", NULL, "DAC 1"},
673 
674 	{"SPK Mux", "Front", "Front"},
675 	{"SPK Mux", "Surround", "Surround"},
676 
677 	{"HPO Mux", "Front", "Front"},
678 	{"HPO Mux", "Surround", "Surround"},
679 
680 	{"SPO", "Switch", "SPK Mux"},
681 	{"HPO L", "Switch", "HPO Mux"},
682 	{"HPO R", "Switch", "HPO Mux"},
683 	{"HPO L", NULL, "HP Power"},
684 	{"HPO R", NULL, "HP Power"},
685 
686 	{"SPOL", NULL, "SPO"},
687 	{"SPOR", NULL, "SPO"},
688 	{"HPO Pin", NULL, "HPO L"},
689 	{"HPO Pin", NULL, "HPO R"},
690 };
691 
rt286_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)692 static int rt286_hw_params(struct snd_pcm_substream *substream,
693 			    struct snd_pcm_hw_params *params,
694 			    struct snd_soc_dai *dai)
695 {
696 	struct snd_soc_codec *codec = dai->codec;
697 	struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
698 	unsigned int val = 0;
699 	int d_len_code;
700 
701 	switch (params_rate(params)) {
702 	/* bit 14 0:48K 1:44.1K */
703 	case 44100:
704 		val |= 0x4000;
705 		break;
706 	case 48000:
707 		break;
708 	default:
709 		dev_err(codec->dev, "Unsupported sample rate %d\n",
710 					params_rate(params));
711 		return -EINVAL;
712 	}
713 	switch (rt286->sys_clk) {
714 	case 12288000:
715 	case 24576000:
716 		if (params_rate(params) != 48000) {
717 			dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
718 					params_rate(params), rt286->sys_clk);
719 			return -EINVAL;
720 		}
721 		break;
722 	case 11289600:
723 	case 22579200:
724 		if (params_rate(params) != 44100) {
725 			dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
726 					params_rate(params), rt286->sys_clk);
727 			return -EINVAL;
728 		}
729 		break;
730 	}
731 
732 	if (params_channels(params) <= 16) {
733 		/* bit 3:0 Number of Channel */
734 		val |= (params_channels(params) - 1);
735 	} else {
736 		dev_err(codec->dev, "Unsupported channels %d\n",
737 					params_channels(params));
738 		return -EINVAL;
739 	}
740 
741 	d_len_code = 0;
742 	switch (params_width(params)) {
743 	/* bit 6:4 Bits per Sample */
744 	case 16:
745 		d_len_code = 0;
746 		val |= (0x1 << 4);
747 		break;
748 	case 32:
749 		d_len_code = 2;
750 		val |= (0x4 << 4);
751 		break;
752 	case 20:
753 		d_len_code = 1;
754 		val |= (0x2 << 4);
755 		break;
756 	case 24:
757 		d_len_code = 2;
758 		val |= (0x3 << 4);
759 		break;
760 	case 8:
761 		d_len_code = 3;
762 		break;
763 	default:
764 		return -EINVAL;
765 	}
766 
767 	snd_soc_update_bits(codec,
768 		RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
769 	dev_dbg(codec->dev, "format val = 0x%x\n", val);
770 
771 	snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
772 	snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
773 
774 	return 0;
775 }
776 
rt286_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)777 static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
778 {
779 	struct snd_soc_codec *codec = dai->codec;
780 
781 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
782 	case SND_SOC_DAIFMT_CBM_CFM:
783 		snd_soc_update_bits(codec,
784 			RT286_I2S_CTRL1, 0x800, 0x800);
785 		break;
786 	case SND_SOC_DAIFMT_CBS_CFS:
787 		snd_soc_update_bits(codec,
788 			RT286_I2S_CTRL1, 0x800, 0x0);
789 		break;
790 	default:
791 		return -EINVAL;
792 	}
793 
794 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
795 	case SND_SOC_DAIFMT_I2S:
796 		snd_soc_update_bits(codec,
797 			RT286_I2S_CTRL1, 0x300, 0x0);
798 		break;
799 	case SND_SOC_DAIFMT_LEFT_J:
800 		snd_soc_update_bits(codec,
801 			RT286_I2S_CTRL1, 0x300, 0x1 << 8);
802 		break;
803 	case SND_SOC_DAIFMT_DSP_A:
804 		snd_soc_update_bits(codec,
805 			RT286_I2S_CTRL1, 0x300, 0x2 << 8);
806 		break;
807 	case SND_SOC_DAIFMT_DSP_B:
808 		snd_soc_update_bits(codec,
809 			RT286_I2S_CTRL1, 0x300, 0x3 << 8);
810 		break;
811 	default:
812 		return -EINVAL;
813 	}
814 	/* bit 15 Stream Type 0:PCM 1:Non-PCM */
815 	snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
816 	snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
817 
818 	return 0;
819 }
820 
rt286_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)821 static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
822 				int clk_id, unsigned int freq, int dir)
823 {
824 	struct snd_soc_codec *codec = dai->codec;
825 	struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
826 
827 	dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
828 
829 	if (RT286_SCLK_S_MCLK == clk_id) {
830 		snd_soc_update_bits(codec,
831 			RT286_I2S_CTRL2, 0x0100, 0x0);
832 		snd_soc_update_bits(codec,
833 			RT286_PLL_CTRL1, 0x20, 0x20);
834 	} else {
835 		snd_soc_update_bits(codec,
836 			RT286_I2S_CTRL2, 0x0100, 0x0100);
837 		snd_soc_update_bits(codec,
838 			RT286_PLL_CTRL, 0x4, 0x4);
839 		snd_soc_update_bits(codec,
840 			RT286_PLL_CTRL1, 0x20, 0x0);
841 	}
842 
843 	switch (freq) {
844 	case 19200000:
845 		if (RT286_SCLK_S_MCLK == clk_id) {
846 			dev_err(codec->dev, "Should not use MCLK\n");
847 			return -EINVAL;
848 		}
849 		snd_soc_update_bits(codec,
850 			RT286_I2S_CTRL2, 0x40, 0x40);
851 		break;
852 	case 24000000:
853 		if (RT286_SCLK_S_MCLK == clk_id) {
854 			dev_err(codec->dev, "Should not use MCLK\n");
855 			return -EINVAL;
856 		}
857 		snd_soc_update_bits(codec,
858 			RT286_I2S_CTRL2, 0x40, 0x0);
859 		break;
860 	case 12288000:
861 	case 11289600:
862 		snd_soc_update_bits(codec,
863 			RT286_I2S_CTRL2, 0x8, 0x0);
864 		snd_soc_update_bits(codec,
865 			RT286_CLK_DIV, 0xfc1e, 0x0004);
866 		break;
867 	case 24576000:
868 	case 22579200:
869 		snd_soc_update_bits(codec,
870 			RT286_I2S_CTRL2, 0x8, 0x8);
871 		snd_soc_update_bits(codec,
872 			RT286_CLK_DIV, 0xfc1e, 0x5406);
873 		break;
874 	default:
875 		dev_err(codec->dev, "Unsupported system clock\n");
876 		return -EINVAL;
877 	}
878 
879 	rt286->sys_clk = freq;
880 	rt286->clk_id = clk_id;
881 
882 	return 0;
883 }
884 
rt286_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)885 static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
886 {
887 	struct snd_soc_codec *codec = dai->codec;
888 
889 	dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
890 	if (50 == ratio)
891 		snd_soc_update_bits(codec,
892 			RT286_I2S_CTRL1, 0x1000, 0x1000);
893 	else
894 		snd_soc_update_bits(codec,
895 			RT286_I2S_CTRL1, 0x1000, 0x0);
896 
897 
898 	return 0;
899 }
900 
rt286_set_bias_level(struct snd_soc_codec * codec,enum snd_soc_bias_level level)901 static int rt286_set_bias_level(struct snd_soc_codec *codec,
902 				 enum snd_soc_bias_level level)
903 {
904 	switch (level) {
905 	case SND_SOC_BIAS_PREPARE:
906 		if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
907 			snd_soc_write(codec,
908 				RT286_SET_AUDIO_POWER, AC_PWRST_D0);
909 			snd_soc_update_bits(codec,
910 				RT286_DC_GAIN, 0x200, 0x200);
911 		}
912 		break;
913 
914 	case SND_SOC_BIAS_ON:
915 		mdelay(10);
916 		snd_soc_update_bits(codec,
917 			RT286_CBJ_CTRL1, 0x0400, 0x0400);
918 		snd_soc_update_bits(codec,
919 			RT286_DC_GAIN, 0x200, 0x0);
920 
921 		break;
922 
923 	case SND_SOC_BIAS_STANDBY:
924 		snd_soc_write(codec,
925 			RT286_SET_AUDIO_POWER, AC_PWRST_D3);
926 		snd_soc_update_bits(codec,
927 			RT286_CBJ_CTRL1, 0x0400, 0x0000);
928 		break;
929 
930 	default:
931 		break;
932 	}
933 
934 	return 0;
935 }
936 
rt286_irq(int irq,void * data)937 static irqreturn_t rt286_irq(int irq, void *data)
938 {
939 	struct rt286_priv *rt286 = data;
940 	bool hp = false;
941 	bool mic = false;
942 	int status = 0;
943 
944 	rt286_jack_detect(rt286, &hp, &mic);
945 
946 	/* Clear IRQ */
947 	regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
948 
949 	if (hp == true)
950 		status |= SND_JACK_HEADPHONE;
951 
952 	if (mic == true)
953 		status |= SND_JACK_MICROPHONE;
954 
955 	snd_soc_jack_report(rt286->jack, status,
956 		SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
957 
958 	pm_wakeup_event(&rt286->i2c->dev, 300);
959 
960 	return IRQ_HANDLED;
961 }
962 
rt286_probe(struct snd_soc_codec * codec)963 static int rt286_probe(struct snd_soc_codec *codec)
964 {
965 	struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
966 
967 	rt286->codec = codec;
968 
969 	if (rt286->i2c->irq) {
970 		regmap_update_bits(rt286->regmap,
971 					RT286_IRQ_CTRL, 0x2, 0x2);
972 
973 		INIT_DELAYED_WORK(&rt286->jack_detect_work,
974 					rt286_jack_detect_work);
975 		schedule_delayed_work(&rt286->jack_detect_work,
976 					msecs_to_jiffies(1250));
977 	}
978 
979 	return 0;
980 }
981 
rt286_remove(struct snd_soc_codec * codec)982 static int rt286_remove(struct snd_soc_codec *codec)
983 {
984 	struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
985 
986 	cancel_delayed_work_sync(&rt286->jack_detect_work);
987 
988 	return 0;
989 }
990 
991 #ifdef CONFIG_PM
rt286_suspend(struct snd_soc_codec * codec)992 static int rt286_suspend(struct snd_soc_codec *codec)
993 {
994 	struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
995 
996 	regcache_cache_only(rt286->regmap, true);
997 	regcache_mark_dirty(rt286->regmap);
998 
999 	return 0;
1000 }
1001 
rt286_resume(struct snd_soc_codec * codec)1002 static int rt286_resume(struct snd_soc_codec *codec)
1003 {
1004 	struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1005 
1006 	regcache_cache_only(rt286->regmap, false);
1007 	rt286_index_sync(codec);
1008 	regcache_sync(rt286->regmap);
1009 
1010 	return 0;
1011 }
1012 #else
1013 #define rt286_suspend NULL
1014 #define rt286_resume NULL
1015 #endif
1016 
1017 #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1018 #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1019 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1020 
1021 static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
1022 	.hw_params = rt286_hw_params,
1023 	.set_fmt = rt286_set_dai_fmt,
1024 	.set_sysclk = rt286_set_dai_sysclk,
1025 	.set_bclk_ratio = rt286_set_bclk_ratio,
1026 };
1027 
1028 static struct snd_soc_dai_driver rt286_dai[] = {
1029 	{
1030 		.name = "rt286-aif1",
1031 		.id = RT286_AIF1,
1032 		.playback = {
1033 			.stream_name = "AIF1 Playback",
1034 			.channels_min = 1,
1035 			.channels_max = 2,
1036 			.rates = RT286_STEREO_RATES,
1037 			.formats = RT286_FORMATS,
1038 		},
1039 		.capture = {
1040 			.stream_name = "AIF1 Capture",
1041 			.channels_min = 1,
1042 			.channels_max = 2,
1043 			.rates = RT286_STEREO_RATES,
1044 			.formats = RT286_FORMATS,
1045 		},
1046 		.ops = &rt286_aif_dai_ops,
1047 		.symmetric_rates = 1,
1048 	},
1049 	{
1050 		.name = "rt286-aif2",
1051 		.id = RT286_AIF2,
1052 		.playback = {
1053 			.stream_name = "AIF2 Playback",
1054 			.channels_min = 1,
1055 			.channels_max = 2,
1056 			.rates = RT286_STEREO_RATES,
1057 			.formats = RT286_FORMATS,
1058 		},
1059 		.capture = {
1060 			.stream_name = "AIF2 Capture",
1061 			.channels_min = 1,
1062 			.channels_max = 2,
1063 			.rates = RT286_STEREO_RATES,
1064 			.formats = RT286_FORMATS,
1065 		},
1066 		.ops = &rt286_aif_dai_ops,
1067 		.symmetric_rates = 1,
1068 	},
1069 
1070 };
1071 
1072 static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
1073 	.probe = rt286_probe,
1074 	.remove = rt286_remove,
1075 	.suspend = rt286_suspend,
1076 	.resume = rt286_resume,
1077 	.set_bias_level = rt286_set_bias_level,
1078 	.idle_bias_off = true,
1079 	.controls = rt286_snd_controls,
1080 	.num_controls = ARRAY_SIZE(rt286_snd_controls),
1081 	.dapm_widgets = rt286_dapm_widgets,
1082 	.num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1083 	.dapm_routes = rt286_dapm_routes,
1084 	.num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1085 };
1086 
1087 static const struct regmap_config rt286_regmap = {
1088 	.reg_bits = 32,
1089 	.val_bits = 32,
1090 	.max_register = 0x02370100,
1091 	.volatile_reg = rt286_volatile_register,
1092 	.readable_reg = rt286_readable_register,
1093 	.reg_write = rl6347a_hw_write,
1094 	.reg_read = rl6347a_hw_read,
1095 	.cache_type = REGCACHE_RBTREE,
1096 	.reg_defaults = rt286_reg,
1097 	.num_reg_defaults = ARRAY_SIZE(rt286_reg),
1098 };
1099 
1100 static const struct i2c_device_id rt286_i2c_id[] = {
1101 	{"rt286", 0},
1102 	{"rt288", 0},
1103 	{}
1104 };
1105 MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1106 
1107 static const struct acpi_device_id rt286_acpi_match[] = {
1108 	{ "INT343A", 0 },
1109 	{},
1110 };
1111 MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1112 
1113 static const struct dmi_system_id force_combo_jack_table[] = {
1114 	{
1115 		.ident = "Intel Wilson Beach",
1116 		.matches = {
1117 			DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1118 		}
1119 	},
1120 	{ }
1121 };
1122 
1123 static const struct dmi_system_id dmi_dell[] = {
1124 	{
1125 		.ident = "Dell",
1126 		.matches = {
1127 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1128 		}
1129 	},
1130 	{ }
1131 };
1132 
rt286_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1133 static int rt286_i2c_probe(struct i2c_client *i2c,
1134 			   const struct i2c_device_id *id)
1135 {
1136 	struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1137 	struct rt286_priv *rt286;
1138 	int i, ret, vendor_id;
1139 
1140 	rt286 = devm_kzalloc(&i2c->dev,	sizeof(*rt286),
1141 				GFP_KERNEL);
1142 	if (NULL == rt286)
1143 		return -ENOMEM;
1144 
1145 	rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1146 	if (IS_ERR(rt286->regmap)) {
1147 		ret = PTR_ERR(rt286->regmap);
1148 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1149 			ret);
1150 		return ret;
1151 	}
1152 
1153 	ret = regmap_read(rt286->regmap,
1154 		RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &vendor_id);
1155 	if (ret != 0) {
1156 		dev_err(&i2c->dev, "I2C error %d\n", ret);
1157 		return ret;
1158 	}
1159 	if (vendor_id != RT286_VENDOR_ID && vendor_id != RT288_VENDOR_ID) {
1160 		dev_err(&i2c->dev,
1161 			"Device with ID register %#x is not rt286\n",
1162 			vendor_id);
1163 		return -ENODEV;
1164 	}
1165 
1166 	rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def,
1167 					  sizeof(rt286_index_def), GFP_KERNEL);
1168 	if (!rt286->index_cache)
1169 		return -ENOMEM;
1170 
1171 	rt286->index_cache_size = INDEX_CACHE_SIZE;
1172 	rt286->i2c = i2c;
1173 	i2c_set_clientdata(i2c, rt286);
1174 
1175 	/* restore codec default */
1176 	for (i = 0; i < INDEX_CACHE_SIZE; i++)
1177 		regmap_write(rt286->regmap, rt286->index_cache[i].reg,
1178 				rt286->index_cache[i].def);
1179 	for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
1180 		regmap_write(rt286->regmap, rt286_reg[i].reg,
1181 				rt286_reg[i].def);
1182 
1183 	if (pdata)
1184 		rt286->pdata = *pdata;
1185 
1186 	if ((vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) ||
1187 		dmi_check_system(force_combo_jack_table))
1188 		rt286->pdata.cbj_en = true;
1189 
1190 	regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1191 
1192 	for (i = 0; i < RT286_POWER_REG_LEN; i++)
1193 		regmap_write(rt286->regmap,
1194 			RT286_SET_POWER(rt286_support_power_controls[i]),
1195 			AC_PWRST_D1);
1196 
1197 	if (!rt286->pdata.cbj_en) {
1198 		regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1199 		regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
1200 		regmap_update_bits(rt286->regmap,
1201 					RT286_CBJ_CTRL1, 0xf000, 0xb000);
1202 	} else {
1203 		regmap_update_bits(rt286->regmap,
1204 					RT286_CBJ_CTRL1, 0xf000, 0x5000);
1205 	}
1206 
1207 	mdelay(10);
1208 
1209 	if (!rt286->pdata.gpio2_en)
1210 		regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1211 	else
1212 		regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1213 
1214 	mdelay(10);
1215 
1216 	regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
1217 	/* Power down LDO, VREF */
1218 	regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1219 	regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
1220 
1221 	/* Set depop parameter */
1222 	regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1223 	regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1224 	regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1225 
1226 	if (vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) {
1227 		regmap_update_bits(rt286->regmap,
1228 			RT286_SET_GPIO_MASK, 0x40, 0x40);
1229 		regmap_update_bits(rt286->regmap,
1230 			RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
1231 		regmap_update_bits(rt286->regmap,
1232 			RT286_SET_GPIO_DATA, 0x40, 0x40);
1233 		regmap_update_bits(rt286->regmap,
1234 			RT286_GPIO_CTRL, 0xc, 0x8);
1235 	}
1236 
1237 	if (rt286->i2c->irq) {
1238 		ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1239 			IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1240 		if (ret != 0) {
1241 			dev_err(&i2c->dev,
1242 				"Failed to reguest IRQ: %d\n", ret);
1243 			return ret;
1244 		}
1245 	}
1246 
1247 	ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
1248 				     rt286_dai, ARRAY_SIZE(rt286_dai));
1249 
1250 	return ret;
1251 }
1252 
rt286_i2c_remove(struct i2c_client * i2c)1253 static int rt286_i2c_remove(struct i2c_client *i2c)
1254 {
1255 	struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1256 
1257 	if (i2c->irq)
1258 		free_irq(i2c->irq, rt286);
1259 	snd_soc_unregister_codec(&i2c->dev);
1260 
1261 	return 0;
1262 }
1263 
1264 
1265 static struct i2c_driver rt286_i2c_driver = {
1266 	.driver = {
1267 		   .name = "rt286",
1268 		   .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1269 		   },
1270 	.probe = rt286_i2c_probe,
1271 	.remove = rt286_i2c_remove,
1272 	.id_table = rt286_i2c_id,
1273 };
1274 
1275 module_i2c_driver(rt286_i2c_driver);
1276 
1277 MODULE_DESCRIPTION("ASoC RT286 driver");
1278 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1279 MODULE_LICENSE("GPL");
1280