1 /*
2 * linux/sound/soc/codecs/tlv320aic32x4.c
3 *
4 * Copyright 2011 Vista Silicon S.L.
5 *
6 * Author: Javier Martin <javier.martin@vista-silicon.com>
7 *
8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 * MA 02110-1301, USA.
24 */
25
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
30 #include <linux/pm.h>
31 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
33 #include <linux/i2c.h>
34 #include <linux/cdev.h>
35 #include <linux/slab.h>
36 #include <linux/clk.h>
37 #include <linux/regulator/consumer.h>
38
39 #include <sound/tlv320aic32x4.h>
40 #include <sound/core.h>
41 #include <sound/pcm.h>
42 #include <sound/pcm_params.h>
43 #include <sound/soc.h>
44 #include <sound/soc-dapm.h>
45 #include <sound/initval.h>
46 #include <sound/tlv.h>
47
48 #include "tlv320aic32x4.h"
49
50 struct aic32x4_rate_divs {
51 u32 mclk;
52 u32 rate;
53 u8 p_val;
54 u8 pll_j;
55 u16 pll_d;
56 u16 dosr;
57 u8 ndac;
58 u8 mdac;
59 u8 aosr;
60 u8 nadc;
61 u8 madc;
62 u8 blck_N;
63 };
64
65 struct aic32x4_priv {
66 struct regmap *regmap;
67 u32 sysclk;
68 u32 power_cfg;
69 u32 micpga_routing;
70 bool swapdacs;
71 int rstn_gpio;
72 struct clk *mclk;
73
74 struct regulator *supply_ldo;
75 struct regulator *supply_iov;
76 struct regulator *supply_dv;
77 struct regulator *supply_av;
78 };
79
80 /* 0dB min, 0.5dB steps */
81 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
82 /* -63.5dB min, 0.5dB steps */
83 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
84 /* -6dB min, 1dB steps */
85 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
86 /* -12dB min, 0.5dB steps */
87 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
88
89 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
90 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
91 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
92 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
93 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
94 tlv_driver_gain),
95 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
96 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
97 tlv_driver_gain),
98 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
99 AIC32X4_HPRGAIN, 6, 0x01, 1),
100 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
101 AIC32X4_LORGAIN, 6, 0x01, 1),
102 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
103 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
104
105 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
106 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
107
108 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
109 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
110 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
111 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
112
113 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
114
115 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
116 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
117 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
118 4, 0x07, 0),
119 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
120 0, 0x03, 0),
121 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
122 6, 0x03, 0),
123 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
124 1, 0x1F, 0),
125 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
126 0, 0x7F, 0),
127 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
128 3, 0x1F, 0),
129 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
130 3, 0x1F, 0),
131 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
132 0, 0x1F, 0),
133 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
134 0, 0x0F, 0),
135 };
136
137 static const struct aic32x4_rate_divs aic32x4_divs[] = {
138 /* 8k rate */
139 {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
140 {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
141 {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
142 /* 11.025k rate */
143 {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
144 {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
145 /* 16k rate */
146 {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
147 {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
148 {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
149 /* 22.05k rate */
150 {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
151 {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
152 {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
153 /* 32k rate */
154 {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
155 {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
156 /* 44.1k rate */
157 {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
158 {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
159 {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
160 /* 48k rate */
161 {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
162 {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
163 {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}
164 };
165
166 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
167 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
168 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
169 };
170
171 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
172 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
173 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
174 };
175
176 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
177 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
178 };
179
180 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
181 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
182 };
183
184 static const struct snd_kcontrol_new left_input_mixer_controls[] = {
185 SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0),
186 SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0),
187 SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0),
188 };
189
190 static const struct snd_kcontrol_new right_input_mixer_controls[] = {
191 SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0),
192 SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0),
193 SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0),
194 };
195
196 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
197 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
198 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
199 &hpl_output_mixer_controls[0],
200 ARRAY_SIZE(hpl_output_mixer_controls)),
201 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
202
203 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
204 &lol_output_mixer_controls[0],
205 ARRAY_SIZE(lol_output_mixer_controls)),
206 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
207
208 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
209 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
210 &hpr_output_mixer_controls[0],
211 ARRAY_SIZE(hpr_output_mixer_controls)),
212 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
213 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
214 &lor_output_mixer_controls[0],
215 ARRAY_SIZE(lor_output_mixer_controls)),
216 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
217 SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
218 &left_input_mixer_controls[0],
219 ARRAY_SIZE(left_input_mixer_controls)),
220 SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
221 &right_input_mixer_controls[0],
222 ARRAY_SIZE(right_input_mixer_controls)),
223 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
224 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
225 SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
226
227 SND_SOC_DAPM_OUTPUT("HPL"),
228 SND_SOC_DAPM_OUTPUT("HPR"),
229 SND_SOC_DAPM_OUTPUT("LOL"),
230 SND_SOC_DAPM_OUTPUT("LOR"),
231 SND_SOC_DAPM_INPUT("IN1_L"),
232 SND_SOC_DAPM_INPUT("IN1_R"),
233 SND_SOC_DAPM_INPUT("IN2_L"),
234 SND_SOC_DAPM_INPUT("IN2_R"),
235 SND_SOC_DAPM_INPUT("IN3_L"),
236 SND_SOC_DAPM_INPUT("IN3_R"),
237 SND_SOC_DAPM_INPUT("CM_L"),
238 SND_SOC_DAPM_INPUT("CM_R"),
239 };
240
241 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
242 /* Left Output */
243 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
244 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
245
246 {"HPL Power", NULL, "HPL Output Mixer"},
247 {"HPL", NULL, "HPL Power"},
248
249 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
250
251 {"LOL Power", NULL, "LOL Output Mixer"},
252 {"LOL", NULL, "LOL Power"},
253
254 /* Right Output */
255 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
256 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
257
258 {"HPR Power", NULL, "HPR Output Mixer"},
259 {"HPR", NULL, "HPR Power"},
260
261 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
262
263 {"LOR Power", NULL, "LOR Output Mixer"},
264 {"LOR", NULL, "LOR Power"},
265
266 /* Left input */
267 {"Left Input Mixer", "IN1_L P Switch", "IN1_L"},
268 {"Left Input Mixer", "IN2_L P Switch", "IN2_L"},
269 {"Left Input Mixer", "IN3_L P Switch", "IN3_L"},
270
271 {"Left ADC", NULL, "Left Input Mixer"},
272
273 /* Right Input */
274 {"Right Input Mixer", "IN1_R P Switch", "IN1_R"},
275 {"Right Input Mixer", "IN2_R P Switch", "IN2_R"},
276 {"Right Input Mixer", "IN3_R P Switch", "IN3_R"},
277
278 {"Right ADC", NULL, "Right Input Mixer"},
279 };
280
281 static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
282 {
283 .selector_reg = 0,
284 .selector_mask = 0xff,
285 .window_start = 0,
286 .window_len = 128,
287 .range_min = 0,
288 .range_max = AIC32X4_RMICPGAVOL,
289 },
290 };
291
292 static const struct regmap_config aic32x4_regmap = {
293 .reg_bits = 8,
294 .val_bits = 8,
295
296 .max_register = AIC32X4_RMICPGAVOL,
297 .ranges = aic32x4_regmap_pages,
298 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
299 };
300
aic32x4_get_divs(int mclk,int rate)301 static inline int aic32x4_get_divs(int mclk, int rate)
302 {
303 int i;
304
305 for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
306 if ((aic32x4_divs[i].rate == rate)
307 && (aic32x4_divs[i].mclk == mclk)) {
308 return i;
309 }
310 }
311 printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
312 return -EINVAL;
313 }
314
aic32x4_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)315 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
316 int clk_id, unsigned int freq, int dir)
317 {
318 struct snd_soc_codec *codec = codec_dai->codec;
319 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
320
321 switch (freq) {
322 case AIC32X4_FREQ_12000000:
323 case AIC32X4_FREQ_24000000:
324 case AIC32X4_FREQ_25000000:
325 aic32x4->sysclk = freq;
326 return 0;
327 }
328 printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
329 return -EINVAL;
330 }
331
aic32x4_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)332 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
333 {
334 struct snd_soc_codec *codec = codec_dai->codec;
335 u8 iface_reg_1;
336 u8 iface_reg_2;
337 u8 iface_reg_3;
338
339 iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
340 iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
341 iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
342 iface_reg_2 = 0;
343 iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
344 iface_reg_3 = iface_reg_3 & ~(1 << 3);
345
346 /* set master/slave audio interface */
347 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
348 case SND_SOC_DAIFMT_CBM_CFM:
349 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
350 break;
351 case SND_SOC_DAIFMT_CBS_CFS:
352 break;
353 default:
354 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
355 return -EINVAL;
356 }
357
358 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
359 case SND_SOC_DAIFMT_I2S:
360 break;
361 case SND_SOC_DAIFMT_DSP_A:
362 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
363 iface_reg_3 |= (1 << 3); /* invert bit clock */
364 iface_reg_2 = 0x01; /* add offset 1 */
365 break;
366 case SND_SOC_DAIFMT_DSP_B:
367 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
368 iface_reg_3 |= (1 << 3); /* invert bit clock */
369 break;
370 case SND_SOC_DAIFMT_RIGHT_J:
371 iface_reg_1 |=
372 (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
373 break;
374 case SND_SOC_DAIFMT_LEFT_J:
375 iface_reg_1 |=
376 (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
377 break;
378 default:
379 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
380 return -EINVAL;
381 }
382
383 snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
384 snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
385 snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
386 return 0;
387 }
388
aic32x4_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)389 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
390 struct snd_pcm_hw_params *params,
391 struct snd_soc_dai *dai)
392 {
393 struct snd_soc_codec *codec = dai->codec;
394 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
395 u8 data;
396 int i;
397
398 i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
399 if (i < 0) {
400 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
401 return i;
402 }
403
404 /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
405 snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
406 snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
407
408 /* We will fix R value to 1 and will make P & J=K.D as varialble */
409 data = snd_soc_read(codec, AIC32X4_PLLPR);
410 data &= ~(7 << 4);
411 snd_soc_write(codec, AIC32X4_PLLPR,
412 (data | (aic32x4_divs[i].p_val << 4) | 0x01));
413
414 snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
415
416 snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
417 snd_soc_write(codec, AIC32X4_PLLDLSB,
418 (aic32x4_divs[i].pll_d & 0xff));
419
420 /* NDAC divider value */
421 data = snd_soc_read(codec, AIC32X4_NDAC);
422 data &= ~(0x7f);
423 snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
424
425 /* MDAC divider value */
426 data = snd_soc_read(codec, AIC32X4_MDAC);
427 data &= ~(0x7f);
428 snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
429
430 /* DOSR MSB & LSB values */
431 snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
432 snd_soc_write(codec, AIC32X4_DOSRLSB,
433 (aic32x4_divs[i].dosr & 0xff));
434
435 /* NADC divider value */
436 data = snd_soc_read(codec, AIC32X4_NADC);
437 data &= ~(0x7f);
438 snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
439
440 /* MADC divider value */
441 data = snd_soc_read(codec, AIC32X4_MADC);
442 data &= ~(0x7f);
443 snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
444
445 /* AOSR value */
446 snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
447
448 /* BCLK N divider */
449 data = snd_soc_read(codec, AIC32X4_BCLKN);
450 data &= ~(0x7f);
451 snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
452
453 data = snd_soc_read(codec, AIC32X4_IFACE1);
454 data = data & ~(3 << 4);
455 switch (params_width(params)) {
456 case 16:
457 break;
458 case 20:
459 data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
460 break;
461 case 24:
462 data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
463 break;
464 case 32:
465 data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
466 break;
467 }
468 snd_soc_write(codec, AIC32X4_IFACE1, data);
469
470 if (params_channels(params) == 1) {
471 data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
472 } else {
473 if (aic32x4->swapdacs)
474 data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
475 else
476 data = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
477 }
478 snd_soc_update_bits(codec, AIC32X4_DACSETUP, AIC32X4_DAC_CHAN_MASK,
479 data);
480
481 return 0;
482 }
483
aic32x4_mute(struct snd_soc_dai * dai,int mute)484 static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
485 {
486 struct snd_soc_codec *codec = dai->codec;
487 u8 dac_reg;
488
489 dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON;
490 if (mute)
491 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON);
492 else
493 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg);
494 return 0;
495 }
496
aic32x4_set_bias_level(struct snd_soc_codec * codec,enum snd_soc_bias_level level)497 static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
498 enum snd_soc_bias_level level)
499 {
500 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
501 int ret;
502
503 switch (level) {
504 case SND_SOC_BIAS_ON:
505 /* Switch on master clock */
506 ret = clk_prepare_enable(aic32x4->mclk);
507 if (ret) {
508 dev_err(codec->dev, "Failed to enable master clock\n");
509 return ret;
510 }
511
512 /* Switch on PLL */
513 snd_soc_update_bits(codec, AIC32X4_PLLPR,
514 AIC32X4_PLLEN, AIC32X4_PLLEN);
515
516 /* Switch on NDAC Divider */
517 snd_soc_update_bits(codec, AIC32X4_NDAC,
518 AIC32X4_NDACEN, AIC32X4_NDACEN);
519
520 /* Switch on MDAC Divider */
521 snd_soc_update_bits(codec, AIC32X4_MDAC,
522 AIC32X4_MDACEN, AIC32X4_MDACEN);
523
524 /* Switch on NADC Divider */
525 snd_soc_update_bits(codec, AIC32X4_NADC,
526 AIC32X4_NADCEN, AIC32X4_NADCEN);
527
528 /* Switch on MADC Divider */
529 snd_soc_update_bits(codec, AIC32X4_MADC,
530 AIC32X4_MADCEN, AIC32X4_MADCEN);
531
532 /* Switch on BCLK_N Divider */
533 snd_soc_update_bits(codec, AIC32X4_BCLKN,
534 AIC32X4_BCLKEN, AIC32X4_BCLKEN);
535 break;
536 case SND_SOC_BIAS_PREPARE:
537 break;
538 case SND_SOC_BIAS_STANDBY:
539 /* Switch off BCLK_N Divider */
540 snd_soc_update_bits(codec, AIC32X4_BCLKN,
541 AIC32X4_BCLKEN, 0);
542
543 /* Switch off MADC Divider */
544 snd_soc_update_bits(codec, AIC32X4_MADC,
545 AIC32X4_MADCEN, 0);
546
547 /* Switch off NADC Divider */
548 snd_soc_update_bits(codec, AIC32X4_NADC,
549 AIC32X4_NADCEN, 0);
550
551 /* Switch off MDAC Divider */
552 snd_soc_update_bits(codec, AIC32X4_MDAC,
553 AIC32X4_MDACEN, 0);
554
555 /* Switch off NDAC Divider */
556 snd_soc_update_bits(codec, AIC32X4_NDAC,
557 AIC32X4_NDACEN, 0);
558
559 /* Switch off PLL */
560 snd_soc_update_bits(codec, AIC32X4_PLLPR,
561 AIC32X4_PLLEN, 0);
562
563 /* Switch off master clock */
564 clk_disable_unprepare(aic32x4->mclk);
565 break;
566 case SND_SOC_BIAS_OFF:
567 break;
568 }
569 return 0;
570 }
571
572 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_48000
573 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
574 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
575
576 static const struct snd_soc_dai_ops aic32x4_ops = {
577 .hw_params = aic32x4_hw_params,
578 .digital_mute = aic32x4_mute,
579 .set_fmt = aic32x4_set_dai_fmt,
580 .set_sysclk = aic32x4_set_dai_sysclk,
581 };
582
583 static struct snd_soc_dai_driver aic32x4_dai = {
584 .name = "tlv320aic32x4-hifi",
585 .playback = {
586 .stream_name = "Playback",
587 .channels_min = 1,
588 .channels_max = 2,
589 .rates = AIC32X4_RATES,
590 .formats = AIC32X4_FORMATS,},
591 .capture = {
592 .stream_name = "Capture",
593 .channels_min = 1,
594 .channels_max = 2,
595 .rates = AIC32X4_RATES,
596 .formats = AIC32X4_FORMATS,},
597 .ops = &aic32x4_ops,
598 .symmetric_rates = 1,
599 };
600
aic32x4_probe(struct snd_soc_codec * codec)601 static int aic32x4_probe(struct snd_soc_codec *codec)
602 {
603 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
604 u32 tmp_reg;
605
606 if (gpio_is_valid(aic32x4->rstn_gpio)) {
607 ndelay(10);
608 gpio_set_value(aic32x4->rstn_gpio, 1);
609 }
610
611 snd_soc_write(codec, AIC32X4_RESET, 0x01);
612
613 /* Power platform configuration */
614 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
615 snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
616 AIC32X4_MICBIAS_2075V);
617 }
618 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
619 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
620
621 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
622 AIC32X4_LDOCTLEN : 0;
623 snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
624
625 tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
626 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
627 tmp_reg |= AIC32X4_LDOIN_18_36;
628 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
629 tmp_reg |= AIC32X4_LDOIN2HP;
630 snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
631
632 /* Mic PGA routing */
633 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
634 snd_soc_write(codec, AIC32X4_LMICPGANIN,
635 AIC32X4_LMICPGANIN_IN2R_10K);
636 else
637 snd_soc_write(codec, AIC32X4_LMICPGANIN,
638 AIC32X4_LMICPGANIN_CM1L_10K);
639 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
640 snd_soc_write(codec, AIC32X4_RMICPGANIN,
641 AIC32X4_RMICPGANIN_IN1L_10K);
642 else
643 snd_soc_write(codec, AIC32X4_RMICPGANIN,
644 AIC32X4_RMICPGANIN_CM1R_10K);
645
646 /*
647 * Workaround: for an unknown reason, the ADC needs to be powered up
648 * and down for the first capture to work properly. It seems related to
649 * a HW BUG or some kind of behavior not documented in the datasheet.
650 */
651 tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP);
652 snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg |
653 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
654 snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg);
655
656 return 0;
657 }
658
659 static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
660 .probe = aic32x4_probe,
661 .set_bias_level = aic32x4_set_bias_level,
662 .suspend_bias_off = true,
663
664 .controls = aic32x4_snd_controls,
665 .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
666 .dapm_widgets = aic32x4_dapm_widgets,
667 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
668 .dapm_routes = aic32x4_dapm_routes,
669 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
670 };
671
aic32x4_parse_dt(struct aic32x4_priv * aic32x4,struct device_node * np)672 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
673 struct device_node *np)
674 {
675 aic32x4->swapdacs = false;
676 aic32x4->micpga_routing = 0;
677 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
678
679 return 0;
680 }
681
aic32x4_disable_regulators(struct aic32x4_priv * aic32x4)682 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
683 {
684 regulator_disable(aic32x4->supply_iov);
685
686 if (!IS_ERR(aic32x4->supply_ldo))
687 regulator_disable(aic32x4->supply_ldo);
688
689 if (!IS_ERR(aic32x4->supply_dv))
690 regulator_disable(aic32x4->supply_dv);
691
692 if (!IS_ERR(aic32x4->supply_av))
693 regulator_disable(aic32x4->supply_av);
694 }
695
aic32x4_setup_regulators(struct device * dev,struct aic32x4_priv * aic32x4)696 static int aic32x4_setup_regulators(struct device *dev,
697 struct aic32x4_priv *aic32x4)
698 {
699 int ret = 0;
700
701 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
702 aic32x4->supply_iov = devm_regulator_get(dev, "iov");
703 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
704 aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
705
706 /* Check if the regulator requirements are fulfilled */
707
708 if (IS_ERR(aic32x4->supply_iov)) {
709 dev_err(dev, "Missing supply 'iov'\n");
710 return PTR_ERR(aic32x4->supply_iov);
711 }
712
713 if (IS_ERR(aic32x4->supply_ldo)) {
714 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
715 return -EPROBE_DEFER;
716
717 if (IS_ERR(aic32x4->supply_dv)) {
718 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
719 return PTR_ERR(aic32x4->supply_dv);
720 }
721 if (IS_ERR(aic32x4->supply_av)) {
722 dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
723 return PTR_ERR(aic32x4->supply_av);
724 }
725 } else {
726 if (IS_ERR(aic32x4->supply_dv) &&
727 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
728 return -EPROBE_DEFER;
729 if (IS_ERR(aic32x4->supply_av) &&
730 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
731 return -EPROBE_DEFER;
732 }
733
734 ret = regulator_enable(aic32x4->supply_iov);
735 if (ret) {
736 dev_err(dev, "Failed to enable regulator iov\n");
737 return ret;
738 }
739
740 if (!IS_ERR(aic32x4->supply_ldo)) {
741 ret = regulator_enable(aic32x4->supply_ldo);
742 if (ret) {
743 dev_err(dev, "Failed to enable regulator ldo\n");
744 goto error_ldo;
745 }
746 }
747
748 if (!IS_ERR(aic32x4->supply_dv)) {
749 ret = regulator_enable(aic32x4->supply_dv);
750 if (ret) {
751 dev_err(dev, "Failed to enable regulator dv\n");
752 goto error_dv;
753 }
754 }
755
756 if (!IS_ERR(aic32x4->supply_av)) {
757 ret = regulator_enable(aic32x4->supply_av);
758 if (ret) {
759 dev_err(dev, "Failed to enable regulator av\n");
760 goto error_av;
761 }
762 }
763
764 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
765 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
766
767 return 0;
768
769 error_av:
770 if (!IS_ERR(aic32x4->supply_dv))
771 regulator_disable(aic32x4->supply_dv);
772
773 error_dv:
774 if (!IS_ERR(aic32x4->supply_ldo))
775 regulator_disable(aic32x4->supply_ldo);
776
777 error_ldo:
778 regulator_disable(aic32x4->supply_iov);
779 return ret;
780 }
781
aic32x4_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)782 static int aic32x4_i2c_probe(struct i2c_client *i2c,
783 const struct i2c_device_id *id)
784 {
785 struct aic32x4_pdata *pdata = i2c->dev.platform_data;
786 struct aic32x4_priv *aic32x4;
787 struct device_node *np = i2c->dev.of_node;
788 int ret;
789
790 aic32x4 = devm_kzalloc(&i2c->dev, sizeof(struct aic32x4_priv),
791 GFP_KERNEL);
792 if (aic32x4 == NULL)
793 return -ENOMEM;
794
795 aic32x4->regmap = devm_regmap_init_i2c(i2c, &aic32x4_regmap);
796 if (IS_ERR(aic32x4->regmap))
797 return PTR_ERR(aic32x4->regmap);
798
799 i2c_set_clientdata(i2c, aic32x4);
800
801 if (pdata) {
802 aic32x4->power_cfg = pdata->power_cfg;
803 aic32x4->swapdacs = pdata->swapdacs;
804 aic32x4->micpga_routing = pdata->micpga_routing;
805 aic32x4->rstn_gpio = pdata->rstn_gpio;
806 } else if (np) {
807 ret = aic32x4_parse_dt(aic32x4, np);
808 if (ret) {
809 dev_err(&i2c->dev, "Failed to parse DT node\n");
810 return ret;
811 }
812 } else {
813 aic32x4->power_cfg = 0;
814 aic32x4->swapdacs = false;
815 aic32x4->micpga_routing = 0;
816 aic32x4->rstn_gpio = -1;
817 }
818
819 aic32x4->mclk = devm_clk_get(&i2c->dev, "mclk");
820 if (IS_ERR(aic32x4->mclk)) {
821 dev_err(&i2c->dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n");
822 return PTR_ERR(aic32x4->mclk);
823 }
824
825 if (gpio_is_valid(aic32x4->rstn_gpio)) {
826 ret = devm_gpio_request_one(&i2c->dev, aic32x4->rstn_gpio,
827 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
828 if (ret != 0)
829 return ret;
830 }
831
832 ret = aic32x4_setup_regulators(&i2c->dev, aic32x4);
833 if (ret) {
834 dev_err(&i2c->dev, "Failed to setup regulators\n");
835 return ret;
836 }
837
838 ret = snd_soc_register_codec(&i2c->dev,
839 &soc_codec_dev_aic32x4, &aic32x4_dai, 1);
840 if (ret) {
841 dev_err(&i2c->dev, "Failed to register codec\n");
842 aic32x4_disable_regulators(aic32x4);
843 return ret;
844 }
845
846 i2c_set_clientdata(i2c, aic32x4);
847
848 return 0;
849 }
850
aic32x4_i2c_remove(struct i2c_client * client)851 static int aic32x4_i2c_remove(struct i2c_client *client)
852 {
853 struct aic32x4_priv *aic32x4 = i2c_get_clientdata(client);
854
855 aic32x4_disable_regulators(aic32x4);
856
857 snd_soc_unregister_codec(&client->dev);
858 return 0;
859 }
860
861 static const struct i2c_device_id aic32x4_i2c_id[] = {
862 { "tlv320aic32x4", 0 },
863 { }
864 };
865 MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id);
866
867 static const struct of_device_id aic32x4_of_id[] = {
868 { .compatible = "ti,tlv320aic32x4", },
869 { /* senitel */ }
870 };
871 MODULE_DEVICE_TABLE(of, aic32x4_of_id);
872
873 static struct i2c_driver aic32x4_i2c_driver = {
874 .driver = {
875 .name = "tlv320aic32x4",
876 .of_match_table = aic32x4_of_id,
877 },
878 .probe = aic32x4_i2c_probe,
879 .remove = aic32x4_i2c_remove,
880 .id_table = aic32x4_i2c_id,
881 };
882
883 module_i2c_driver(aic32x4_i2c_driver);
884
885 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
886 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
887 MODULE_LICENSE("GPL");
888