1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_data/davinci_asp.h>
30 #include <linux/math64.h>
31
32 #include <sound/asoundef.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/initval.h>
37 #include <sound/soc.h>
38 #include <sound/dmaengine_pcm.h>
39 #include <sound/omap-pcm.h>
40
41 #include "edma-pcm.h"
42 #include "davinci-mcasp.h"
43
44 #define MCASP_MAX_AFIFO_DEPTH 64
45
46 #ifdef CONFIG_PM
47 static u32 context_regs[] = {
48 DAVINCI_MCASP_TXFMCTL_REG,
49 DAVINCI_MCASP_RXFMCTL_REG,
50 DAVINCI_MCASP_TXFMT_REG,
51 DAVINCI_MCASP_RXFMT_REG,
52 DAVINCI_MCASP_ACLKXCTL_REG,
53 DAVINCI_MCASP_ACLKRCTL_REG,
54 DAVINCI_MCASP_AHCLKXCTL_REG,
55 DAVINCI_MCASP_AHCLKRCTL_REG,
56 DAVINCI_MCASP_PDIR_REG,
57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
61 };
62
63 struct davinci_mcasp_context {
64 u32 config_regs[ARRAY_SIZE(context_regs)];
65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
67 bool pm_state;
68 };
69 #endif
70
71 struct davinci_mcasp_ruledata {
72 struct davinci_mcasp *mcasp;
73 int serializers;
74 };
75
76 struct davinci_mcasp {
77 struct snd_dmaengine_dai_dma_data dma_data[2];
78 void __iomem *base;
79 u32 fifo_base;
80 struct device *dev;
81 struct snd_pcm_substream *substreams[2];
82
83 /* McASP specific data */
84 int tdm_slots;
85 u32 tdm_mask[2];
86 int slot_width;
87 u8 op_mode;
88 u8 num_serializer;
89 u8 *serial_dir;
90 u8 version;
91 u8 bclk_div;
92 int streams;
93 u32 irq_request[2];
94 int dma_request[2];
95
96 int sysclk_freq;
97 bool bclk_master;
98
99 /* McASP FIFO related */
100 u8 txnumevt;
101 u8 rxnumevt;
102
103 bool dat_port;
104
105 /* Used for comstraint setting on the second stream */
106 u32 channels;
107
108 #ifdef CONFIG_PM_SLEEP
109 struct davinci_mcasp_context context;
110 #endif
111
112 struct davinci_mcasp_ruledata ruledata[2];
113 struct snd_pcm_hw_constraint_list chconstr[2];
114 };
115
mcasp_set_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)116 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
117 u32 val)
118 {
119 void __iomem *reg = mcasp->base + offset;
120 __raw_writel(__raw_readl(reg) | val, reg);
121 }
122
mcasp_clr_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)123 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
124 u32 val)
125 {
126 void __iomem *reg = mcasp->base + offset;
127 __raw_writel((__raw_readl(reg) & ~(val)), reg);
128 }
129
mcasp_mod_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val,u32 mask)130 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
131 u32 val, u32 mask)
132 {
133 void __iomem *reg = mcasp->base + offset;
134 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
135 }
136
mcasp_set_reg(struct davinci_mcasp * mcasp,u32 offset,u32 val)137 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
138 u32 val)
139 {
140 __raw_writel(val, mcasp->base + offset);
141 }
142
mcasp_get_reg(struct davinci_mcasp * mcasp,u32 offset)143 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
144 {
145 return (u32)__raw_readl(mcasp->base + offset);
146 }
147
mcasp_set_ctl_reg(struct davinci_mcasp * mcasp,u32 ctl_reg,u32 val)148 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
149 {
150 int i = 0;
151
152 mcasp_set_bits(mcasp, ctl_reg, val);
153
154 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
155 /* loop count is to avoid the lock-up */
156 for (i = 0; i < 1000; i++) {
157 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
158 break;
159 }
160
161 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
162 printk(KERN_ERR "GBLCTL write error\n");
163 }
164
mcasp_is_synchronous(struct davinci_mcasp * mcasp)165 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
166 {
167 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
168 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
169
170 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
171 }
172
mcasp_start_rx(struct davinci_mcasp * mcasp)173 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
174 {
175 if (mcasp->rxnumevt) { /* enable FIFO */
176 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
177
178 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
179 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
180 }
181
182 /* Start clocks */
183 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
184 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
185 /*
186 * When ASYNC == 0 the transmit and receive sections operate
187 * synchronously from the transmit clock and frame sync. We need to make
188 * sure that the TX signlas are enabled when starting reception.
189 */
190 if (mcasp_is_synchronous(mcasp)) {
191 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
192 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
193 }
194
195 /* Activate serializer(s) */
196 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
197 /* Release RX state machine */
198 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
199 /* Release Frame Sync generator */
200 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
201 if (mcasp_is_synchronous(mcasp))
202 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
203
204 /* enable receive IRQs */
205 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
206 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
207 }
208
mcasp_start_tx(struct davinci_mcasp * mcasp)209 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
210 {
211 u32 cnt;
212
213 if (mcasp->txnumevt) { /* enable FIFO */
214 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
215
216 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
217 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
218 }
219
220 /* Start clocks */
221 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
223 /* Activate serializer(s) */
224 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
225
226 /* wait for XDATA to be cleared */
227 cnt = 0;
228 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
229 (cnt < 100000))
230 cnt++;
231
232 /* Release TX state machine */
233 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
234 /* Release Frame Sync generator */
235 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
236
237 /* enable transmit IRQs */
238 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
239 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
240 }
241
davinci_mcasp_start(struct davinci_mcasp * mcasp,int stream)242 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
243 {
244 mcasp->streams++;
245
246 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
247 mcasp_start_tx(mcasp);
248 else
249 mcasp_start_rx(mcasp);
250 }
251
mcasp_stop_rx(struct davinci_mcasp * mcasp)252 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
253 {
254 /* disable IRQ sources */
255 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
256 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
257
258 /*
259 * In synchronous mode stop the TX clocks if no other stream is
260 * running
261 */
262 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
263 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
264
265 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
266 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
267
268 if (mcasp->rxnumevt) { /* disable FIFO */
269 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
270
271 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
272 }
273 }
274
mcasp_stop_tx(struct davinci_mcasp * mcasp)275 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
276 {
277 u32 val = 0;
278
279 /* disable IRQ sources */
280 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
281 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
282
283 /*
284 * In synchronous mode keep TX clocks running if the capture stream is
285 * still running.
286 */
287 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
288 val = TXHCLKRST | TXCLKRST | TXFSRST;
289
290 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
291 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
292
293 if (mcasp->txnumevt) { /* disable FIFO */
294 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
295
296 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
297 }
298 }
299
davinci_mcasp_stop(struct davinci_mcasp * mcasp,int stream)300 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
301 {
302 mcasp->streams--;
303
304 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
305 mcasp_stop_tx(mcasp);
306 else
307 mcasp_stop_rx(mcasp);
308 }
309
davinci_mcasp_tx_irq_handler(int irq,void * data)310 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
311 {
312 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
313 struct snd_pcm_substream *substream;
314 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
315 u32 handled_mask = 0;
316 u32 stat;
317
318 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
319 if (stat & XUNDRN & irq_mask) {
320 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
321 handled_mask |= XUNDRN;
322
323 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
324 if (substream) {
325 snd_pcm_stream_lock_irq(substream);
326 if (snd_pcm_running(substream))
327 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
328 snd_pcm_stream_unlock_irq(substream);
329 }
330 }
331
332 if (!handled_mask)
333 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
334 stat);
335
336 if (stat & XRERR)
337 handled_mask |= XRERR;
338
339 /* Ack the handled event only */
340 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
341
342 return IRQ_RETVAL(handled_mask);
343 }
344
davinci_mcasp_rx_irq_handler(int irq,void * data)345 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
346 {
347 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
348 struct snd_pcm_substream *substream;
349 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
350 u32 handled_mask = 0;
351 u32 stat;
352
353 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
354 if (stat & ROVRN & irq_mask) {
355 dev_warn(mcasp->dev, "Receive buffer overflow\n");
356 handled_mask |= ROVRN;
357
358 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
359 if (substream) {
360 snd_pcm_stream_lock_irq(substream);
361 if (snd_pcm_running(substream))
362 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
363 snd_pcm_stream_unlock_irq(substream);
364 }
365 }
366
367 if (!handled_mask)
368 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
369 stat);
370
371 if (stat & XRERR)
372 handled_mask |= XRERR;
373
374 /* Ack the handled event only */
375 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
376
377 return IRQ_RETVAL(handled_mask);
378 }
379
davinci_mcasp_common_irq_handler(int irq,void * data)380 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
381 {
382 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
383 irqreturn_t ret = IRQ_NONE;
384
385 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
386 ret = davinci_mcasp_tx_irq_handler(irq, data);
387
388 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
389 ret |= davinci_mcasp_rx_irq_handler(irq, data);
390
391 return ret;
392 }
393
davinci_mcasp_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)394 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
395 unsigned int fmt)
396 {
397 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
398 int ret = 0;
399 u32 data_delay;
400 bool fs_pol_rising;
401 bool inv_fs = false;
402
403 pm_runtime_get_sync(mcasp->dev);
404 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
405 case SND_SOC_DAIFMT_DSP_A:
406 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
407 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
408 /* 1st data bit occur one ACLK cycle after the frame sync */
409 data_delay = 1;
410 break;
411 case SND_SOC_DAIFMT_DSP_B:
412 case SND_SOC_DAIFMT_AC97:
413 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
414 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
415 /* No delay after FS */
416 data_delay = 0;
417 break;
418 case SND_SOC_DAIFMT_I2S:
419 /* configure a full-word SYNC pulse (LRCLK) */
420 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
421 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
422 /* 1st data bit occur one ACLK cycle after the frame sync */
423 data_delay = 1;
424 /* FS need to be inverted */
425 inv_fs = true;
426 break;
427 case SND_SOC_DAIFMT_LEFT_J:
428 /* configure a full-word SYNC pulse (LRCLK) */
429 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
430 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
431 /* No delay after FS */
432 data_delay = 0;
433 break;
434 default:
435 ret = -EINVAL;
436 goto out;
437 }
438
439 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
440 FSXDLY(3));
441 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
442 FSRDLY(3));
443
444 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
445 case SND_SOC_DAIFMT_CBS_CFS:
446 /* codec is clock and frame slave */
447 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
448 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
449
450 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
451 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
452
453 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
454 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
455 mcasp->bclk_master = 1;
456 break;
457 case SND_SOC_DAIFMT_CBS_CFM:
458 /* codec is clock slave and frame master */
459 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
460 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
461
462 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
463 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
464
465 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
466 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
467 mcasp->bclk_master = 1;
468 break;
469 case SND_SOC_DAIFMT_CBM_CFS:
470 /* codec is clock master and frame slave */
471 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
472 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
473
474 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
475 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
476
477 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
478 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
479 mcasp->bclk_master = 0;
480 break;
481 case SND_SOC_DAIFMT_CBM_CFM:
482 /* codec is clock and frame master */
483 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
484 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
485
486 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
487 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
488
489 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
490 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
491 mcasp->bclk_master = 0;
492 break;
493 default:
494 ret = -EINVAL;
495 goto out;
496 }
497
498 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
499 case SND_SOC_DAIFMT_IB_NF:
500 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
501 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
502 fs_pol_rising = true;
503 break;
504 case SND_SOC_DAIFMT_NB_IF:
505 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
506 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
507 fs_pol_rising = false;
508 break;
509 case SND_SOC_DAIFMT_IB_IF:
510 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
511 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
512 fs_pol_rising = false;
513 break;
514 case SND_SOC_DAIFMT_NB_NF:
515 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
516 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
517 fs_pol_rising = true;
518 break;
519 default:
520 ret = -EINVAL;
521 goto out;
522 }
523
524 if (inv_fs)
525 fs_pol_rising = !fs_pol_rising;
526
527 if (fs_pol_rising) {
528 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
529 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
530 } else {
531 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
532 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
533 }
534 out:
535 pm_runtime_put(mcasp->dev);
536 return ret;
537 }
538
__davinci_mcasp_set_clkdiv(struct snd_soc_dai * dai,int div_id,int div,bool explicit)539 static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
540 int div, bool explicit)
541 {
542 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
543
544 pm_runtime_get_sync(mcasp->dev);
545 switch (div_id) {
546 case 0: /* MCLK divider */
547 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
548 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
549 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
550 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
551 break;
552
553 case 1: /* BCLK divider */
554 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
555 ACLKXDIV(div - 1), ACLKXDIV_MASK);
556 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
557 ACLKRDIV(div - 1), ACLKRDIV_MASK);
558 if (explicit)
559 mcasp->bclk_div = div;
560 break;
561
562 case 2: /*
563 * BCLK/LRCLK ratio descries how many bit-clock cycles
564 * fit into one frame. The clock ratio is given for a
565 * full period of data (for I2S format both left and
566 * right channels), so it has to be divided by number
567 * of tdm-slots (for I2S - divided by 2).
568 * Instead of storing this ratio, we calculate a new
569 * tdm_slot width by dividing the the ratio by the
570 * number of configured tdm slots.
571 */
572 mcasp->slot_width = div / mcasp->tdm_slots;
573 if (div % mcasp->tdm_slots)
574 dev_warn(mcasp->dev,
575 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
576 __func__, div, mcasp->tdm_slots);
577 break;
578
579 default:
580 return -EINVAL;
581 }
582
583 pm_runtime_put(mcasp->dev);
584 return 0;
585 }
586
davinci_mcasp_set_clkdiv(struct snd_soc_dai * dai,int div_id,int div)587 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
588 int div)
589 {
590 return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
591 }
592
davinci_mcasp_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)593 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
594 unsigned int freq, int dir)
595 {
596 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
597
598 pm_runtime_get_sync(mcasp->dev);
599 if (dir == SND_SOC_CLOCK_OUT) {
600 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
601 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
602 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
603 } else {
604 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
605 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
606 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
607 }
608
609 mcasp->sysclk_freq = freq;
610
611 pm_runtime_put(mcasp->dev);
612 return 0;
613 }
614
615 /* All serializers must have equal number of channels */
davinci_mcasp_ch_constraint(struct davinci_mcasp * mcasp,int stream,int serializers)616 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
617 int serializers)
618 {
619 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
620 unsigned int *list = (unsigned int *) cl->list;
621 int slots = mcasp->tdm_slots;
622 int i, count = 0;
623
624 if (mcasp->tdm_mask[stream])
625 slots = hweight32(mcasp->tdm_mask[stream]);
626
627 for (i = 2; i <= slots; i++)
628 list[count++] = i;
629
630 for (i = 2; i <= serializers; i++)
631 list[count++] = i*slots;
632
633 cl->count = count;
634
635 return 0;
636 }
637
davinci_mcasp_set_ch_constraints(struct davinci_mcasp * mcasp)638 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
639 {
640 int rx_serializers = 0, tx_serializers = 0, ret, i;
641
642 for (i = 0; i < mcasp->num_serializer; i++)
643 if (mcasp->serial_dir[i] == TX_MODE)
644 tx_serializers++;
645 else if (mcasp->serial_dir[i] == RX_MODE)
646 rx_serializers++;
647
648 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
649 tx_serializers);
650 if (ret)
651 return ret;
652
653 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
654 rx_serializers);
655
656 return ret;
657 }
658
659
davinci_mcasp_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)660 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
661 unsigned int tx_mask,
662 unsigned int rx_mask,
663 int slots, int slot_width)
664 {
665 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
666
667 dev_dbg(mcasp->dev,
668 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
669 __func__, tx_mask, rx_mask, slots, slot_width);
670
671 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
672 dev_err(mcasp->dev,
673 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
674 tx_mask, rx_mask, slots);
675 return -EINVAL;
676 }
677
678 if (slot_width &&
679 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
680 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
681 __func__, slot_width);
682 return -EINVAL;
683 }
684
685 mcasp->tdm_slots = slots;
686 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
687 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
688 mcasp->slot_width = slot_width;
689
690 return davinci_mcasp_set_ch_constraints(mcasp);
691 }
692
davinci_config_channel_size(struct davinci_mcasp * mcasp,int sample_width)693 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
694 int sample_width)
695 {
696 u32 fmt;
697 u32 tx_rotate = (sample_width / 4) & 0x7;
698 u32 mask = (1ULL << sample_width) - 1;
699 u32 slot_width = sample_width;
700
701 /*
702 * For captured data we should not rotate, inversion and masking is
703 * enoguh to get the data to the right position:
704 * Format data from bus after reverse (XRBUF)
705 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
706 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
707 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
708 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
709 */
710 u32 rx_rotate = 0;
711
712 /*
713 * Setting the tdm slot width either with set_clkdiv() or
714 * set_tdm_slot() allows us to for example send 32 bits per
715 * channel to the codec, while only 16 of them carry audio
716 * payload.
717 */
718 if (mcasp->slot_width) {
719 /*
720 * When we have more bclk then it is needed for the
721 * data, we need to use the rotation to move the
722 * received samples to have correct alignment.
723 */
724 slot_width = mcasp->slot_width;
725 rx_rotate = (slot_width - sample_width) / 4;
726 }
727
728 /* mapping of the XSSZ bit-field as described in the datasheet */
729 fmt = (slot_width >> 1) - 1;
730
731 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
732 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
733 RXSSZ(0x0F));
734 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
735 TXSSZ(0x0F));
736 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
737 TXROT(7));
738 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
739 RXROT(7));
740 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
741 }
742
743 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
744
745 return 0;
746 }
747
mcasp_common_hw_param(struct davinci_mcasp * mcasp,int stream,int period_words,int channels)748 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
749 int period_words, int channels)
750 {
751 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
752 int i;
753 u8 tx_ser = 0;
754 u8 rx_ser = 0;
755 u8 slots = mcasp->tdm_slots;
756 u8 max_active_serializers = (channels + slots - 1) / slots;
757 int active_serializers, numevt;
758 u32 reg;
759 /* Default configuration */
760 if (mcasp->version < MCASP_VERSION_3)
761 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
762
763 /* All PINS as McASP */
764 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
765
766 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
767 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
768 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
769 } else {
770 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
771 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
772 }
773
774 for (i = 0; i < mcasp->num_serializer; i++) {
775 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
776 mcasp->serial_dir[i]);
777 if (mcasp->serial_dir[i] == TX_MODE &&
778 tx_ser < max_active_serializers) {
779 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
780 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
781 DISMOD_LOW, DISMOD_MASK);
782 tx_ser++;
783 } else if (mcasp->serial_dir[i] == RX_MODE &&
784 rx_ser < max_active_serializers) {
785 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
786 rx_ser++;
787 } else {
788 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
789 SRMOD_INACTIVE, SRMOD_MASK);
790 }
791 }
792
793 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
794 active_serializers = tx_ser;
795 numevt = mcasp->txnumevt;
796 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
797 } else {
798 active_serializers = rx_ser;
799 numevt = mcasp->rxnumevt;
800 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
801 }
802
803 if (active_serializers < max_active_serializers) {
804 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
805 "enabled in mcasp (%d)\n", channels,
806 active_serializers * slots);
807 return -EINVAL;
808 }
809
810 /* AFIFO is not in use */
811 if (!numevt) {
812 /* Configure the burst size for platform drivers */
813 if (active_serializers > 1) {
814 /*
815 * If more than one serializers are in use we have one
816 * DMA request to provide data for all serializers.
817 * For example if three serializers are enabled the DMA
818 * need to transfer three words per DMA request.
819 */
820 dma_data->maxburst = active_serializers;
821 } else {
822 dma_data->maxburst = 0;
823 }
824 return 0;
825 }
826
827 if (period_words % active_serializers) {
828 dev_err(mcasp->dev, "Invalid combination of period words and "
829 "active serializers: %d, %d\n", period_words,
830 active_serializers);
831 return -EINVAL;
832 }
833
834 /*
835 * Calculate the optimal AFIFO depth for platform side:
836 * The number of words for numevt need to be in steps of active
837 * serializers.
838 */
839 numevt = (numevt / active_serializers) * active_serializers;
840
841 while (period_words % numevt && numevt > 0)
842 numevt -= active_serializers;
843 if (numevt <= 0)
844 numevt = active_serializers;
845
846 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
847 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
848
849 /* Configure the burst size for platform drivers */
850 if (numevt == 1)
851 numevt = 0;
852 dma_data->maxburst = numevt;
853
854 return 0;
855 }
856
mcasp_i2s_hw_param(struct davinci_mcasp * mcasp,int stream,int channels)857 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
858 int channels)
859 {
860 int i, active_slots;
861 int total_slots;
862 int active_serializers;
863 u32 mask = 0;
864 u32 busel = 0;
865
866 total_slots = mcasp->tdm_slots;
867
868 /*
869 * If more than one serializer is needed, then use them with
870 * all the specified tdm_slots. Otherwise, one serializer can
871 * cope with the transaction using just as many slots as there
872 * are channels in the stream.
873 */
874 if (mcasp->tdm_mask[stream]) {
875 active_slots = hweight32(mcasp->tdm_mask[stream]);
876 active_serializers = (channels + active_slots - 1) /
877 active_slots;
878 if (active_serializers == 1)
879 active_slots = channels;
880 for (i = 0; i < total_slots; i++) {
881 if ((1 << i) & mcasp->tdm_mask[stream]) {
882 mask |= (1 << i);
883 if (--active_slots <= 0)
884 break;
885 }
886 }
887 } else {
888 active_serializers = (channels + total_slots - 1) / total_slots;
889 if (active_serializers == 1)
890 active_slots = channels;
891 else
892 active_slots = total_slots;
893
894 for (i = 0; i < active_slots; i++)
895 mask |= (1 << i);
896 }
897 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
898
899 if (!mcasp->dat_port)
900 busel = TXSEL;
901
902 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
903 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
904 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
905 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
906 FSXMOD(total_slots), FSXMOD(0x1FF));
907 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
908 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
909 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
910 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
911 FSRMOD(total_slots), FSRMOD(0x1FF));
912 /*
913 * If McASP is set to be TX/RX synchronous and the playback is
914 * not running already we need to configure the TX slots in
915 * order to have correct FSX on the bus
916 */
917 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
918 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
919 FSXMOD(total_slots), FSXMOD(0x1FF));
920 }
921
922 return 0;
923 }
924
925 /* S/PDIF */
mcasp_dit_hw_param(struct davinci_mcasp * mcasp,unsigned int rate)926 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
927 unsigned int rate)
928 {
929 u32 cs_value = 0;
930 u8 *cs_bytes = (u8*) &cs_value;
931
932 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
933 and LSB first */
934 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
935
936 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
937 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
938
939 /* Set the TX tdm : for all the slots */
940 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
941
942 /* Set the TX clock controls : div = 1 and internal */
943 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
944
945 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
946
947 /* Only 44100 and 48000 are valid, both have the same setting */
948 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
949
950 /* Enable the DIT */
951 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
952
953 /* Set S/PDIF channel status bits */
954 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
955 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
956
957 switch (rate) {
958 case 22050:
959 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
960 break;
961 case 24000:
962 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
963 break;
964 case 32000:
965 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
966 break;
967 case 44100:
968 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
969 break;
970 case 48000:
971 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
972 break;
973 case 88200:
974 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
975 break;
976 case 96000:
977 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
978 break;
979 case 176400:
980 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
981 break;
982 case 192000:
983 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
984 break;
985 default:
986 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
987 return -EINVAL;
988 }
989
990 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
991 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
992
993 return 0;
994 }
995
davinci_mcasp_calc_clk_div(struct davinci_mcasp * mcasp,unsigned int bclk_freq,int * error_ppm)996 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
997 unsigned int bclk_freq,
998 int *error_ppm)
999 {
1000 int div = mcasp->sysclk_freq / bclk_freq;
1001 int rem = mcasp->sysclk_freq % bclk_freq;
1002
1003 if (rem != 0) {
1004 if (div == 0 ||
1005 ((mcasp->sysclk_freq / div) - bclk_freq) >
1006 (bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
1007 div++;
1008 rem = rem - bclk_freq;
1009 }
1010 }
1011 if (error_ppm)
1012 *error_ppm =
1013 (div*1000000 + (int)div64_long(1000000LL*rem,
1014 (int)bclk_freq))
1015 /div - 1000000;
1016
1017 return div;
1018 }
1019
davinci_mcasp_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)1020 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1021 struct snd_pcm_hw_params *params,
1022 struct snd_soc_dai *cpu_dai)
1023 {
1024 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1025 int word_length;
1026 int channels = params_channels(params);
1027 int period_size = params_period_size(params);
1028 int ret;
1029
1030 /*
1031 * If mcasp is BCLK master, and a BCLK divider was not provided by
1032 * the machine driver, we need to calculate the ratio.
1033 */
1034 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1035 int slots = mcasp->tdm_slots;
1036 int rate = params_rate(params);
1037 int sbits = params_width(params);
1038 int ppm, div;
1039
1040 if (mcasp->slot_width)
1041 sbits = mcasp->slot_width;
1042
1043 div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots,
1044 &ppm);
1045 if (ppm)
1046 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1047 ppm);
1048
1049 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
1050 }
1051
1052 ret = mcasp_common_hw_param(mcasp, substream->stream,
1053 period_size * channels, channels);
1054 if (ret)
1055 return ret;
1056
1057 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1058 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1059 else
1060 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1061 channels);
1062
1063 if (ret)
1064 return ret;
1065
1066 switch (params_format(params)) {
1067 case SNDRV_PCM_FORMAT_U8:
1068 case SNDRV_PCM_FORMAT_S8:
1069 word_length = 8;
1070 break;
1071
1072 case SNDRV_PCM_FORMAT_U16_LE:
1073 case SNDRV_PCM_FORMAT_S16_LE:
1074 word_length = 16;
1075 break;
1076
1077 case SNDRV_PCM_FORMAT_U24_3LE:
1078 case SNDRV_PCM_FORMAT_S24_3LE:
1079 word_length = 24;
1080 break;
1081
1082 case SNDRV_PCM_FORMAT_U24_LE:
1083 case SNDRV_PCM_FORMAT_S24_LE:
1084 word_length = 24;
1085 break;
1086
1087 case SNDRV_PCM_FORMAT_U32_LE:
1088 case SNDRV_PCM_FORMAT_S32_LE:
1089 word_length = 32;
1090 break;
1091
1092 default:
1093 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1094 return -EINVAL;
1095 }
1096
1097 davinci_config_channel_size(mcasp, word_length);
1098
1099 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1100 mcasp->channels = channels;
1101
1102 return 0;
1103 }
1104
davinci_mcasp_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)1105 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1106 int cmd, struct snd_soc_dai *cpu_dai)
1107 {
1108 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1109 int ret = 0;
1110
1111 switch (cmd) {
1112 case SNDRV_PCM_TRIGGER_RESUME:
1113 case SNDRV_PCM_TRIGGER_START:
1114 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1115 davinci_mcasp_start(mcasp, substream->stream);
1116 break;
1117 case SNDRV_PCM_TRIGGER_SUSPEND:
1118 case SNDRV_PCM_TRIGGER_STOP:
1119 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1120 davinci_mcasp_stop(mcasp, substream->stream);
1121 break;
1122
1123 default:
1124 ret = -EINVAL;
1125 }
1126
1127 return ret;
1128 }
1129
davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1130 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1131 struct snd_pcm_hw_rule *rule)
1132 {
1133 struct davinci_mcasp_ruledata *rd = rule->private;
1134 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1135 struct snd_mask nfmt;
1136 int i, slot_width;
1137
1138 snd_mask_none(&nfmt);
1139 slot_width = rd->mcasp->slot_width;
1140
1141 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1142 if (snd_mask_test(fmt, i)) {
1143 if (snd_pcm_format_width(i) <= slot_width) {
1144 snd_mask_set(&nfmt, i);
1145 }
1146 }
1147 }
1148
1149 return snd_mask_refine(fmt, &nfmt);
1150 }
1151
1152 static const unsigned int davinci_mcasp_dai_rates[] = {
1153 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1154 88200, 96000, 176400, 192000,
1155 };
1156
1157 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1158
davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1159 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1160 struct snd_pcm_hw_rule *rule)
1161 {
1162 struct davinci_mcasp_ruledata *rd = rule->private;
1163 struct snd_interval *ri =
1164 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1165 int sbits = params_width(params);
1166 int slots = rd->mcasp->tdm_slots;
1167 struct snd_interval range;
1168 int i;
1169
1170 if (rd->mcasp->slot_width)
1171 sbits = rd->mcasp->slot_width;
1172
1173 snd_interval_any(&range);
1174 range.empty = 1;
1175
1176 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1177 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1178 uint bclk_freq = sbits*slots*
1179 davinci_mcasp_dai_rates[i];
1180 int ppm;
1181
1182 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1183 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1184 if (range.empty) {
1185 range.min = davinci_mcasp_dai_rates[i];
1186 range.empty = 0;
1187 }
1188 range.max = davinci_mcasp_dai_rates[i];
1189 }
1190 }
1191 }
1192
1193 dev_dbg(rd->mcasp->dev,
1194 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1195 ri->min, ri->max, range.min, range.max, sbits, slots);
1196
1197 return snd_interval_refine(hw_param_interval(params, rule->var),
1198 &range);
1199 }
1200
davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1201 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1202 struct snd_pcm_hw_rule *rule)
1203 {
1204 struct davinci_mcasp_ruledata *rd = rule->private;
1205 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1206 struct snd_mask nfmt;
1207 int rate = params_rate(params);
1208 int slots = rd->mcasp->tdm_slots;
1209 int i, count = 0;
1210
1211 snd_mask_none(&nfmt);
1212
1213 for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
1214 if (snd_mask_test(fmt, i)) {
1215 uint sbits = snd_pcm_format_width(i);
1216 int ppm;
1217
1218 if (rd->mcasp->slot_width)
1219 sbits = rd->mcasp->slot_width;
1220
1221 davinci_mcasp_calc_clk_div(rd->mcasp, sbits*slots*rate,
1222 &ppm);
1223 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1224 snd_mask_set(&nfmt, i);
1225 count++;
1226 }
1227 }
1228 }
1229 dev_dbg(rd->mcasp->dev,
1230 "%d possible sample format for %d Hz and %d tdm slots\n",
1231 count, rate, slots);
1232
1233 return snd_mask_refine(fmt, &nfmt);
1234 }
1235
davinci_mcasp_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1236 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1237 struct snd_soc_dai *cpu_dai)
1238 {
1239 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1240 struct davinci_mcasp_ruledata *ruledata =
1241 &mcasp->ruledata[substream->stream];
1242 u32 max_channels = 0;
1243 int i, dir, ret;
1244 int tdm_slots = mcasp->tdm_slots;
1245
1246 if (mcasp->tdm_mask[substream->stream])
1247 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1248
1249 mcasp->substreams[substream->stream] = substream;
1250
1251 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1252 return 0;
1253
1254 /*
1255 * Limit the maximum allowed channels for the first stream:
1256 * number of serializers for the direction * tdm slots per serializer
1257 */
1258 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1259 dir = TX_MODE;
1260 else
1261 dir = RX_MODE;
1262
1263 for (i = 0; i < mcasp->num_serializer; i++) {
1264 if (mcasp->serial_dir[i] == dir)
1265 max_channels++;
1266 }
1267 ruledata->serializers = max_channels;
1268 ruledata->mcasp = mcasp;
1269 max_channels *= tdm_slots;
1270 /*
1271 * If the already active stream has less channels than the calculated
1272 * limnit based on the seirializers * tdm_slots, we need to use that as
1273 * a constraint for the second stream.
1274 * Otherwise (first stream or less allowed channels) we use the
1275 * calculated constraint.
1276 */
1277 if (mcasp->channels && mcasp->channels < max_channels)
1278 max_channels = mcasp->channels;
1279 /*
1280 * But we can always allow channels upto the amount of
1281 * the available tdm_slots.
1282 */
1283 if (max_channels < tdm_slots)
1284 max_channels = tdm_slots;
1285
1286 snd_pcm_hw_constraint_minmax(substream->runtime,
1287 SNDRV_PCM_HW_PARAM_CHANNELS,
1288 2, max_channels);
1289
1290 snd_pcm_hw_constraint_list(substream->runtime,
1291 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1292 &mcasp->chconstr[substream->stream]);
1293
1294 if (mcasp->slot_width) {
1295 /* Only allow formats require <= slot_width bits on the bus */
1296 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1297 SNDRV_PCM_HW_PARAM_FORMAT,
1298 davinci_mcasp_hw_rule_slot_width,
1299 ruledata,
1300 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1301 if (ret)
1302 return ret;
1303 }
1304
1305 /*
1306 * If we rely on implicit BCLK divider setting we should
1307 * set constraints based on what we can provide.
1308 */
1309 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1310 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1311 SNDRV_PCM_HW_PARAM_RATE,
1312 davinci_mcasp_hw_rule_rate,
1313 ruledata,
1314 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1315 if (ret)
1316 return ret;
1317 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1318 SNDRV_PCM_HW_PARAM_FORMAT,
1319 davinci_mcasp_hw_rule_format,
1320 ruledata,
1321 SNDRV_PCM_HW_PARAM_RATE, -1);
1322 if (ret)
1323 return ret;
1324 }
1325
1326 return 0;
1327 }
1328
davinci_mcasp_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1329 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1330 struct snd_soc_dai *cpu_dai)
1331 {
1332 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1333
1334 mcasp->substreams[substream->stream] = NULL;
1335
1336 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1337 return;
1338
1339 if (!cpu_dai->active)
1340 mcasp->channels = 0;
1341 }
1342
1343 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1344 .startup = davinci_mcasp_startup,
1345 .shutdown = davinci_mcasp_shutdown,
1346 .trigger = davinci_mcasp_trigger,
1347 .hw_params = davinci_mcasp_hw_params,
1348 .set_fmt = davinci_mcasp_set_dai_fmt,
1349 .set_clkdiv = davinci_mcasp_set_clkdiv,
1350 .set_sysclk = davinci_mcasp_set_sysclk,
1351 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1352 };
1353
davinci_mcasp_dai_probe(struct snd_soc_dai * dai)1354 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1355 {
1356 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1357
1358 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1359 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1360
1361 return 0;
1362 }
1363
1364 #ifdef CONFIG_PM_SLEEP
davinci_mcasp_suspend(struct snd_soc_dai * dai)1365 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1366 {
1367 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1368 struct davinci_mcasp_context *context = &mcasp->context;
1369 u32 reg;
1370 int i;
1371
1372 context->pm_state = pm_runtime_active(mcasp->dev);
1373 if (!context->pm_state)
1374 pm_runtime_get_sync(mcasp->dev);
1375
1376 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1377 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1378
1379 if (mcasp->txnumevt) {
1380 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1381 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1382 }
1383 if (mcasp->rxnumevt) {
1384 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1385 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1386 }
1387
1388 for (i = 0; i < mcasp->num_serializer; i++)
1389 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1390 DAVINCI_MCASP_XRSRCTL_REG(i));
1391
1392 pm_runtime_put_sync(mcasp->dev);
1393
1394 return 0;
1395 }
1396
davinci_mcasp_resume(struct snd_soc_dai * dai)1397 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1398 {
1399 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1400 struct davinci_mcasp_context *context = &mcasp->context;
1401 u32 reg;
1402 int i;
1403
1404 pm_runtime_get_sync(mcasp->dev);
1405
1406 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1407 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1408
1409 if (mcasp->txnumevt) {
1410 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1411 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1412 }
1413 if (mcasp->rxnumevt) {
1414 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1415 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1416 }
1417
1418 for (i = 0; i < mcasp->num_serializer; i++)
1419 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1420 context->xrsr_regs[i]);
1421
1422 if (!context->pm_state)
1423 pm_runtime_put_sync(mcasp->dev);
1424
1425 return 0;
1426 }
1427 #else
1428 #define davinci_mcasp_suspend NULL
1429 #define davinci_mcasp_resume NULL
1430 #endif
1431
1432 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1433
1434 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1435 SNDRV_PCM_FMTBIT_U8 | \
1436 SNDRV_PCM_FMTBIT_S16_LE | \
1437 SNDRV_PCM_FMTBIT_U16_LE | \
1438 SNDRV_PCM_FMTBIT_S24_LE | \
1439 SNDRV_PCM_FMTBIT_U24_LE | \
1440 SNDRV_PCM_FMTBIT_S24_3LE | \
1441 SNDRV_PCM_FMTBIT_U24_3LE | \
1442 SNDRV_PCM_FMTBIT_S32_LE | \
1443 SNDRV_PCM_FMTBIT_U32_LE)
1444
1445 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1446 {
1447 .name = "davinci-mcasp.0",
1448 .probe = davinci_mcasp_dai_probe,
1449 .suspend = davinci_mcasp_suspend,
1450 .resume = davinci_mcasp_resume,
1451 .playback = {
1452 .channels_min = 2,
1453 .channels_max = 32 * 16,
1454 .rates = DAVINCI_MCASP_RATES,
1455 .formats = DAVINCI_MCASP_PCM_FMTS,
1456 },
1457 .capture = {
1458 .channels_min = 2,
1459 .channels_max = 32 * 16,
1460 .rates = DAVINCI_MCASP_RATES,
1461 .formats = DAVINCI_MCASP_PCM_FMTS,
1462 },
1463 .ops = &davinci_mcasp_dai_ops,
1464
1465 .symmetric_samplebits = 1,
1466 .symmetric_rates = 1,
1467 },
1468 {
1469 .name = "davinci-mcasp.1",
1470 .probe = davinci_mcasp_dai_probe,
1471 .playback = {
1472 .channels_min = 1,
1473 .channels_max = 384,
1474 .rates = DAVINCI_MCASP_RATES,
1475 .formats = DAVINCI_MCASP_PCM_FMTS,
1476 },
1477 .ops = &davinci_mcasp_dai_ops,
1478 },
1479
1480 };
1481
1482 static const struct snd_soc_component_driver davinci_mcasp_component = {
1483 .name = "davinci-mcasp",
1484 };
1485
1486 /* Some HW specific values and defaults. The rest is filled in from DT. */
1487 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1488 .tx_dma_offset = 0x400,
1489 .rx_dma_offset = 0x400,
1490 .version = MCASP_VERSION_1,
1491 };
1492
1493 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1494 .tx_dma_offset = 0x2000,
1495 .rx_dma_offset = 0x2000,
1496 .version = MCASP_VERSION_2,
1497 };
1498
1499 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1500 .tx_dma_offset = 0,
1501 .rx_dma_offset = 0,
1502 .version = MCASP_VERSION_3,
1503 };
1504
1505 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1506 .tx_dma_offset = 0x200,
1507 .rx_dma_offset = 0x284,
1508 .version = MCASP_VERSION_4,
1509 };
1510
1511 static const struct of_device_id mcasp_dt_ids[] = {
1512 {
1513 .compatible = "ti,dm646x-mcasp-audio",
1514 .data = &dm646x_mcasp_pdata,
1515 },
1516 {
1517 .compatible = "ti,da830-mcasp-audio",
1518 .data = &da830_mcasp_pdata,
1519 },
1520 {
1521 .compatible = "ti,am33xx-mcasp-audio",
1522 .data = &am33xx_mcasp_pdata,
1523 },
1524 {
1525 .compatible = "ti,dra7-mcasp-audio",
1526 .data = &dra7_mcasp_pdata,
1527 },
1528 { /* sentinel */ }
1529 };
1530 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1531
mcasp_reparent_fck(struct platform_device * pdev)1532 static int mcasp_reparent_fck(struct platform_device *pdev)
1533 {
1534 struct device_node *node = pdev->dev.of_node;
1535 struct clk *gfclk, *parent_clk;
1536 const char *parent_name;
1537 int ret;
1538
1539 if (!node)
1540 return 0;
1541
1542 parent_name = of_get_property(node, "fck_parent", NULL);
1543 if (!parent_name)
1544 return 0;
1545
1546 gfclk = clk_get(&pdev->dev, "fck");
1547 if (IS_ERR(gfclk)) {
1548 dev_err(&pdev->dev, "failed to get fck\n");
1549 return PTR_ERR(gfclk);
1550 }
1551
1552 parent_clk = clk_get(NULL, parent_name);
1553 if (IS_ERR(parent_clk)) {
1554 dev_err(&pdev->dev, "failed to get parent clock\n");
1555 ret = PTR_ERR(parent_clk);
1556 goto err1;
1557 }
1558
1559 ret = clk_set_parent(gfclk, parent_clk);
1560 if (ret) {
1561 dev_err(&pdev->dev, "failed to reparent fck\n");
1562 goto err2;
1563 }
1564
1565 err2:
1566 clk_put(parent_clk);
1567 err1:
1568 clk_put(gfclk);
1569 return ret;
1570 }
1571
davinci_mcasp_set_pdata_from_of(struct platform_device * pdev)1572 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1573 struct platform_device *pdev)
1574 {
1575 struct device_node *np = pdev->dev.of_node;
1576 struct davinci_mcasp_pdata *pdata = NULL;
1577 const struct of_device_id *match =
1578 of_match_device(mcasp_dt_ids, &pdev->dev);
1579 struct of_phandle_args dma_spec;
1580
1581 const u32 *of_serial_dir32;
1582 u32 val;
1583 int i, ret = 0;
1584
1585 if (pdev->dev.platform_data) {
1586 pdata = pdev->dev.platform_data;
1587 return pdata;
1588 } else if (match) {
1589 pdata = (struct davinci_mcasp_pdata*) match->data;
1590 } else {
1591 /* control shouldn't reach here. something is wrong */
1592 ret = -EINVAL;
1593 goto nodata;
1594 }
1595
1596 ret = of_property_read_u32(np, "op-mode", &val);
1597 if (ret >= 0)
1598 pdata->op_mode = val;
1599
1600 ret = of_property_read_u32(np, "tdm-slots", &val);
1601 if (ret >= 0) {
1602 if (val < 2 || val > 32) {
1603 dev_err(&pdev->dev,
1604 "tdm-slots must be in rage [2-32]\n");
1605 ret = -EINVAL;
1606 goto nodata;
1607 }
1608
1609 pdata->tdm_slots = val;
1610 }
1611
1612 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1613 val /= sizeof(u32);
1614 if (of_serial_dir32) {
1615 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1616 (sizeof(*of_serial_dir) * val),
1617 GFP_KERNEL);
1618 if (!of_serial_dir) {
1619 ret = -ENOMEM;
1620 goto nodata;
1621 }
1622
1623 for (i = 0; i < val; i++)
1624 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1625
1626 pdata->num_serializer = val;
1627 pdata->serial_dir = of_serial_dir;
1628 }
1629
1630 ret = of_property_match_string(np, "dma-names", "tx");
1631 if (ret < 0)
1632 goto nodata;
1633
1634 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1635 &dma_spec);
1636 if (ret < 0)
1637 goto nodata;
1638
1639 pdata->tx_dma_channel = dma_spec.args[0];
1640
1641 /* RX is not valid in DIT mode */
1642 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1643 ret = of_property_match_string(np, "dma-names", "rx");
1644 if (ret < 0)
1645 goto nodata;
1646
1647 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1648 &dma_spec);
1649 if (ret < 0)
1650 goto nodata;
1651
1652 pdata->rx_dma_channel = dma_spec.args[0];
1653 }
1654
1655 ret = of_property_read_u32(np, "tx-num-evt", &val);
1656 if (ret >= 0)
1657 pdata->txnumevt = val;
1658
1659 ret = of_property_read_u32(np, "rx-num-evt", &val);
1660 if (ret >= 0)
1661 pdata->rxnumevt = val;
1662
1663 ret = of_property_read_u32(np, "sram-size-playback", &val);
1664 if (ret >= 0)
1665 pdata->sram_size_playback = val;
1666
1667 ret = of_property_read_u32(np, "sram-size-capture", &val);
1668 if (ret >= 0)
1669 pdata->sram_size_capture = val;
1670
1671 return pdata;
1672
1673 nodata:
1674 if (ret < 0) {
1675 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1676 ret);
1677 pdata = NULL;
1678 }
1679 return pdata;
1680 }
1681
1682 enum {
1683 PCM_EDMA,
1684 PCM_SDMA,
1685 };
1686 static const char *sdma_prefix = "ti,omap";
1687
davinci_mcasp_get_dma_type(struct davinci_mcasp * mcasp)1688 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1689 {
1690 struct dma_chan *chan;
1691 const char *tmp;
1692 int ret = PCM_EDMA;
1693
1694 if (!mcasp->dev->of_node)
1695 return PCM_EDMA;
1696
1697 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1698 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1699 if (IS_ERR(chan)) {
1700 if (PTR_ERR(chan) != -EPROBE_DEFER)
1701 dev_err(mcasp->dev,
1702 "Can't verify DMA configuration (%ld)\n",
1703 PTR_ERR(chan));
1704 return PTR_ERR(chan);
1705 }
1706 BUG_ON(!chan->device || !chan->device->dev);
1707
1708 if (chan->device->dev->of_node)
1709 ret = of_property_read_string(chan->device->dev->of_node,
1710 "compatible", &tmp);
1711 else
1712 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1713
1714 dma_release_channel(chan);
1715 if (ret)
1716 return ret;
1717
1718 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1719 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1720 return PCM_SDMA;
1721
1722 return PCM_EDMA;
1723 }
1724
davinci_mcasp_probe(struct platform_device * pdev)1725 static int davinci_mcasp_probe(struct platform_device *pdev)
1726 {
1727 struct snd_dmaengine_dai_dma_data *dma_data;
1728 struct resource *mem, *res, *dat;
1729 struct davinci_mcasp_pdata *pdata;
1730 struct davinci_mcasp *mcasp;
1731 char *irq_name;
1732 int *dma;
1733 int irq;
1734 int ret;
1735
1736 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1737 dev_err(&pdev->dev, "No platform data supplied\n");
1738 return -EINVAL;
1739 }
1740
1741 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1742 GFP_KERNEL);
1743 if (!mcasp)
1744 return -ENOMEM;
1745
1746 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1747 if (!pdata) {
1748 dev_err(&pdev->dev, "no platform data\n");
1749 return -EINVAL;
1750 }
1751
1752 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1753 if (!mem) {
1754 dev_warn(mcasp->dev,
1755 "\"mpu\" mem resource not found, using index 0\n");
1756 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1757 if (!mem) {
1758 dev_err(&pdev->dev, "no mem resource?\n");
1759 return -ENODEV;
1760 }
1761 }
1762
1763 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1764 if (IS_ERR(mcasp->base))
1765 return PTR_ERR(mcasp->base);
1766
1767 pm_runtime_enable(&pdev->dev);
1768
1769 mcasp->op_mode = pdata->op_mode;
1770 /* sanity check for tdm slots parameter */
1771 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1772 if (pdata->tdm_slots < 2) {
1773 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1774 pdata->tdm_slots);
1775 mcasp->tdm_slots = 2;
1776 } else if (pdata->tdm_slots > 32) {
1777 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1778 pdata->tdm_slots);
1779 mcasp->tdm_slots = 32;
1780 } else {
1781 mcasp->tdm_slots = pdata->tdm_slots;
1782 }
1783 }
1784
1785 mcasp->num_serializer = pdata->num_serializer;
1786 #ifdef CONFIG_PM_SLEEP
1787 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1788 sizeof(u32) * mcasp->num_serializer,
1789 GFP_KERNEL);
1790 #endif
1791 mcasp->serial_dir = pdata->serial_dir;
1792 mcasp->version = pdata->version;
1793 mcasp->txnumevt = pdata->txnumevt;
1794 mcasp->rxnumevt = pdata->rxnumevt;
1795
1796 mcasp->dev = &pdev->dev;
1797
1798 irq = platform_get_irq_byname(pdev, "common");
1799 if (irq >= 0) {
1800 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1801 dev_name(&pdev->dev));
1802 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1803 davinci_mcasp_common_irq_handler,
1804 IRQF_ONESHOT | IRQF_SHARED,
1805 irq_name, mcasp);
1806 if (ret) {
1807 dev_err(&pdev->dev, "common IRQ request failed\n");
1808 goto err;
1809 }
1810
1811 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1812 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1813 }
1814
1815 irq = platform_get_irq_byname(pdev, "rx");
1816 if (irq >= 0) {
1817 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1818 dev_name(&pdev->dev));
1819 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1820 davinci_mcasp_rx_irq_handler,
1821 IRQF_ONESHOT, irq_name, mcasp);
1822 if (ret) {
1823 dev_err(&pdev->dev, "RX IRQ request failed\n");
1824 goto err;
1825 }
1826
1827 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1828 }
1829
1830 irq = platform_get_irq_byname(pdev, "tx");
1831 if (irq >= 0) {
1832 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1833 dev_name(&pdev->dev));
1834 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1835 davinci_mcasp_tx_irq_handler,
1836 IRQF_ONESHOT, irq_name, mcasp);
1837 if (ret) {
1838 dev_err(&pdev->dev, "TX IRQ request failed\n");
1839 goto err;
1840 }
1841
1842 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1843 }
1844
1845 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1846 if (dat)
1847 mcasp->dat_port = true;
1848
1849 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1850 if (dat)
1851 dma_data->addr = dat->start;
1852 else
1853 dma_data->addr = mem->start + pdata->tx_dma_offset;
1854
1855 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1856 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1857 if (res)
1858 *dma = res->start;
1859 else
1860 *dma = pdata->tx_dma_channel;
1861
1862 /* dmaengine filter data for DT and non-DT boot */
1863 if (pdev->dev.of_node)
1864 dma_data->filter_data = "tx";
1865 else
1866 dma_data->filter_data = dma;
1867
1868 /* RX is not valid in DIT mode */
1869 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1870 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1871 if (dat)
1872 dma_data->addr = dat->start;
1873 else
1874 dma_data->addr = mem->start + pdata->rx_dma_offset;
1875
1876 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1877 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1878 if (res)
1879 *dma = res->start;
1880 else
1881 *dma = pdata->rx_dma_channel;
1882
1883 /* dmaengine filter data for DT and non-DT boot */
1884 if (pdev->dev.of_node)
1885 dma_data->filter_data = "rx";
1886 else
1887 dma_data->filter_data = dma;
1888 }
1889
1890 if (mcasp->version < MCASP_VERSION_3) {
1891 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1892 /* dma_params->dma_addr is pointing to the data port address */
1893 mcasp->dat_port = true;
1894 } else {
1895 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1896 }
1897
1898 /* Allocate memory for long enough list for all possible
1899 * scenarios. Maximum number tdm slots is 32 and there cannot
1900 * be more serializers than given in the configuration. The
1901 * serializer directions could be taken into account, but it
1902 * would make code much more complex and save only couple of
1903 * bytes.
1904 */
1905 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
1906 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1907 (32 + mcasp->num_serializer - 2),
1908 GFP_KERNEL);
1909
1910 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
1911 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1912 (32 + mcasp->num_serializer - 2),
1913 GFP_KERNEL);
1914
1915 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
1916 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list)
1917 return -ENOMEM;
1918
1919 ret = davinci_mcasp_set_ch_constraints(mcasp);
1920 if (ret)
1921 goto err;
1922
1923 dev_set_drvdata(&pdev->dev, mcasp);
1924
1925 mcasp_reparent_fck(pdev);
1926
1927 ret = devm_snd_soc_register_component(&pdev->dev,
1928 &davinci_mcasp_component,
1929 &davinci_mcasp_dai[pdata->op_mode], 1);
1930
1931 if (ret != 0)
1932 goto err;
1933
1934 ret = davinci_mcasp_get_dma_type(mcasp);
1935 switch (ret) {
1936 case PCM_EDMA:
1937 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1938 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1939 IS_MODULE(CONFIG_SND_EDMA_SOC))
1940 ret = edma_pcm_platform_register(&pdev->dev);
1941 #else
1942 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
1943 ret = -EINVAL;
1944 goto err;
1945 #endif
1946 break;
1947 case PCM_SDMA:
1948 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1949 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1950 IS_MODULE(CONFIG_SND_OMAP_SOC))
1951 ret = omap_pcm_platform_register(&pdev->dev);
1952 #else
1953 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
1954 ret = -EINVAL;
1955 goto err;
1956 #endif
1957 break;
1958 default:
1959 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
1960 case -EPROBE_DEFER:
1961 goto err;
1962 break;
1963 }
1964
1965 if (ret) {
1966 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1967 goto err;
1968 }
1969
1970 return 0;
1971
1972 err:
1973 pm_runtime_disable(&pdev->dev);
1974 return ret;
1975 }
1976
davinci_mcasp_remove(struct platform_device * pdev)1977 static int davinci_mcasp_remove(struct platform_device *pdev)
1978 {
1979 pm_runtime_disable(&pdev->dev);
1980
1981 return 0;
1982 }
1983
1984 static struct platform_driver davinci_mcasp_driver = {
1985 .probe = davinci_mcasp_probe,
1986 .remove = davinci_mcasp_remove,
1987 .driver = {
1988 .name = "davinci-mcasp",
1989 .of_match_table = mcasp_dt_ids,
1990 },
1991 };
1992
1993 module_platform_driver(davinci_mcasp_driver);
1994
1995 MODULE_AUTHOR("Steve Chen");
1996 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1997 MODULE_LICENSE("GPL");
1998