1 /*
2 * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
3 *
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11 #include <linux/clk.h>
12 #include <linux/dmaengine.h>
13 #include <linux/module.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
18
19 #include "fsl_esai.h"
20 #include "imx-pcm.h"
21
22 #define FSL_ESAI_RATES SNDRV_PCM_RATE_8000_192000
23 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
24 SNDRV_PCM_FMTBIT_S16_LE | \
25 SNDRV_PCM_FMTBIT_S20_3LE | \
26 SNDRV_PCM_FMTBIT_S24_LE)
27
28 /**
29 * fsl_esai: ESAI private data
30 *
31 * @dma_params_rx: DMA parameters for receive channel
32 * @dma_params_tx: DMA parameters for transmit channel
33 * @pdev: platform device pointer
34 * @regmap: regmap handler
35 * @coreclk: clock source to access register
36 * @extalclk: esai clock source to derive HCK, SCK and FS
37 * @fsysclk: system clock source to derive HCK, SCK and FS
38 * @fifo_depth: depth of tx/rx FIFO
39 * @slot_width: width of each DAI slot
40 * @slots: number of slots
41 * @hck_rate: clock rate of desired HCKx clock
42 * @sck_rate: clock rate of desired SCKx clock
43 * @hck_dir: the direction of HCKx pads
44 * @sck_div: if using PSR/PM dividers for SCKx clock
45 * @slave_mode: if fully using DAI slave mode
46 * @synchronous: if using tx/rx synchronous mode
47 * @name: driver name
48 */
49 struct fsl_esai {
50 struct snd_dmaengine_dai_dma_data dma_params_rx;
51 struct snd_dmaengine_dai_dma_data dma_params_tx;
52 struct platform_device *pdev;
53 struct regmap *regmap;
54 struct clk *coreclk;
55 struct clk *extalclk;
56 struct clk *fsysclk;
57 u32 fifo_depth;
58 u32 slot_width;
59 u32 slots;
60 u32 tx_mask;
61 u32 rx_mask;
62 u32 hck_rate[2];
63 u32 sck_rate[2];
64 bool hck_dir[2];
65 bool sck_div[2];
66 bool slave_mode;
67 bool synchronous;
68 char name[32];
69 };
70
esai_isr(int irq,void * devid)71 static irqreturn_t esai_isr(int irq, void *devid)
72 {
73 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
74 struct platform_device *pdev = esai_priv->pdev;
75 u32 esr;
76
77 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
78
79 if (esr & ESAI_ESR_TINIT_MASK)
80 dev_dbg(&pdev->dev, "isr: Transmition Initialized\n");
81
82 if (esr & ESAI_ESR_RFF_MASK)
83 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
84
85 if (esr & ESAI_ESR_TFE_MASK)
86 dev_warn(&pdev->dev, "isr: Transmition underrun\n");
87
88 if (esr & ESAI_ESR_TLS_MASK)
89 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
90
91 if (esr & ESAI_ESR_TDE_MASK)
92 dev_dbg(&pdev->dev, "isr: Transmition data exception\n");
93
94 if (esr & ESAI_ESR_TED_MASK)
95 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
96
97 if (esr & ESAI_ESR_TD_MASK)
98 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
99
100 if (esr & ESAI_ESR_RLS_MASK)
101 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
102
103 if (esr & ESAI_ESR_RDE_MASK)
104 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
105
106 if (esr & ESAI_ESR_RED_MASK)
107 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
108
109 if (esr & ESAI_ESR_RD_MASK)
110 dev_dbg(&pdev->dev, "isr: Receiving data\n");
111
112 return IRQ_HANDLED;
113 }
114
115 /**
116 * This function is used to calculate the divisors of psr, pm, fp and it is
117 * supposed to be called in set_dai_sysclk() and set_bclk().
118 *
119 * @ratio: desired overall ratio for the paticipating dividers
120 * @usefp: for HCK setting, there is no need to set fp divider
121 * @fp: bypass other dividers by setting fp directly if fp != 0
122 * @tx: current setting is for playback or capture
123 */
fsl_esai_divisor_cal(struct snd_soc_dai * dai,bool tx,u32 ratio,bool usefp,u32 fp)124 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
125 bool usefp, u32 fp)
126 {
127 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
128 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
129
130 maxfp = usefp ? 16 : 1;
131
132 if (usefp && fp)
133 goto out_fp;
134
135 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
136 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
137 2 * 8 * 256 * maxfp);
138 return -EINVAL;
139 } else if (ratio % 2) {
140 dev_err(dai->dev, "the raio must be even if using upper divider\n");
141 return -EINVAL;
142 }
143
144 ratio /= 2;
145
146 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
147
148 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
149 if (ratio <= 256) {
150 pm = ratio;
151 fp = 1;
152 goto out;
153 }
154
155 /* Set the max fluctuation -- 0.1% of the max devisor */
156 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
157
158 /* Find the best value for PM */
159 for (i = 1; i <= 256; i++) {
160 for (j = 1; j <= maxfp; j++) {
161 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
162 prod = (psr ? 1 : 8) * i * j;
163
164 if (prod == ratio)
165 sub = 0;
166 else if (prod / ratio == 1)
167 sub = prod - ratio;
168 else if (ratio / prod == 1)
169 sub = ratio - prod;
170 else
171 continue;
172
173 /* Calculate the fraction */
174 sub = sub * 1000 / ratio;
175 if (sub < savesub) {
176 savesub = sub;
177 pm = i;
178 fp = j;
179 }
180
181 /* We are lucky */
182 if (savesub == 0)
183 goto out;
184 }
185 }
186
187 if (pm == 999) {
188 dev_err(dai->dev, "failed to calculate proper divisors\n");
189 return -EINVAL;
190 }
191
192 out:
193 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
194 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
195 psr | ESAI_xCCR_xPM(pm));
196
197 out_fp:
198 /* Bypass fp if not being required */
199 if (maxfp <= 1)
200 return 0;
201
202 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
203 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
204
205 return 0;
206 }
207
208 /**
209 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
210 *
211 * @Parameters:
212 * clk_id: The clock source of HCKT/HCKR
213 * (Input from outside; output from inside, FSYS or EXTAL)
214 * freq: The required clock rate of HCKT/HCKR
215 * dir: The clock direction of HCKT/HCKR
216 *
217 * Note: If the direction is input, we do not care about clk_id.
218 */
fsl_esai_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)219 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
220 unsigned int freq, int dir)
221 {
222 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
223 struct clk *clksrc = esai_priv->extalclk;
224 bool tx = clk_id <= ESAI_HCKT_EXTAL;
225 bool in = dir == SND_SOC_CLOCK_IN;
226 u32 ratio, ecr = 0;
227 unsigned long clk_rate;
228 int ret;
229
230 /* Bypass divider settings if the requirement doesn't change */
231 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
232 return 0;
233
234 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
235 esai_priv->sck_div[tx] = true;
236
237 /* Set the direction of HCKT/HCKR pins */
238 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
239 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
240
241 if (in)
242 goto out;
243
244 switch (clk_id) {
245 case ESAI_HCKT_FSYS:
246 case ESAI_HCKR_FSYS:
247 clksrc = esai_priv->fsysclk;
248 break;
249 case ESAI_HCKT_EXTAL:
250 ecr |= ESAI_ECR_ETI;
251 case ESAI_HCKR_EXTAL:
252 ecr |= ESAI_ECR_ERI;
253 break;
254 default:
255 return -EINVAL;
256 }
257
258 if (IS_ERR(clksrc)) {
259 dev_err(dai->dev, "no assigned %s clock\n",
260 clk_id % 2 ? "extal" : "fsys");
261 return PTR_ERR(clksrc);
262 }
263 clk_rate = clk_get_rate(clksrc);
264
265 ratio = clk_rate / freq;
266 if (ratio * freq > clk_rate)
267 ret = ratio * freq - clk_rate;
268 else if (ratio * freq < clk_rate)
269 ret = clk_rate - ratio * freq;
270 else
271 ret = 0;
272
273 /* Block if clock source can not be divided into the required rate */
274 if (ret != 0 && clk_rate / ret < 1000) {
275 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
276 tx ? 'T' : 'R');
277 return -EINVAL;
278 }
279
280 /* Only EXTAL source can be output directly without using PSR and PM */
281 if (ratio == 1 && clksrc == esai_priv->extalclk) {
282 /* Bypass all the dividers if not being needed */
283 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
284 goto out;
285 } else if (ratio < 2) {
286 /* The ratio should be no less than 2 if using other sources */
287 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
288 tx ? 'T' : 'R');
289 return -EINVAL;
290 }
291
292 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
293 if (ret)
294 return ret;
295
296 esai_priv->sck_div[tx] = false;
297
298 out:
299 esai_priv->hck_dir[tx] = dir;
300 esai_priv->hck_rate[tx] = freq;
301
302 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
303 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
304 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
305
306 return 0;
307 }
308
309 /**
310 * This function configures the related dividers according to the bclk rate
311 */
fsl_esai_set_bclk(struct snd_soc_dai * dai,bool tx,u32 freq)312 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
313 {
314 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
315 u32 hck_rate = esai_priv->hck_rate[tx];
316 u32 sub, ratio = hck_rate / freq;
317 int ret;
318
319 /* Don't apply for fully slave mode or unchanged bclk */
320 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
321 return 0;
322
323 if (ratio * freq > hck_rate)
324 sub = ratio * freq - hck_rate;
325 else if (ratio * freq < hck_rate)
326 sub = hck_rate - ratio * freq;
327 else
328 sub = 0;
329
330 /* Block if clock source can not be divided into the required rate */
331 if (sub != 0 && hck_rate / sub < 1000) {
332 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
333 tx ? 'T' : 'R');
334 return -EINVAL;
335 }
336
337 /* The ratio should be contented by FP alone if bypassing PM and PSR */
338 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
339 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
340 return -EINVAL;
341 }
342
343 ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
344 esai_priv->sck_div[tx] ? 0 : ratio);
345 if (ret)
346 return ret;
347
348 /* Save current bclk rate */
349 esai_priv->sck_rate[tx] = freq;
350
351 return 0;
352 }
353
fsl_esai_set_dai_tdm_slot(struct snd_soc_dai * dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)354 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
355 u32 rx_mask, int slots, int slot_width)
356 {
357 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
358
359 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
360 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
361
362 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
363 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
364
365 esai_priv->slot_width = slot_width;
366 esai_priv->slots = slots;
367 esai_priv->tx_mask = tx_mask;
368 esai_priv->rx_mask = rx_mask;
369
370 return 0;
371 }
372
fsl_esai_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)373 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
374 {
375 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
376 u32 xcr = 0, xccr = 0, mask;
377
378 /* DAI mode */
379 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
380 case SND_SOC_DAIFMT_I2S:
381 /* Data on rising edge of bclk, frame low, 1clk before data */
382 xcr |= ESAI_xCR_xFSR;
383 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
384 break;
385 case SND_SOC_DAIFMT_LEFT_J:
386 /* Data on rising edge of bclk, frame high */
387 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
388 break;
389 case SND_SOC_DAIFMT_RIGHT_J:
390 /* Data on rising edge of bclk, frame high, right aligned */
391 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
392 xcr |= ESAI_xCR_xWA;
393 break;
394 case SND_SOC_DAIFMT_DSP_A:
395 /* Data on rising edge of bclk, frame high, 1clk before data */
396 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
397 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
398 break;
399 case SND_SOC_DAIFMT_DSP_B:
400 /* Data on rising edge of bclk, frame high */
401 xcr |= ESAI_xCR_xFSL;
402 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
403 break;
404 default:
405 return -EINVAL;
406 }
407
408 /* DAI clock inversion */
409 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
410 case SND_SOC_DAIFMT_NB_NF:
411 /* Nothing to do for both normal cases */
412 break;
413 case SND_SOC_DAIFMT_IB_NF:
414 /* Invert bit clock */
415 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
416 break;
417 case SND_SOC_DAIFMT_NB_IF:
418 /* Invert frame clock */
419 xccr ^= ESAI_xCCR_xFSP;
420 break;
421 case SND_SOC_DAIFMT_IB_IF:
422 /* Invert both clocks */
423 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
424 break;
425 default:
426 return -EINVAL;
427 }
428
429 esai_priv->slave_mode = false;
430
431 /* DAI clock master masks */
432 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
433 case SND_SOC_DAIFMT_CBM_CFM:
434 esai_priv->slave_mode = true;
435 break;
436 case SND_SOC_DAIFMT_CBS_CFM:
437 xccr |= ESAI_xCCR_xCKD;
438 break;
439 case SND_SOC_DAIFMT_CBM_CFS:
440 xccr |= ESAI_xCCR_xFSD;
441 break;
442 case SND_SOC_DAIFMT_CBS_CFS:
443 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
444 break;
445 default:
446 return -EINVAL;
447 }
448
449 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA;
450 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
451 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
452
453 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
454 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
455 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
456 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
457
458 return 0;
459 }
460
fsl_esai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)461 static int fsl_esai_startup(struct snd_pcm_substream *substream,
462 struct snd_soc_dai *dai)
463 {
464 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
465 int ret;
466
467 /*
468 * Some platforms might use the same bit to gate all three or two of
469 * clocks, so keep all clocks open/close at the same time for safety
470 */
471 ret = clk_prepare_enable(esai_priv->coreclk);
472 if (ret)
473 return ret;
474 if (!IS_ERR(esai_priv->extalclk)) {
475 ret = clk_prepare_enable(esai_priv->extalclk);
476 if (ret)
477 goto err_extalck;
478 }
479 if (!IS_ERR(esai_priv->fsysclk)) {
480 ret = clk_prepare_enable(esai_priv->fsysclk);
481 if (ret)
482 goto err_fsysclk;
483 }
484
485 if (!dai->active) {
486 /* Set synchronous mode */
487 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
488 ESAI_SAICR_SYNC, esai_priv->synchronous ?
489 ESAI_SAICR_SYNC : 0);
490
491 /* Set slots count */
492 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
493 ESAI_xCCR_xDC_MASK,
494 ESAI_xCCR_xDC(esai_priv->slots));
495 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
496 ESAI_xCCR_xDC_MASK,
497 ESAI_xCCR_xDC(esai_priv->slots));
498 }
499
500 return 0;
501
502 err_fsysclk:
503 if (!IS_ERR(esai_priv->extalclk))
504 clk_disable_unprepare(esai_priv->extalclk);
505 err_extalck:
506 clk_disable_unprepare(esai_priv->coreclk);
507
508 return ret;
509 }
510
fsl_esai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)511 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
512 struct snd_pcm_hw_params *params,
513 struct snd_soc_dai *dai)
514 {
515 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
516 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
517 u32 width = snd_pcm_format_width(params_format(params));
518 u32 channels = params_channels(params);
519 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
520 u32 slot_width = width;
521 u32 bclk, mask, val;
522 int ret;
523
524 /* Override slot_width if being specifically set */
525 if (esai_priv->slot_width)
526 slot_width = esai_priv->slot_width;
527
528 bclk = params_rate(params) * slot_width * esai_priv->slots;
529
530 ret = fsl_esai_set_bclk(dai, tx, bclk);
531 if (ret)
532 return ret;
533
534 /* Use Normal mode to support monaural audio */
535 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
536 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
537 ESAI_xCR_xMOD_NETWORK : 0);
538
539 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
540 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
541
542 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
543 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
544 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
545 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
546
547 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
548
549 mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
550 val = ESAI_xCR_xSWS(slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
551
552 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
553
554 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
555 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
556 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
557 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
558 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
559 return 0;
560 }
561
fsl_esai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)562 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
563 struct snd_soc_dai *dai)
564 {
565 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
566
567 if (!IS_ERR(esai_priv->fsysclk))
568 clk_disable_unprepare(esai_priv->fsysclk);
569 if (!IS_ERR(esai_priv->extalclk))
570 clk_disable_unprepare(esai_priv->extalclk);
571 clk_disable_unprepare(esai_priv->coreclk);
572 }
573
fsl_esai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)574 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
575 struct snd_soc_dai *dai)
576 {
577 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
578 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
579 u8 i, channels = substream->runtime->channels;
580 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
581 u32 mask;
582
583 switch (cmd) {
584 case SNDRV_PCM_TRIGGER_START:
585 case SNDRV_PCM_TRIGGER_RESUME:
586 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
587 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
588 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
589
590 /* Write initial words reqiured by ESAI as normal procedure */
591 for (i = 0; tx && i < channels; i++)
592 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
593
594 /*
595 * When set the TE/RE in the end of enablement flow, there
596 * will be channel swap issue for multi data line case.
597 * In order to workaround this issue, we switch the bit
598 * enablement sequence to below sequence
599 * 1) clear the xSMB & xSMA: which is done in probe and
600 * stop state.
601 * 2) set TE/RE
602 * 3) set xSMB
603 * 4) set xSMA: xSMA is the last one in this flow, which
604 * will trigger esai to start.
605 */
606 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
607 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
608 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
609 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
610
611 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
612 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
613 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
614 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
615
616 break;
617 case SNDRV_PCM_TRIGGER_SUSPEND:
618 case SNDRV_PCM_TRIGGER_STOP:
619 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
620 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
621 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
622 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
623 ESAI_xSMA_xS_MASK, 0);
624 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
625 ESAI_xSMB_xS_MASK, 0);
626
627 /* Disable and reset FIFO */
628 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
629 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
630 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
631 ESAI_xFCR_xFR, 0);
632 break;
633 default:
634 return -EINVAL;
635 }
636
637 return 0;
638 }
639
640 static struct snd_soc_dai_ops fsl_esai_dai_ops = {
641 .startup = fsl_esai_startup,
642 .shutdown = fsl_esai_shutdown,
643 .trigger = fsl_esai_trigger,
644 .hw_params = fsl_esai_hw_params,
645 .set_sysclk = fsl_esai_set_dai_sysclk,
646 .set_fmt = fsl_esai_set_dai_fmt,
647 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
648 };
649
fsl_esai_dai_probe(struct snd_soc_dai * dai)650 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
651 {
652 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
653
654 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
655 &esai_priv->dma_params_rx);
656
657 return 0;
658 }
659
660 static struct snd_soc_dai_driver fsl_esai_dai = {
661 .probe = fsl_esai_dai_probe,
662 .playback = {
663 .stream_name = "CPU-Playback",
664 .channels_min = 1,
665 .channels_max = 12,
666 .rates = FSL_ESAI_RATES,
667 .formats = FSL_ESAI_FORMATS,
668 },
669 .capture = {
670 .stream_name = "CPU-Capture",
671 .channels_min = 1,
672 .channels_max = 8,
673 .rates = FSL_ESAI_RATES,
674 .formats = FSL_ESAI_FORMATS,
675 },
676 .ops = &fsl_esai_dai_ops,
677 };
678
679 static const struct snd_soc_component_driver fsl_esai_component = {
680 .name = "fsl-esai",
681 };
682
683 static const struct reg_default fsl_esai_reg_defaults[] = {
684 {0x8, 0x00000000},
685 {0x10, 0x00000000},
686 {0x18, 0x00000000},
687 {0x98, 0x00000000},
688 {0xd0, 0x00000000},
689 {0xd4, 0x00000000},
690 {0xd8, 0x00000000},
691 {0xdc, 0x00000000},
692 {0xe0, 0x00000000},
693 {0xe4, 0x0000ffff},
694 {0xe8, 0x0000ffff},
695 {0xec, 0x0000ffff},
696 {0xf0, 0x0000ffff},
697 {0xf8, 0x00000000},
698 {0xfc, 0x00000000},
699 };
700
fsl_esai_readable_reg(struct device * dev,unsigned int reg)701 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
702 {
703 switch (reg) {
704 case REG_ESAI_ERDR:
705 case REG_ESAI_ECR:
706 case REG_ESAI_ESR:
707 case REG_ESAI_TFCR:
708 case REG_ESAI_TFSR:
709 case REG_ESAI_RFCR:
710 case REG_ESAI_RFSR:
711 case REG_ESAI_RX0:
712 case REG_ESAI_RX1:
713 case REG_ESAI_RX2:
714 case REG_ESAI_RX3:
715 case REG_ESAI_SAISR:
716 case REG_ESAI_SAICR:
717 case REG_ESAI_TCR:
718 case REG_ESAI_TCCR:
719 case REG_ESAI_RCR:
720 case REG_ESAI_RCCR:
721 case REG_ESAI_TSMA:
722 case REG_ESAI_TSMB:
723 case REG_ESAI_RSMA:
724 case REG_ESAI_RSMB:
725 case REG_ESAI_PRRC:
726 case REG_ESAI_PCRC:
727 return true;
728 default:
729 return false;
730 }
731 }
732
fsl_esai_volatile_reg(struct device * dev,unsigned int reg)733 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
734 {
735 switch (reg) {
736 case REG_ESAI_ETDR:
737 case REG_ESAI_ERDR:
738 case REG_ESAI_ESR:
739 case REG_ESAI_TFSR:
740 case REG_ESAI_RFSR:
741 case REG_ESAI_TX0:
742 case REG_ESAI_TX1:
743 case REG_ESAI_TX2:
744 case REG_ESAI_TX3:
745 case REG_ESAI_TX4:
746 case REG_ESAI_TX5:
747 case REG_ESAI_RX0:
748 case REG_ESAI_RX1:
749 case REG_ESAI_RX2:
750 case REG_ESAI_RX3:
751 case REG_ESAI_SAISR:
752 return true;
753 default:
754 return false;
755 }
756 }
757
fsl_esai_writeable_reg(struct device * dev,unsigned int reg)758 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
759 {
760 switch (reg) {
761 case REG_ESAI_ETDR:
762 case REG_ESAI_ECR:
763 case REG_ESAI_TFCR:
764 case REG_ESAI_RFCR:
765 case REG_ESAI_TX0:
766 case REG_ESAI_TX1:
767 case REG_ESAI_TX2:
768 case REG_ESAI_TX3:
769 case REG_ESAI_TX4:
770 case REG_ESAI_TX5:
771 case REG_ESAI_TSR:
772 case REG_ESAI_SAICR:
773 case REG_ESAI_TCR:
774 case REG_ESAI_TCCR:
775 case REG_ESAI_RCR:
776 case REG_ESAI_RCCR:
777 case REG_ESAI_TSMA:
778 case REG_ESAI_TSMB:
779 case REG_ESAI_RSMA:
780 case REG_ESAI_RSMB:
781 case REG_ESAI_PRRC:
782 case REG_ESAI_PCRC:
783 return true;
784 default:
785 return false;
786 }
787 }
788
789 static const struct regmap_config fsl_esai_regmap_config = {
790 .reg_bits = 32,
791 .reg_stride = 4,
792 .val_bits = 32,
793
794 .max_register = REG_ESAI_PCRC,
795 .reg_defaults = fsl_esai_reg_defaults,
796 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults),
797 .readable_reg = fsl_esai_readable_reg,
798 .volatile_reg = fsl_esai_volatile_reg,
799 .writeable_reg = fsl_esai_writeable_reg,
800 .cache_type = REGCACHE_RBTREE,
801 };
802
fsl_esai_probe(struct platform_device * pdev)803 static int fsl_esai_probe(struct platform_device *pdev)
804 {
805 struct device_node *np = pdev->dev.of_node;
806 struct fsl_esai *esai_priv;
807 struct resource *res;
808 const uint32_t *iprop;
809 void __iomem *regs;
810 int irq, ret;
811
812 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
813 if (!esai_priv)
814 return -ENOMEM;
815
816 esai_priv->pdev = pdev;
817 strncpy(esai_priv->name, np->name, sizeof(esai_priv->name) - 1);
818
819 /* Get the addresses and IRQ */
820 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
821 regs = devm_ioremap_resource(&pdev->dev, res);
822 if (IS_ERR(regs))
823 return PTR_ERR(regs);
824
825 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
826 "core", regs, &fsl_esai_regmap_config);
827 if (IS_ERR(esai_priv->regmap)) {
828 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
829 PTR_ERR(esai_priv->regmap));
830 return PTR_ERR(esai_priv->regmap);
831 }
832
833 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
834 if (IS_ERR(esai_priv->coreclk)) {
835 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
836 PTR_ERR(esai_priv->coreclk));
837 return PTR_ERR(esai_priv->coreclk);
838 }
839
840 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
841 if (IS_ERR(esai_priv->extalclk))
842 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
843 PTR_ERR(esai_priv->extalclk));
844
845 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
846 if (IS_ERR(esai_priv->fsysclk))
847 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
848 PTR_ERR(esai_priv->fsysclk));
849
850 irq = platform_get_irq(pdev, 0);
851 if (irq < 0) {
852 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
853 return irq;
854 }
855
856 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
857 esai_priv->name, esai_priv);
858 if (ret) {
859 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
860 return ret;
861 }
862
863 /* Set a default slot number */
864 esai_priv->slots = 2;
865
866 /* Set a default master/slave state */
867 esai_priv->slave_mode = true;
868
869 /* Determine the FIFO depth */
870 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
871 if (iprop)
872 esai_priv->fifo_depth = be32_to_cpup(iprop);
873 else
874 esai_priv->fifo_depth = 64;
875
876 esai_priv->dma_params_tx.maxburst = 16;
877 esai_priv->dma_params_rx.maxburst = 16;
878 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
879 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
880
881 esai_priv->synchronous =
882 of_property_read_bool(np, "fsl,esai-synchronous");
883
884 /* Implement full symmetry for synchronous mode */
885 if (esai_priv->synchronous) {
886 fsl_esai_dai.symmetric_rates = 1;
887 fsl_esai_dai.symmetric_channels = 1;
888 fsl_esai_dai.symmetric_samplebits = 1;
889 }
890
891 dev_set_drvdata(&pdev->dev, esai_priv);
892
893 /* Reset ESAI unit */
894 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
895 if (ret) {
896 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
897 return ret;
898 }
899
900 /*
901 * We need to enable ESAI so as to access some of its registers.
902 * Otherwise, we would fail to dump regmap from user space.
903 */
904 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
905 if (ret) {
906 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
907 return ret;
908 }
909
910 esai_priv->tx_mask = 0xFFFFFFFF;
911 esai_priv->rx_mask = 0xFFFFFFFF;
912
913 /* Clear the TSMA, TSMB, RSMA, RSMB */
914 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);
915 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);
916 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);
917 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);
918
919 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
920 &fsl_esai_dai, 1);
921 if (ret) {
922 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
923 return ret;
924 }
925
926 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
927 if (ret)
928 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
929
930 return ret;
931 }
932
933 static const struct of_device_id fsl_esai_dt_ids[] = {
934 { .compatible = "fsl,imx35-esai", },
935 { .compatible = "fsl,vf610-esai", },
936 {}
937 };
938 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
939
940 #ifdef CONFIG_PM_SLEEP
fsl_esai_suspend(struct device * dev)941 static int fsl_esai_suspend(struct device *dev)
942 {
943 struct fsl_esai *esai = dev_get_drvdata(dev);
944
945 regcache_cache_only(esai->regmap, true);
946 regcache_mark_dirty(esai->regmap);
947
948 return 0;
949 }
950
fsl_esai_resume(struct device * dev)951 static int fsl_esai_resume(struct device *dev)
952 {
953 struct fsl_esai *esai = dev_get_drvdata(dev);
954 int ret;
955
956 regcache_cache_only(esai->regmap, false);
957
958 /* FIFO reset for safety */
959 regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
960 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
961 regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
962 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
963
964 ret = regcache_sync(esai->regmap);
965 if (ret)
966 return ret;
967
968 /* FIFO reset done */
969 regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
970 regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
971
972 return 0;
973 }
974 #endif /* CONFIG_PM_SLEEP */
975
976 static const struct dev_pm_ops fsl_esai_pm_ops = {
977 SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume)
978 };
979
980 static struct platform_driver fsl_esai_driver = {
981 .probe = fsl_esai_probe,
982 .driver = {
983 .name = "fsl-esai-dai",
984 .pm = &fsl_esai_pm_ops,
985 .of_match_table = fsl_esai_dt_ids,
986 },
987 };
988
989 module_platform_driver(fsl_esai_driver);
990
991 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
992 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
993 MODULE_LICENSE("GPL v2");
994 MODULE_ALIAS("platform:fsl-esai-dai");
995