1 /*
2 * Intel Baytrail SST DSP driver
3 * Copyright (c) 2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/fs.h>
17 #include <linux/slab.h>
18 #include <linux/device.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/platform_device.h>
23 #include <linux/firmware.h>
24
25 #include "../common/sst-dsp.h"
26 #include "../common/sst-dsp-priv.h"
27 #include "sst-baytrail-ipc.h"
28
29 #define SST_BYT_FW_SIGNATURE_SIZE 4
30 #define SST_BYT_FW_SIGN "$SST"
31
32 #define SST_BYT_IRAM_OFFSET 0xC0000
33 #define SST_BYT_DRAM_OFFSET 0x100000
34 #define SST_BYT_SHIM_OFFSET 0x140000
35
36 enum sst_ram_type {
37 SST_BYT_IRAM = 1,
38 SST_BYT_DRAM = 2,
39 SST_BYT_CACHE = 3,
40 };
41
42 struct dma_block_info {
43 enum sst_ram_type type; /* IRAM/DRAM */
44 u32 size; /* Bytes */
45 u32 ram_offset; /* Offset in I/DRAM */
46 u32 rsvd; /* Reserved field */
47 };
48
49 struct fw_header {
50 unsigned char signature[SST_BYT_FW_SIGNATURE_SIZE];
51 u32 file_size; /* size of fw minus this header */
52 u32 modules; /* # of modules */
53 u32 file_format; /* version of header format */
54 u32 reserved[4];
55 };
56
57 struct sst_byt_fw_module_header {
58 unsigned char signature[SST_BYT_FW_SIGNATURE_SIZE];
59 u32 mod_size; /* size of module */
60 u32 blocks; /* # of blocks */
61 u32 type; /* codec type, pp lib */
62 u32 entry_point;
63 };
64
sst_byt_parse_module(struct sst_dsp * dsp,struct sst_fw * fw,struct sst_byt_fw_module_header * module)65 static int sst_byt_parse_module(struct sst_dsp *dsp, struct sst_fw *fw,
66 struct sst_byt_fw_module_header *module)
67 {
68 struct dma_block_info *block;
69 struct sst_module *mod;
70 struct sst_module_template template;
71 int count;
72
73 memset(&template, 0, sizeof(template));
74 template.id = module->type;
75 template.entry = module->entry_point;
76
77 mod = sst_module_new(fw, &template, NULL);
78 if (mod == NULL)
79 return -ENOMEM;
80
81 block = (void *)module + sizeof(*module);
82
83 for (count = 0; count < module->blocks; count++) {
84
85 if (block->size <= 0) {
86 dev_err(dsp->dev, "block %d size invalid\n", count);
87 return -EINVAL;
88 }
89
90 switch (block->type) {
91 case SST_BYT_IRAM:
92 mod->offset = block->ram_offset +
93 dsp->addr.iram_offset;
94 mod->type = SST_MEM_IRAM;
95 break;
96 case SST_BYT_DRAM:
97 mod->offset = block->ram_offset +
98 dsp->addr.dram_offset;
99 mod->type = SST_MEM_DRAM;
100 break;
101 case SST_BYT_CACHE:
102 mod->offset = block->ram_offset +
103 (dsp->addr.fw_ext - dsp->addr.lpe);
104 mod->type = SST_MEM_CACHE;
105 break;
106 default:
107 dev_err(dsp->dev, "wrong ram type 0x%x in block0x%x\n",
108 block->type, count);
109 return -EINVAL;
110 }
111
112 mod->size = block->size;
113 mod->data = (void *)block + sizeof(*block);
114
115 sst_module_alloc_blocks(mod);
116
117 block = (void *)block + sizeof(*block) + block->size;
118 }
119 return 0;
120 }
121
sst_byt_parse_fw_image(struct sst_fw * sst_fw)122 static int sst_byt_parse_fw_image(struct sst_fw *sst_fw)
123 {
124 struct fw_header *header;
125 struct sst_byt_fw_module_header *module;
126 struct sst_dsp *dsp = sst_fw->dsp;
127 int ret, count;
128
129 /* Read the header information from the data pointer */
130 header = (struct fw_header *)sst_fw->dma_buf;
131
132 /* verify FW */
133 if ((strncmp(header->signature, SST_BYT_FW_SIGN, 4) != 0) ||
134 (sst_fw->size != header->file_size + sizeof(*header))) {
135 /* Invalid FW signature */
136 dev_err(dsp->dev, "Invalid FW sign/filesize mismatch\n");
137 return -EINVAL;
138 }
139
140 dev_dbg(dsp->dev,
141 "header sign=%4s size=0x%x modules=0x%x fmt=0x%x size=%zu\n",
142 header->signature, header->file_size, header->modules,
143 header->file_format, sizeof(*header));
144
145 module = (void *)sst_fw->dma_buf + sizeof(*header);
146 for (count = 0; count < header->modules; count++) {
147 /* module */
148 ret = sst_byt_parse_module(dsp, sst_fw, module);
149 if (ret < 0) {
150 dev_err(dsp->dev, "invalid module %d\n", count);
151 return ret;
152 }
153 module = (void *)module + sizeof(*module) + module->mod_size;
154 }
155
156 return 0;
157 }
158
sst_byt_dump_shim(struct sst_dsp * sst)159 static void sst_byt_dump_shim(struct sst_dsp *sst)
160 {
161 int i;
162 u64 reg;
163
164 for (i = 0; i <= 0xF0; i += 8) {
165 reg = sst_dsp_shim_read64_unlocked(sst, i);
166 if (reg)
167 dev_dbg(sst->dev, "shim 0x%2.2x value 0x%16.16llx\n",
168 i, reg);
169 }
170
171 for (i = 0x00; i <= 0xff; i += 4) {
172 reg = readl(sst->addr.pci_cfg + i);
173 if (reg)
174 dev_dbg(sst->dev, "pci 0x%2.2x value 0x%8.8x\n",
175 i, (u32)reg);
176 }
177 }
178
sst_byt_irq(int irq,void * context)179 static irqreturn_t sst_byt_irq(int irq, void *context)
180 {
181 struct sst_dsp *sst = (struct sst_dsp *) context;
182 u64 isrx;
183 irqreturn_t ret = IRQ_NONE;
184
185 spin_lock(&sst->spinlock);
186
187 isrx = sst_dsp_shim_read64_unlocked(sst, SST_ISRX);
188 if (isrx & SST_ISRX_DONE) {
189 /* ADSP has processed the message request from IA */
190 sst_dsp_shim_update_bits64_unlocked(sst, SST_IPCX,
191 SST_BYT_IPCX_DONE, 0);
192 ret = IRQ_WAKE_THREAD;
193 }
194 if (isrx & SST_BYT_ISRX_REQUEST) {
195 /* mask message request from ADSP and do processing later */
196 sst_dsp_shim_update_bits64_unlocked(sst, SST_IMRX,
197 SST_BYT_IMRX_REQUEST,
198 SST_BYT_IMRX_REQUEST);
199 ret = IRQ_WAKE_THREAD;
200 }
201
202 spin_unlock(&sst->spinlock);
203
204 return ret;
205 }
206
sst_byt_boot(struct sst_dsp * sst)207 static void sst_byt_boot(struct sst_dsp *sst)
208 {
209 int tries = 10;
210
211 /*
212 * save the physical address of extended firmware block in the first
213 * 4 bytes of the mailbox
214 */
215 memcpy_toio(sst->addr.lpe + SST_BYT_MAILBOX_OFFSET,
216 &sst->pdata->fw_base, sizeof(u32));
217
218 /* release stall and wait to unstall */
219 sst_dsp_shim_update_bits64(sst, SST_CSR, SST_BYT_CSR_STALL, 0x0);
220 while (tries--) {
221 if (!(sst_dsp_shim_read64(sst, SST_CSR) &
222 SST_BYT_CSR_PWAITMODE))
223 break;
224 msleep(100);
225 }
226 if (tries < 0) {
227 dev_err(sst->dev, "unable to start DSP\n");
228 sst_byt_dump_shim(sst);
229 }
230 }
231
sst_byt_reset(struct sst_dsp * sst)232 static void sst_byt_reset(struct sst_dsp *sst)
233 {
234 /* put DSP into reset, set reset vector and stall */
235 sst_dsp_shim_update_bits64(sst, SST_CSR,
236 SST_BYT_CSR_RST | SST_BYT_CSR_VECTOR_SEL | SST_BYT_CSR_STALL,
237 SST_BYT_CSR_RST | SST_BYT_CSR_VECTOR_SEL | SST_BYT_CSR_STALL);
238
239 udelay(10);
240
241 /* take DSP out of reset and keep stalled for FW loading */
242 sst_dsp_shim_update_bits64(sst, SST_CSR, SST_BYT_CSR_RST, 0);
243 }
244
245 struct sst_adsp_memregion {
246 u32 start;
247 u32 end;
248 int blocks;
249 enum sst_mem_type type;
250 };
251
252 /* BYT test stuff */
253 static const struct sst_adsp_memregion byt_region[] = {
254 {0xC0000, 0x100000, 8, SST_MEM_IRAM}, /* I-SRAM - 8 * 32kB */
255 {0x100000, 0x140000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
256 };
257
sst_byt_resource_map(struct sst_dsp * sst,struct sst_pdata * pdata)258 static int sst_byt_resource_map(struct sst_dsp *sst, struct sst_pdata *pdata)
259 {
260 sst->addr.lpe_base = pdata->lpe_base;
261 sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);
262 if (!sst->addr.lpe)
263 return -ENODEV;
264
265 /* ADSP PCI MMIO config space */
266 sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);
267 if (!sst->addr.pci_cfg) {
268 iounmap(sst->addr.lpe);
269 return -ENODEV;
270 }
271
272 /* SST Extended FW allocation */
273 sst->addr.fw_ext = ioremap(pdata->fw_base, pdata->fw_size);
274 if (!sst->addr.fw_ext) {
275 iounmap(sst->addr.pci_cfg);
276 iounmap(sst->addr.lpe);
277 return -ENODEV;
278 }
279
280 /* SST Shim */
281 sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;
282
283 sst_dsp_mailbox_init(sst, SST_BYT_MAILBOX_OFFSET + 0x204,
284 SST_BYT_IPC_MAX_PAYLOAD_SIZE,
285 SST_BYT_MAILBOX_OFFSET,
286 SST_BYT_IPC_MAX_PAYLOAD_SIZE);
287
288 sst->irq = pdata->irq;
289
290 return 0;
291 }
292
sst_byt_init(struct sst_dsp * sst,struct sst_pdata * pdata)293 static int sst_byt_init(struct sst_dsp *sst, struct sst_pdata *pdata)
294 {
295 const struct sst_adsp_memregion *region;
296 struct device *dev;
297 int ret = -ENODEV, i, j, region_count;
298 u32 offset, size;
299
300 dev = sst->dev;
301
302 switch (sst->id) {
303 case SST_DEV_ID_BYT:
304 region = byt_region;
305 region_count = ARRAY_SIZE(byt_region);
306 sst->addr.iram_offset = SST_BYT_IRAM_OFFSET;
307 sst->addr.dram_offset = SST_BYT_DRAM_OFFSET;
308 sst->addr.shim_offset = SST_BYT_SHIM_OFFSET;
309 break;
310 default:
311 dev_err(dev, "failed to get mem resources\n");
312 return ret;
313 }
314
315 ret = sst_byt_resource_map(sst, pdata);
316 if (ret < 0) {
317 dev_err(dev, "failed to map resources\n");
318 return ret;
319 }
320
321 ret = dma_coerce_mask_and_coherent(sst->dma_dev, DMA_BIT_MASK(32));
322 if (ret)
323 return ret;
324
325 /* enable Interrupt from both sides */
326 sst_dsp_shim_update_bits64(sst, SST_IMRX, 0x3, 0x0);
327 sst_dsp_shim_update_bits64(sst, SST_IMRD, 0x3, 0x0);
328
329 /* register DSP memory blocks - ideally we should get this from ACPI */
330 for (i = 0; i < region_count; i++) {
331 offset = region[i].start;
332 size = (region[i].end - region[i].start) / region[i].blocks;
333
334 /* register individual memory blocks */
335 for (j = 0; j < region[i].blocks; j++) {
336 sst_mem_block_register(sst, offset, size,
337 region[i].type, NULL, j, sst);
338 offset += size;
339 }
340 }
341
342 return 0;
343 }
344
sst_byt_free(struct sst_dsp * sst)345 static void sst_byt_free(struct sst_dsp *sst)
346 {
347 sst_mem_block_unregister_all(sst);
348 iounmap(sst->addr.lpe);
349 iounmap(sst->addr.pci_cfg);
350 iounmap(sst->addr.fw_ext);
351 }
352
353 struct sst_ops sst_byt_ops = {
354 .reset = sst_byt_reset,
355 .boot = sst_byt_boot,
356 .write = sst_shim32_write,
357 .read = sst_shim32_read,
358 .write64 = sst_shim32_write64,
359 .read64 = sst_shim32_read64,
360 .ram_read = sst_memcpy_fromio_32,
361 .ram_write = sst_memcpy_toio_32,
362 .irq_handler = sst_byt_irq,
363 .init = sst_byt_init,
364 .free = sst_byt_free,
365 .parse_fw = sst_byt_parse_fw_image,
366 };
367