1 /*
2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * Derived mostly from Intel HDA driver with following copyrights:
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
22 */
23
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/platform_device.h>
28 #include <linux/firmware.h>
29 #include <sound/pcm.h>
30 #include "skl.h"
31
32 /*
33 * initialize the PCI registers
34 */
skl_update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)35 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
36 unsigned char mask, unsigned char val)
37 {
38 unsigned char data;
39
40 pci_read_config_byte(pci, reg, &data);
41 data &= ~mask;
42 data |= (val & mask);
43 pci_write_config_byte(pci, reg, data);
44 }
45
skl_init_pci(struct skl * skl)46 static void skl_init_pci(struct skl *skl)
47 {
48 struct hdac_ext_bus *ebus = &skl->ebus;
49
50 /*
51 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
52 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
53 * Ensuring these bits are 0 clears playback static on some HD Audio
54 * codecs.
55 * The PCI register TCSEL is defined in the Intel manuals.
56 */
57 dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n");
58 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
59 }
60
61 /* called from IRQ */
skl_stream_update(struct hdac_bus * bus,struct hdac_stream * hstr)62 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
63 {
64 snd_pcm_period_elapsed(hstr->substream);
65 }
66
skl_interrupt(int irq,void * dev_id)67 static irqreturn_t skl_interrupt(int irq, void *dev_id)
68 {
69 struct hdac_ext_bus *ebus = dev_id;
70 struct hdac_bus *bus = ebus_to_hbus(ebus);
71 u32 status;
72
73 if (!pm_runtime_active(bus->dev))
74 return IRQ_NONE;
75
76 spin_lock(&bus->reg_lock);
77
78 status = snd_hdac_chip_readl(bus, INTSTS);
79 if (status == 0 || status == 0xffffffff) {
80 spin_unlock(&bus->reg_lock);
81 return IRQ_NONE;
82 }
83
84 /* clear rirb int */
85 status = snd_hdac_chip_readb(bus, RIRBSTS);
86 if (status & RIRB_INT_MASK) {
87 if (status & RIRB_INT_RESPONSE)
88 snd_hdac_bus_update_rirb(bus);
89 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
90 }
91
92 spin_unlock(&bus->reg_lock);
93
94 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
95 }
96
skl_threaded_handler(int irq,void * dev_id)97 static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
98 {
99 struct hdac_ext_bus *ebus = dev_id;
100 struct hdac_bus *bus = ebus_to_hbus(ebus);
101 u32 status;
102
103 status = snd_hdac_chip_readl(bus, INTSTS);
104
105 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
106
107 return IRQ_HANDLED;
108 }
109
skl_acquire_irq(struct hdac_ext_bus * ebus,int do_disconnect)110 static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect)
111 {
112 struct skl *skl = ebus_to_skl(ebus);
113 struct hdac_bus *bus = ebus_to_hbus(ebus);
114 int ret;
115
116 ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
117 skl_threaded_handler,
118 IRQF_SHARED,
119 KBUILD_MODNAME, ebus);
120 if (ret) {
121 dev_err(bus->dev,
122 "unable to grab IRQ %d, disabling device\n",
123 skl->pci->irq);
124 return ret;
125 }
126
127 bus->irq = skl->pci->irq;
128 pci_intx(skl->pci, 1);
129
130 return 0;
131 }
132
133 #ifdef CONFIG_PM_SLEEP
134 /*
135 * power management
136 */
skl_suspend(struct device * dev)137 static int skl_suspend(struct device *dev)
138 {
139 struct pci_dev *pci = to_pci_dev(dev);
140 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
141 struct hdac_bus *bus = ebus_to_hbus(ebus);
142
143 snd_hdac_bus_stop_chip(bus);
144 snd_hdac_bus_enter_link_reset(bus);
145
146 return 0;
147 }
148
skl_resume(struct device * dev)149 static int skl_resume(struct device *dev)
150 {
151 struct pci_dev *pci = to_pci_dev(dev);
152 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
153 struct hdac_bus *bus = ebus_to_hbus(ebus);
154 struct skl *hda = ebus_to_skl(ebus);
155
156 skl_init_pci(hda);
157
158 snd_hdac_bus_init_chip(bus, 1);
159
160 return 0;
161 }
162 #endif /* CONFIG_PM_SLEEP */
163
164 #ifdef CONFIG_PM
skl_runtime_suspend(struct device * dev)165 static int skl_runtime_suspend(struct device *dev)
166 {
167 struct pci_dev *pci = to_pci_dev(dev);
168 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
169 struct hdac_bus *bus = ebus_to_hbus(ebus);
170 struct skl *skl = ebus_to_skl(ebus);
171 int ret;
172
173 dev_dbg(bus->dev, "in %s\n", __func__);
174
175 /* enable controller wake up event */
176 snd_hdac_chip_updatew(bus, WAKEEN, 0, STATESTS_INT_MASK);
177
178 snd_hdac_ext_bus_link_power_down_all(ebus);
179
180 ret = skl_suspend_dsp(skl);
181 if (ret < 0)
182 return ret;
183
184 snd_hdac_bus_stop_chip(bus);
185 snd_hdac_bus_enter_link_reset(bus);
186
187 return 0;
188 }
189
skl_runtime_resume(struct device * dev)190 static int skl_runtime_resume(struct device *dev)
191 {
192 struct pci_dev *pci = to_pci_dev(dev);
193 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
194 struct hdac_bus *bus = ebus_to_hbus(ebus);
195 struct skl *skl = ebus_to_skl(ebus);
196 int status;
197
198 dev_dbg(bus->dev, "in %s\n", __func__);
199
200 /* Read STATESTS before controller reset */
201 status = snd_hdac_chip_readw(bus, STATESTS);
202
203 skl_init_pci(skl);
204 snd_hdac_bus_init_chip(bus, true);
205 /* disable controller Wake Up event */
206 snd_hdac_chip_updatew(bus, WAKEEN, STATESTS_INT_MASK, 0);
207
208 return skl_resume_dsp(skl);
209 }
210 #endif /* CONFIG_PM */
211
212 static const struct dev_pm_ops skl_pm = {
213 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
214 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
215 };
216
217 /*
218 * destructor
219 */
skl_free(struct hdac_ext_bus * ebus)220 static int skl_free(struct hdac_ext_bus *ebus)
221 {
222 struct skl *skl = ebus_to_skl(ebus);
223 struct hdac_bus *bus = ebus_to_hbus(ebus);
224
225 skl->init_failed = 1; /* to be sure */
226
227 snd_hdac_ext_stop_streams(ebus);
228
229 if (bus->irq >= 0)
230 free_irq(bus->irq, (void *)bus);
231 if (bus->remap_addr)
232 iounmap(bus->remap_addr);
233
234 snd_hdac_bus_free_stream_pages(bus);
235 snd_hdac_stream_free_all(ebus);
236 snd_hdac_link_free_all(ebus);
237 pci_release_regions(skl->pci);
238 pci_disable_device(skl->pci);
239
240 snd_hdac_ext_bus_exit(ebus);
241
242 return 0;
243 }
244
skl_dmic_device_register(struct skl * skl)245 static int skl_dmic_device_register(struct skl *skl)
246 {
247 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus);
248 struct platform_device *pdev;
249 int ret;
250
251 /* SKL has one dmic port, so allocate dmic device for this */
252 pdev = platform_device_alloc("dmic-codec", -1);
253 if (!pdev) {
254 dev_err(bus->dev, "failed to allocate dmic device\n");
255 return -ENOMEM;
256 }
257
258 ret = platform_device_add(pdev);
259 if (ret) {
260 dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
261 platform_device_put(pdev);
262 return ret;
263 }
264 skl->dmic_dev = pdev;
265
266 return 0;
267 }
268
skl_dmic_device_unregister(struct skl * skl)269 static void skl_dmic_device_unregister(struct skl *skl)
270 {
271 if (skl->dmic_dev)
272 platform_device_unregister(skl->dmic_dev);
273 }
274
275 /*
276 * Probe the given codec address
277 */
probe_codec(struct hdac_ext_bus * ebus,int addr)278 static int probe_codec(struct hdac_ext_bus *ebus, int addr)
279 {
280 struct hdac_bus *bus = ebus_to_hbus(ebus);
281 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
282 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
283 unsigned int res = -1;
284
285 mutex_lock(&bus->cmd_mutex);
286 snd_hdac_bus_send_cmd(bus, cmd);
287 snd_hdac_bus_get_response(bus, addr, &res);
288 mutex_unlock(&bus->cmd_mutex);
289 if (res == -1)
290 return -EIO;
291 dev_dbg(bus->dev, "codec #%d probed OK\n", addr);
292
293 return snd_hdac_ext_bus_device_init(ebus, addr);
294 }
295
296 /* Codec initialization */
skl_codec_create(struct hdac_ext_bus * ebus)297 static int skl_codec_create(struct hdac_ext_bus *ebus)
298 {
299 struct hdac_bus *bus = ebus_to_hbus(ebus);
300 int c, max_slots;
301
302 max_slots = HDA_MAX_CODECS;
303
304 /* First try to probe all given codec slots */
305 for (c = 0; c < max_slots; c++) {
306 if ((bus->codec_mask & (1 << c))) {
307 if (probe_codec(ebus, c) < 0) {
308 /*
309 * Some BIOSen give you wrong codec addresses
310 * that don't exist
311 */
312 dev_warn(bus->dev,
313 "Codec #%d probe error; disabling it...\n", c);
314 bus->codec_mask &= ~(1 << c);
315 /*
316 * More badly, accessing to a non-existing
317 * codec often screws up the controller bus,
318 * and disturbs the further communications.
319 * Thus if an error occurs during probing,
320 * better to reset the controller bus to get
321 * back to the sanity state.
322 */
323 snd_hdac_bus_stop_chip(bus);
324 snd_hdac_bus_init_chip(bus, true);
325 }
326 }
327 }
328
329 return 0;
330 }
331
332 static const struct hdac_bus_ops bus_core_ops = {
333 .command = snd_hdac_bus_send_cmd,
334 .get_response = snd_hdac_bus_get_response,
335 };
336
337 /*
338 * constructor
339 */
skl_create(struct pci_dev * pci,const struct hdac_io_ops * io_ops,struct skl ** rskl)340 static int skl_create(struct pci_dev *pci,
341 const struct hdac_io_ops *io_ops,
342 struct skl **rskl)
343 {
344 struct skl *skl;
345 struct hdac_ext_bus *ebus;
346
347 int err;
348
349 *rskl = NULL;
350
351 err = pci_enable_device(pci);
352 if (err < 0)
353 return err;
354
355 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
356 if (!skl) {
357 pci_disable_device(pci);
358 return -ENOMEM;
359 }
360 ebus = &skl->ebus;
361 snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops);
362 ebus->bus.use_posbuf = 1;
363 skl->pci = pci;
364
365 ebus->bus.bdl_pos_adj = 0;
366
367 *rskl = skl;
368
369 return 0;
370 }
371
skl_first_init(struct hdac_ext_bus * ebus)372 static int skl_first_init(struct hdac_ext_bus *ebus)
373 {
374 struct skl *skl = ebus_to_skl(ebus);
375 struct hdac_bus *bus = ebus_to_hbus(ebus);
376 struct pci_dev *pci = skl->pci;
377 int err;
378 unsigned short gcap;
379 int cp_streams, pb_streams, start_idx;
380
381 err = pci_request_regions(pci, "Skylake HD audio");
382 if (err < 0)
383 return err;
384
385 bus->addr = pci_resource_start(pci, 0);
386 bus->remap_addr = pci_ioremap_bar(pci, 0);
387 if (bus->remap_addr == NULL) {
388 dev_err(bus->dev, "ioremap error\n");
389 return -ENXIO;
390 }
391
392 snd_hdac_ext_bus_parse_capabilities(ebus);
393
394 if (skl_acquire_irq(ebus, 0) < 0)
395 return -EBUSY;
396
397 pci_set_master(pci);
398 synchronize_irq(bus->irq);
399
400 gcap = snd_hdac_chip_readw(bus, GCAP);
401 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
402
403 /* allow 64bit DMA address if supported by H/W */
404 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) {
405 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64));
406 } else {
407 dma_set_mask(bus->dev, DMA_BIT_MASK(32));
408 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32));
409 }
410
411 /* read number of streams from GCAP register */
412 cp_streams = (gcap >> 8) & 0x0f;
413 pb_streams = (gcap >> 12) & 0x0f;
414
415 if (!pb_streams && !cp_streams)
416 return -EIO;
417
418 ebus->num_streams = cp_streams + pb_streams;
419
420 /* initialize streams */
421 snd_hdac_ext_stream_init_all
422 (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
423 start_idx = cp_streams;
424 snd_hdac_ext_stream_init_all
425 (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
426
427 err = snd_hdac_bus_alloc_stream_pages(bus);
428 if (err < 0)
429 return err;
430
431 /* initialize chip */
432 skl_init_pci(skl);
433
434 snd_hdac_bus_init_chip(bus, true);
435
436 /* codec detection */
437 if (!bus->codec_mask) {
438 dev_err(bus->dev, "no codecs found!\n");
439 return -ENODEV;
440 }
441
442 return 0;
443 }
444
skl_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)445 static int skl_probe(struct pci_dev *pci,
446 const struct pci_device_id *pci_id)
447 {
448 struct skl *skl;
449 struct hdac_ext_bus *ebus = NULL;
450 struct hdac_bus *bus = NULL;
451 int err;
452
453 /* we use ext core ops, so provide NULL for ops here */
454 err = skl_create(pci, NULL, &skl);
455 if (err < 0)
456 return err;
457
458 ebus = &skl->ebus;
459 bus = ebus_to_hbus(ebus);
460
461 err = skl_first_init(ebus);
462 if (err < 0)
463 goto out_free;
464
465 skl->nhlt = skl_nhlt_init(bus->dev);
466
467 if (skl->nhlt == NULL) {
468 err = -ENODEV;
469 goto out_free;
470 }
471
472 pci_set_drvdata(skl->pci, ebus);
473
474 /* check if dsp is there */
475 if (ebus->ppcap) {
476 err = skl_init_dsp(skl);
477 if (err < 0) {
478 dev_dbg(bus->dev, "error failed to register dsp\n");
479 goto out_free;
480 }
481 }
482 if (ebus->mlcap)
483 snd_hdac_ext_bus_get_ml_capabilities(ebus);
484
485 /* create device for soc dmic */
486 err = skl_dmic_device_register(skl);
487 if (err < 0)
488 goto out_dsp_free;
489
490 /* register platform dai and controls */
491 err = skl_platform_register(bus->dev);
492 if (err < 0)
493 goto out_dmic_free;
494
495 /* create codec instances */
496 err = skl_codec_create(ebus);
497 if (err < 0)
498 goto out_unregister;
499
500 /*configure PM */
501 pm_runtime_set_autosuspend_delay(bus->dev, SKL_SUSPEND_DELAY);
502 pm_runtime_use_autosuspend(bus->dev);
503 pm_runtime_put_noidle(bus->dev);
504 pm_runtime_allow(bus->dev);
505
506 return 0;
507
508 out_unregister:
509 skl_platform_unregister(bus->dev);
510 out_dmic_free:
511 skl_dmic_device_unregister(skl);
512 out_dsp_free:
513 skl_free_dsp(skl);
514 out_free:
515 skl->init_failed = 1;
516 skl_free(ebus);
517
518 return err;
519 }
520
skl_remove(struct pci_dev * pci)521 static void skl_remove(struct pci_dev *pci)
522 {
523 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
524 struct skl *skl = ebus_to_skl(ebus);
525
526 if (skl->tplg)
527 release_firmware(skl->tplg);
528
529 if (pci_dev_run_wake(pci))
530 pm_runtime_get_noresume(&pci->dev);
531 pci_dev_put(pci);
532 skl_platform_unregister(&pci->dev);
533 skl_free_dsp(skl);
534 skl_dmic_device_unregister(skl);
535 skl_free(ebus);
536 dev_set_drvdata(&pci->dev, NULL);
537 }
538
539 /* PCI IDs */
540 static const struct pci_device_id skl_ids[] = {
541 /* Sunrise Point-LP */
542 { PCI_DEVICE(0x8086, 0x9d70), 0},
543 { 0, }
544 };
545 MODULE_DEVICE_TABLE(pci, skl_ids);
546
547 /* pci_driver definition */
548 static struct pci_driver skl_driver = {
549 .name = KBUILD_MODNAME,
550 .id_table = skl_ids,
551 .probe = skl_probe,
552 .remove = skl_remove,
553 .driver = {
554 .pm = &skl_pm,
555 },
556 };
557 module_pci_driver(skl_driver);
558
559 MODULE_LICENSE("GPL v2");
560 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");
561