1 /*
2 * Mediatek ALSA SoC AFE platform driver
3 *
4 * Copyright (c) 2015 MediaTek Inc.
5 * Author: Koro Chen <koro.chen@mediatek.com>
6 * Sascha Hauer <s.hauer@pengutronix.de>
7 * Hidalgo Huang <hidalgo.huang@mediatek.com>
8 * Ir Lian <ir.lian@mediatek.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 and
12 * only version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/pm_runtime.h>
25 #include <sound/soc.h>
26 #include "mtk-afe-common.h"
27
28 /*****************************************************************************
29 * R E G I S T E R D E F I N I T I O N
30 *****************************************************************************/
31 #define AUDIO_TOP_CON0 0x0000
32 #define AUDIO_TOP_CON1 0x0004
33 #define AFE_DAC_CON0 0x0010
34 #define AFE_DAC_CON1 0x0014
35 #define AFE_I2S_CON1 0x0034
36 #define AFE_I2S_CON2 0x0038
37 #define AFE_CONN_24BIT 0x006c
38
39 #define AFE_CONN1 0x0024
40 #define AFE_CONN2 0x0028
41 #define AFE_CONN7 0x0460
42 #define AFE_CONN8 0x0464
43 #define AFE_HDMI_CONN0 0x0390
44
45 /* Memory interface */
46 #define AFE_DL1_BASE 0x0040
47 #define AFE_DL1_CUR 0x0044
48 #define AFE_DL1_END 0x0048
49 #define AFE_DL2_BASE 0x0050
50 #define AFE_DL2_CUR 0x0054
51 #define AFE_AWB_BASE 0x0070
52 #define AFE_AWB_CUR 0x007c
53 #define AFE_VUL_BASE 0x0080
54 #define AFE_VUL_CUR 0x008c
55 #define AFE_VUL_END 0x0088
56 #define AFE_DAI_BASE 0x0090
57 #define AFE_DAI_CUR 0x009c
58 #define AFE_MOD_PCM_BASE 0x0330
59 #define AFE_MOD_PCM_CUR 0x033c
60 #define AFE_HDMI_OUT_BASE 0x0374
61 #define AFE_HDMI_OUT_CUR 0x0378
62 #define AFE_HDMI_OUT_END 0x037c
63
64 #define AFE_ADDA2_TOP_CON0 0x0600
65
66 #define AFE_HDMI_OUT_CON0 0x0370
67
68 #define AFE_IRQ_MCU_CON 0x03a0
69 #define AFE_IRQ_STATUS 0x03a4
70 #define AFE_IRQ_CLR 0x03a8
71 #define AFE_IRQ_CNT1 0x03ac
72 #define AFE_IRQ_CNT2 0x03b0
73 #define AFE_IRQ_MCU_EN 0x03b4
74 #define AFE_IRQ_CNT5 0x03bc
75 #define AFE_IRQ_CNT7 0x03dc
76
77 #define AFE_TDM_CON1 0x0548
78 #define AFE_TDM_CON2 0x054c
79
80 #define AFE_BASE_END_OFFSET 8
81 #define AFE_IRQ_STATUS_BITS 0xff
82
83 /* AUDIO_TOP_CON0 (0x0000) */
84 #define AUD_TCON0_PDN_SPDF (0x1 << 21)
85 #define AUD_TCON0_PDN_HDMI (0x1 << 20)
86 #define AUD_TCON0_PDN_24M (0x1 << 9)
87 #define AUD_TCON0_PDN_22M (0x1 << 8)
88 #define AUD_TCON0_PDN_AFE (0x1 << 2)
89
90 /* AFE_I2S_CON1 (0x0034) */
91 #define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12)
92 #define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8)
93 #define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3)
94 #define AFE_I2S_CON1_EN (0x1 << 0)
95
96 /* AFE_I2S_CON2 (0x0038) */
97 #define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12)
98 #define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8)
99 #define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3)
100 #define AFE_I2S_CON2_EN (0x1 << 0)
101
102 /* AFE_CONN_24BIT (0x006c) */
103 #define AFE_CONN_24BIT_O04 (0x1 << 4)
104 #define AFE_CONN_24BIT_O03 (0x1 << 3)
105
106 /* AFE_HDMI_CONN0 (0x0390) */
107 #define AFE_HDMI_CONN0_O37_I37 (0x7 << 21)
108 #define AFE_HDMI_CONN0_O36_I36 (0x6 << 18)
109 #define AFE_HDMI_CONN0_O35_I33 (0x3 << 15)
110 #define AFE_HDMI_CONN0_O34_I32 (0x2 << 12)
111 #define AFE_HDMI_CONN0_O33_I35 (0x5 << 9)
112 #define AFE_HDMI_CONN0_O32_I34 (0x4 << 6)
113 #define AFE_HDMI_CONN0_O31_I31 (0x1 << 3)
114 #define AFE_HDMI_CONN0_O30_I30 (0x0 << 0)
115
116 /* AFE_TDM_CON1 (0x0548) */
117 #define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24)
118 #define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12)
119 #define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8)
120 #define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4)
121 #define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3)
122 #define AFE_TDM_CON1_BCK_INV (0x1 << 1)
123 #define AFE_TDM_CON1_EN (0x1 << 0)
124
125 enum afe_tdm_ch_start {
126 AFE_TDM_CH_START_O30_O31 = 0,
127 AFE_TDM_CH_START_O32_O33,
128 AFE_TDM_CH_START_O34_O35,
129 AFE_TDM_CH_START_O36_O37,
130 AFE_TDM_CH_ZERO,
131 };
132
133 static const unsigned int mtk_afe_backup_list[] = {
134 AUDIO_TOP_CON0,
135 AFE_CONN1,
136 AFE_CONN2,
137 AFE_CONN7,
138 AFE_CONN8,
139 AFE_DAC_CON1,
140 AFE_DL1_BASE,
141 AFE_DL1_END,
142 AFE_VUL_BASE,
143 AFE_VUL_END,
144 AFE_HDMI_OUT_BASE,
145 AFE_HDMI_OUT_END,
146 AFE_HDMI_CONN0,
147 AFE_DAC_CON0,
148 };
149
150 struct mtk_afe {
151 /* address for ioremap audio hardware register */
152 void __iomem *base_addr;
153 struct device *dev;
154 struct regmap *regmap;
155 struct mtk_afe_memif memif[MTK_AFE_MEMIF_NUM];
156 struct clk *clocks[MTK_CLK_NUM];
157 unsigned int backup_regs[ARRAY_SIZE(mtk_afe_backup_list)];
158 bool suspended;
159 };
160
161 static const struct snd_pcm_hardware mtk_afe_hardware = {
162 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
163 SNDRV_PCM_INFO_MMAP_VALID),
164 .buffer_bytes_max = 256 * 1024,
165 .period_bytes_min = 512,
166 .period_bytes_max = 128 * 1024,
167 .periods_min = 2,
168 .periods_max = 256,
169 .fifo_size = 0,
170 };
171
mtk_afe_pcm_pointer(struct snd_pcm_substream * substream)172 static snd_pcm_uframes_t mtk_afe_pcm_pointer
173 (struct snd_pcm_substream *substream)
174 {
175 struct snd_soc_pcm_runtime *rtd = substream->private_data;
176 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
177 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
178
179 return bytes_to_frames(substream->runtime, memif->hw_ptr);
180 }
181
182 static const struct snd_pcm_ops mtk_afe_pcm_ops = {
183 .ioctl = snd_pcm_lib_ioctl,
184 .pointer = mtk_afe_pcm_pointer,
185 };
186
mtk_afe_pcm_new(struct snd_soc_pcm_runtime * rtd)187 static int mtk_afe_pcm_new(struct snd_soc_pcm_runtime *rtd)
188 {
189 size_t size;
190 struct snd_card *card = rtd->card->snd_card;
191 struct snd_pcm *pcm = rtd->pcm;
192
193 size = mtk_afe_hardware.buffer_bytes_max;
194
195 return snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
196 card->dev, size, size);
197 }
198
mtk_afe_pcm_free(struct snd_pcm * pcm)199 static void mtk_afe_pcm_free(struct snd_pcm *pcm)
200 {
201 snd_pcm_lib_preallocate_free_for_all(pcm);
202 }
203
204 static const struct snd_soc_platform_driver mtk_afe_pcm_platform = {
205 .ops = &mtk_afe_pcm_ops,
206 .pcm_new = mtk_afe_pcm_new,
207 .pcm_free = mtk_afe_pcm_free,
208 };
209
210 struct mtk_afe_rate {
211 unsigned int rate;
212 unsigned int regvalue;
213 };
214
215 static const struct mtk_afe_rate mtk_afe_i2s_rates[] = {
216 { .rate = 8000, .regvalue = 0 },
217 { .rate = 11025, .regvalue = 1 },
218 { .rate = 12000, .regvalue = 2 },
219 { .rate = 16000, .regvalue = 4 },
220 { .rate = 22050, .regvalue = 5 },
221 { .rate = 24000, .regvalue = 6 },
222 { .rate = 32000, .regvalue = 8 },
223 { .rate = 44100, .regvalue = 9 },
224 { .rate = 48000, .regvalue = 10 },
225 { .rate = 88000, .regvalue = 11 },
226 { .rate = 96000, .regvalue = 12 },
227 { .rate = 174000, .regvalue = 13 },
228 { .rate = 192000, .regvalue = 14 },
229 };
230
mtk_afe_i2s_fs(unsigned int sample_rate)231 static int mtk_afe_i2s_fs(unsigned int sample_rate)
232 {
233 int i;
234
235 for (i = 0; i < ARRAY_SIZE(mtk_afe_i2s_rates); i++)
236 if (mtk_afe_i2s_rates[i].rate == sample_rate)
237 return mtk_afe_i2s_rates[i].regvalue;
238
239 return -EINVAL;
240 }
241
mtk_afe_set_i2s(struct mtk_afe * afe,unsigned int rate)242 static int mtk_afe_set_i2s(struct mtk_afe *afe, unsigned int rate)
243 {
244 unsigned int val;
245 int fs = mtk_afe_i2s_fs(rate);
246
247 if (fs < 0)
248 return -EINVAL;
249
250 /* from external ADC */
251 regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
252
253 /* set input */
254 val = AFE_I2S_CON2_LOW_JITTER_CLK |
255 AFE_I2S_CON2_RATE(fs) |
256 AFE_I2S_CON2_FORMAT_I2S;
257
258 regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
259
260 /* set output */
261 val = AFE_I2S_CON1_LOW_JITTER_CLK |
262 AFE_I2S_CON1_RATE(fs) |
263 AFE_I2S_CON1_FORMAT_I2S;
264
265 regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
266 return 0;
267 }
268
mtk_afe_set_i2s_enable(struct mtk_afe * afe,bool enable)269 static void mtk_afe_set_i2s_enable(struct mtk_afe *afe, bool enable)
270 {
271 unsigned int val;
272
273 regmap_read(afe->regmap, AFE_I2S_CON2, &val);
274 if (!!(val & AFE_I2S_CON2_EN) == enable)
275 return; /* must skip soft reset */
276
277 /* I2S soft reset begin */
278 regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0x4);
279
280 /* input */
281 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
282
283 /* output */
284 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
285
286 /* I2S soft reset end */
287 udelay(1);
288 regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0);
289 }
290
mtk_afe_dais_enable_clks(struct mtk_afe * afe,struct clk * m_ck,struct clk * b_ck)291 static int mtk_afe_dais_enable_clks(struct mtk_afe *afe,
292 struct clk *m_ck, struct clk *b_ck)
293 {
294 int ret;
295
296 if (m_ck) {
297 ret = clk_prepare_enable(m_ck);
298 if (ret) {
299 dev_err(afe->dev, "Failed to enable m_ck\n");
300 return ret;
301 }
302 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
303 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
304 }
305
306 if (b_ck) {
307 ret = clk_prepare_enable(b_ck);
308 if (ret) {
309 dev_err(afe->dev, "Failed to enable b_ck\n");
310 return ret;
311 }
312 }
313 return 0;
314 }
315
mtk_afe_dais_set_clks(struct mtk_afe * afe,struct clk * m_ck,unsigned int mck_rate,struct clk * b_ck,unsigned int bck_rate)316 static int mtk_afe_dais_set_clks(struct mtk_afe *afe,
317 struct clk *m_ck, unsigned int mck_rate,
318 struct clk *b_ck, unsigned int bck_rate)
319 {
320 int ret;
321
322 if (m_ck) {
323 ret = clk_set_rate(m_ck, mck_rate);
324 if (ret) {
325 dev_err(afe->dev, "Failed to set m_ck rate\n");
326 return ret;
327 }
328 }
329
330 if (b_ck) {
331 ret = clk_set_rate(b_ck, bck_rate);
332 if (ret) {
333 dev_err(afe->dev, "Failed to set b_ck rate\n");
334 return ret;
335 }
336 }
337 return 0;
338 }
339
mtk_afe_dais_disable_clks(struct mtk_afe * afe,struct clk * m_ck,struct clk * b_ck)340 static void mtk_afe_dais_disable_clks(struct mtk_afe *afe,
341 struct clk *m_ck, struct clk *b_ck)
342 {
343 if (m_ck) {
344 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
345 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
346 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
347 clk_disable_unprepare(m_ck);
348 }
349 if (b_ck)
350 clk_disable_unprepare(b_ck);
351 }
352
mtk_afe_i2s_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)353 static int mtk_afe_i2s_startup(struct snd_pcm_substream *substream,
354 struct snd_soc_dai *dai)
355 {
356 struct snd_soc_pcm_runtime *rtd = substream->private_data;
357 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
358
359 if (dai->active)
360 return 0;
361
362 mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
363 return 0;
364 }
365
mtk_afe_i2s_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)366 static void mtk_afe_i2s_shutdown(struct snd_pcm_substream *substream,
367 struct snd_soc_dai *dai)
368 {
369 struct snd_soc_pcm_runtime *rtd = substream->private_data;
370 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
371
372 if (dai->active)
373 return;
374
375 mtk_afe_set_i2s_enable(afe, false);
376 mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
377
378 /* disable AFE */
379 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
380 }
381
mtk_afe_i2s_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)382 static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream,
383 struct snd_soc_dai *dai)
384 {
385 struct snd_soc_pcm_runtime *rtd = substream->private_data;
386 struct snd_pcm_runtime * const runtime = substream->runtime;
387 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
388 int ret;
389
390 mtk_afe_dais_set_clks(afe,
391 afe->clocks[MTK_CLK_I2S1_M], runtime->rate * 256,
392 NULL, 0);
393 /* config I2S */
394 ret = mtk_afe_set_i2s(afe, substream->runtime->rate);
395 if (ret)
396 return ret;
397
398 mtk_afe_set_i2s_enable(afe, true);
399
400 return 0;
401 }
402
mtk_afe_hdmi_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)403 static int mtk_afe_hdmi_startup(struct snd_pcm_substream *substream,
404 struct snd_soc_dai *dai)
405 {
406 struct snd_soc_pcm_runtime *rtd = substream->private_data;
407 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
408
409 if (dai->active)
410 return 0;
411
412 mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S3_M],
413 afe->clocks[MTK_CLK_I2S3_B]);
414 return 0;
415 }
416
mtk_afe_hdmi_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)417 static void mtk_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
418 struct snd_soc_dai *dai)
419 {
420 struct snd_soc_pcm_runtime *rtd = substream->private_data;
421 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
422
423 if (dai->active)
424 return;
425
426 mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S3_M],
427 afe->clocks[MTK_CLK_I2S3_B]);
428
429 /* disable AFE */
430 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
431 }
432
mtk_afe_hdmi_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)433 static int mtk_afe_hdmi_prepare(struct snd_pcm_substream *substream,
434 struct snd_soc_dai *dai)
435 {
436 struct snd_soc_pcm_runtime *rtd = substream->private_data;
437 struct snd_pcm_runtime * const runtime = substream->runtime;
438 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
439 unsigned int val;
440
441 mtk_afe_dais_set_clks(afe,
442 afe->clocks[MTK_CLK_I2S3_M], runtime->rate * 128,
443 afe->clocks[MTK_CLK_I2S3_B],
444 runtime->rate * runtime->channels * 32);
445
446 val = AFE_TDM_CON1_BCK_INV |
447 AFE_TDM_CON1_1_BCK_DELAY |
448 AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */
449 AFE_TDM_CON1_WLEN_32BIT |
450 AFE_TDM_CON1_32_BCK_CYCLES |
451 AFE_TDM_CON1_LRCK_WIDTH(32);
452 regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
453
454 /* set tdm2 config */
455 switch (runtime->channels) {
456 case 1:
457 case 2:
458 val = AFE_TDM_CH_START_O30_O31;
459 val |= (AFE_TDM_CH_ZERO << 4);
460 val |= (AFE_TDM_CH_ZERO << 8);
461 val |= (AFE_TDM_CH_ZERO << 12);
462 break;
463 case 3:
464 case 4:
465 val = AFE_TDM_CH_START_O30_O31;
466 val |= (AFE_TDM_CH_START_O32_O33 << 4);
467 val |= (AFE_TDM_CH_ZERO << 8);
468 val |= (AFE_TDM_CH_ZERO << 12);
469 break;
470 case 5:
471 case 6:
472 val = AFE_TDM_CH_START_O30_O31;
473 val |= (AFE_TDM_CH_START_O32_O33 << 4);
474 val |= (AFE_TDM_CH_START_O34_O35 << 8);
475 val |= (AFE_TDM_CH_ZERO << 12);
476 break;
477 case 7:
478 case 8:
479 val = AFE_TDM_CH_START_O30_O31;
480 val |= (AFE_TDM_CH_START_O32_O33 << 4);
481 val |= (AFE_TDM_CH_START_O34_O35 << 8);
482 val |= (AFE_TDM_CH_START_O36_O37 << 12);
483 break;
484 default:
485 val = 0;
486 }
487 regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
488
489 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
490 0x000000f0, runtime->channels << 4);
491 return 0;
492 }
493
mtk_afe_hdmi_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)494 static int mtk_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
495 struct snd_soc_dai *dai)
496 {
497 struct snd_soc_pcm_runtime *rtd = substream->private_data;
498 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
499
500 dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
501
502 switch (cmd) {
503 case SNDRV_PCM_TRIGGER_START:
504 case SNDRV_PCM_TRIGGER_RESUME:
505 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
506 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
507
508 /* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
509 regmap_write(afe->regmap, AFE_HDMI_CONN0,
510 AFE_HDMI_CONN0_O30_I30 | AFE_HDMI_CONN0_O31_I31 |
511 AFE_HDMI_CONN0_O32_I34 | AFE_HDMI_CONN0_O33_I35 |
512 AFE_HDMI_CONN0_O34_I32 | AFE_HDMI_CONN0_O35_I33 |
513 AFE_HDMI_CONN0_O36_I36 | AFE_HDMI_CONN0_O37_I37);
514
515 /* enable Out control */
516 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
517
518 /* enable tdm */
519 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
520
521 return 0;
522 case SNDRV_PCM_TRIGGER_STOP:
523 case SNDRV_PCM_TRIGGER_SUSPEND:
524 /* disable tdm */
525 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
526
527 /* disable Out control */
528 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
529
530 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
531 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
532 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
533
534 return 0;
535 default:
536 return -EINVAL;
537 }
538 }
539
mtk_afe_dais_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)540 static int mtk_afe_dais_startup(struct snd_pcm_substream *substream,
541 struct snd_soc_dai *dai)
542 {
543 struct snd_soc_pcm_runtime *rtd = substream->private_data;
544 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
545 struct snd_pcm_runtime *runtime = substream->runtime;
546 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
547 int ret;
548
549 memif->substream = substream;
550
551 snd_soc_set_runtime_hwparams(substream, &mtk_afe_hardware);
552
553 /*
554 * Capture cannot use ping-pong buffer since hw_ptr at IRQ may be
555 * smaller than period_size due to AFE's internal buffer.
556 * This easily leads to overrun when avail_min is period_size.
557 * One more period can hold the possible unread buffer.
558 */
559 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
560 ret = snd_pcm_hw_constraint_minmax(runtime,
561 SNDRV_PCM_HW_PARAM_PERIODS,
562 3,
563 mtk_afe_hardware.periods_max);
564 if (ret < 0) {
565 dev_err(afe->dev, "hw_constraint_minmax failed\n");
566 return ret;
567 }
568 }
569 ret = snd_pcm_hw_constraint_integer(runtime,
570 SNDRV_PCM_HW_PARAM_PERIODS);
571 if (ret < 0)
572 dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
573 return ret;
574 }
575
mtk_afe_dais_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)576 static void mtk_afe_dais_shutdown(struct snd_pcm_substream *substream,
577 struct snd_soc_dai *dai)
578 {
579 struct snd_soc_pcm_runtime *rtd = substream->private_data;
580 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
581 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
582
583 memif->substream = NULL;
584 }
585
mtk_afe_dais_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)586 static int mtk_afe_dais_hw_params(struct snd_pcm_substream *substream,
587 struct snd_pcm_hw_params *params,
588 struct snd_soc_dai *dai)
589 {
590 struct snd_soc_pcm_runtime *rtd = substream->private_data;
591 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
592 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
593 int ret;
594
595 dev_dbg(afe->dev,
596 "%s period = %u, rate= %u, channels=%u\n",
597 __func__, params_period_size(params), params_rate(params),
598 params_channels(params));
599
600 ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
601 if (ret < 0)
602 return ret;
603
604 memif->phys_buf_addr = substream->runtime->dma_addr;
605 memif->buffer_size = substream->runtime->dma_bytes;
606 memif->hw_ptr = 0;
607
608 /* start */
609 regmap_write(afe->regmap,
610 memif->data->reg_ofs_base, memif->phys_buf_addr);
611 /* end */
612 regmap_write(afe->regmap,
613 memif->data->reg_ofs_base + AFE_BASE_END_OFFSET,
614 memif->phys_buf_addr + memif->buffer_size - 1);
615
616 /* set channel */
617 if (memif->data->mono_shift >= 0) {
618 unsigned int mono = (params_channels(params) == 1) ? 1 : 0;
619
620 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
621 1 << memif->data->mono_shift,
622 mono << memif->data->mono_shift);
623 }
624
625 /* set rate */
626 if (memif->data->fs_shift < 0)
627 return 0;
628 if (memif->data->id == MTK_AFE_MEMIF_DAI ||
629 memif->data->id == MTK_AFE_MEMIF_MOD_DAI) {
630 unsigned int val;
631
632 switch (params_rate(params)) {
633 case 8000:
634 val = 0;
635 break;
636 case 16000:
637 val = 1;
638 break;
639 case 32000:
640 val = 2;
641 break;
642 default:
643 return -EINVAL;
644 }
645
646 if (memif->data->id == MTK_AFE_MEMIF_DAI)
647 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
648 0x3 << memif->data->fs_shift,
649 val << memif->data->fs_shift);
650 else
651 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
652 0x3 << memif->data->fs_shift,
653 val << memif->data->fs_shift);
654
655 } else {
656 int fs = mtk_afe_i2s_fs(params_rate(params));
657
658 if (fs < 0)
659 return -EINVAL;
660
661 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
662 0xf << memif->data->fs_shift,
663 fs << memif->data->fs_shift);
664 }
665
666 return 0;
667 }
668
mtk_afe_dais_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)669 static int mtk_afe_dais_hw_free(struct snd_pcm_substream *substream,
670 struct snd_soc_dai *dai)
671 {
672 return snd_pcm_lib_free_pages(substream);
673 }
674
mtk_afe_dais_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)675 static int mtk_afe_dais_prepare(struct snd_pcm_substream *substream,
676 struct snd_soc_dai *dai)
677 {
678 struct snd_soc_pcm_runtime *rtd = substream->private_data;
679 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
680
681 /* enable AFE */
682 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
683 return 0;
684 }
685
mtk_afe_dais_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)686 static int mtk_afe_dais_trigger(struct snd_pcm_substream *substream, int cmd,
687 struct snd_soc_dai *dai)
688 {
689 struct snd_soc_pcm_runtime *rtd = substream->private_data;
690 struct snd_pcm_runtime * const runtime = substream->runtime;
691 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
692 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
693 unsigned int counter = runtime->period_size;
694
695 dev_info(afe->dev, "%s %s cmd=%d\n", __func__, memif->data->name, cmd);
696
697 switch (cmd) {
698 case SNDRV_PCM_TRIGGER_START:
699 case SNDRV_PCM_TRIGGER_RESUME:
700 if (memif->data->enable_shift >= 0)
701 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
702 1 << memif->data->enable_shift,
703 1 << memif->data->enable_shift);
704
705 /* set irq counter */
706 regmap_update_bits(afe->regmap,
707 memif->data->irq_reg_cnt,
708 0x3ffff << memif->data->irq_cnt_shift,
709 counter << memif->data->irq_cnt_shift);
710
711 /* set irq fs */
712 if (memif->data->irq_fs_shift >= 0) {
713 int fs = mtk_afe_i2s_fs(runtime->rate);
714
715 if (fs < 0)
716 return -EINVAL;
717
718 regmap_update_bits(afe->regmap,
719 AFE_IRQ_MCU_CON,
720 0xf << memif->data->irq_fs_shift,
721 fs << memif->data->irq_fs_shift);
722 }
723 /* enable interrupt */
724 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON,
725 1 << memif->data->irq_en_shift,
726 1 << memif->data->irq_en_shift);
727
728 return 0;
729 case SNDRV_PCM_TRIGGER_STOP:
730 case SNDRV_PCM_TRIGGER_SUSPEND:
731 if (memif->data->enable_shift >= 0)
732 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
733 1 << memif->data->enable_shift, 0);
734 /* disable interrupt */
735 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON,
736 1 << memif->data->irq_en_shift,
737 0 << memif->data->irq_en_shift);
738 /* and clear pending IRQ */
739 regmap_write(afe->regmap, AFE_IRQ_CLR,
740 1 << memif->data->irq_clr_shift);
741 memif->hw_ptr = 0;
742 return 0;
743 default:
744 return -EINVAL;
745 }
746 }
747
748 /* FE DAIs */
749 static const struct snd_soc_dai_ops mtk_afe_dai_ops = {
750 .startup = mtk_afe_dais_startup,
751 .shutdown = mtk_afe_dais_shutdown,
752 .hw_params = mtk_afe_dais_hw_params,
753 .hw_free = mtk_afe_dais_hw_free,
754 .prepare = mtk_afe_dais_prepare,
755 .trigger = mtk_afe_dais_trigger,
756 };
757
758 /* BE DAIs */
759 static const struct snd_soc_dai_ops mtk_afe_i2s_ops = {
760 .startup = mtk_afe_i2s_startup,
761 .shutdown = mtk_afe_i2s_shutdown,
762 .prepare = mtk_afe_i2s_prepare,
763 };
764
765 static const struct snd_soc_dai_ops mtk_afe_hdmi_ops = {
766 .startup = mtk_afe_hdmi_startup,
767 .shutdown = mtk_afe_hdmi_shutdown,
768 .prepare = mtk_afe_hdmi_prepare,
769 .trigger = mtk_afe_hdmi_trigger,
770
771 };
772
773 static int mtk_afe_runtime_suspend(struct device *dev);
774 static int mtk_afe_runtime_resume(struct device *dev);
775
mtk_afe_dai_suspend(struct snd_soc_dai * dai)776 static int mtk_afe_dai_suspend(struct snd_soc_dai *dai)
777 {
778 struct mtk_afe *afe = snd_soc_dai_get_drvdata(dai);
779 int i;
780
781 dev_dbg(afe->dev, "%s\n", __func__);
782 if (pm_runtime_status_suspended(afe->dev) || afe->suspended)
783 return 0;
784
785 for (i = 0; i < ARRAY_SIZE(mtk_afe_backup_list); i++)
786 regmap_read(afe->regmap, mtk_afe_backup_list[i],
787 &afe->backup_regs[i]);
788
789 afe->suspended = true;
790 mtk_afe_runtime_suspend(afe->dev);
791 return 0;
792 }
793
mtk_afe_dai_resume(struct snd_soc_dai * dai)794 static int mtk_afe_dai_resume(struct snd_soc_dai *dai)
795 {
796 struct mtk_afe *afe = snd_soc_dai_get_drvdata(dai);
797 int i = 0;
798
799 dev_dbg(afe->dev, "%s\n", __func__);
800 if (pm_runtime_status_suspended(afe->dev) || !afe->suspended)
801 return 0;
802
803 mtk_afe_runtime_resume(afe->dev);
804
805 for (i = 0; i < ARRAY_SIZE(mtk_afe_backup_list); i++)
806 regmap_write(afe->regmap, mtk_afe_backup_list[i],
807 afe->backup_regs[i]);
808
809 afe->suspended = false;
810 return 0;
811 }
812
813 static struct snd_soc_dai_driver mtk_afe_pcm_dais[] = {
814 /* FE DAIs: memory intefaces to CPU */
815 {
816 .name = "DL1", /* downlink 1 */
817 .id = MTK_AFE_MEMIF_DL1,
818 .suspend = mtk_afe_dai_suspend,
819 .resume = mtk_afe_dai_resume,
820 .playback = {
821 .stream_name = "DL1",
822 .channels_min = 1,
823 .channels_max = 2,
824 .rates = SNDRV_PCM_RATE_8000_48000,
825 .formats = SNDRV_PCM_FMTBIT_S16_LE,
826 },
827 .ops = &mtk_afe_dai_ops,
828 }, {
829 .name = "VUL", /* voice uplink */
830 .id = MTK_AFE_MEMIF_VUL,
831 .suspend = mtk_afe_dai_suspend,
832 .resume = mtk_afe_dai_resume,
833 .capture = {
834 .stream_name = "VUL",
835 .channels_min = 1,
836 .channels_max = 2,
837 .rates = SNDRV_PCM_RATE_8000_48000,
838 .formats = SNDRV_PCM_FMTBIT_S16_LE,
839 },
840 .ops = &mtk_afe_dai_ops,
841 }, {
842 /* BE DAIs */
843 .name = "I2S",
844 .id = MTK_AFE_IO_I2S,
845 .playback = {
846 .stream_name = "I2S Playback",
847 .channels_min = 1,
848 .channels_max = 2,
849 .rates = SNDRV_PCM_RATE_8000_48000,
850 .formats = SNDRV_PCM_FMTBIT_S16_LE,
851 },
852 .capture = {
853 .stream_name = "I2S Capture",
854 .channels_min = 1,
855 .channels_max = 2,
856 .rates = SNDRV_PCM_RATE_8000_48000,
857 .formats = SNDRV_PCM_FMTBIT_S16_LE,
858 },
859 .ops = &mtk_afe_i2s_ops,
860 .symmetric_rates = 1,
861 },
862 };
863
864 static struct snd_soc_dai_driver mtk_afe_hdmi_dais[] = {
865 /* FE DAIs */
866 {
867 .name = "HDMI",
868 .id = MTK_AFE_MEMIF_HDMI,
869 .suspend = mtk_afe_dai_suspend,
870 .resume = mtk_afe_dai_resume,
871 .playback = {
872 .stream_name = "HDMI",
873 .channels_min = 2,
874 .channels_max = 8,
875 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
876 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
877 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
878 SNDRV_PCM_RATE_192000,
879 .formats = SNDRV_PCM_FMTBIT_S16_LE,
880 },
881 .ops = &mtk_afe_dai_ops,
882 }, {
883 /* BE DAIs */
884 .name = "HDMIO",
885 .id = MTK_AFE_IO_HDMI,
886 .playback = {
887 .stream_name = "HDMIO Playback",
888 .channels_min = 2,
889 .channels_max = 8,
890 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
891 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
892 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
893 SNDRV_PCM_RATE_192000,
894 .formats = SNDRV_PCM_FMTBIT_S16_LE,
895 },
896 .ops = &mtk_afe_hdmi_ops,
897 },
898 };
899
900 static const struct snd_kcontrol_new mtk_afe_o03_mix[] = {
901 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
902 };
903
904 static const struct snd_kcontrol_new mtk_afe_o04_mix[] = {
905 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
906 };
907
908 static const struct snd_kcontrol_new mtk_afe_o09_mix[] = {
909 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
910 };
911
912 static const struct snd_kcontrol_new mtk_afe_o10_mix[] = {
913 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
914 };
915
916 static const struct snd_soc_dapm_widget mtk_afe_pcm_widgets[] = {
917 /* inter-connections */
918 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
919 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
920 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
921 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
922
923 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
924 mtk_afe_o03_mix, ARRAY_SIZE(mtk_afe_o03_mix)),
925 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
926 mtk_afe_o04_mix, ARRAY_SIZE(mtk_afe_o04_mix)),
927 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
928 mtk_afe_o09_mix, ARRAY_SIZE(mtk_afe_o09_mix)),
929 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
930 mtk_afe_o10_mix, ARRAY_SIZE(mtk_afe_o10_mix)),
931 };
932
933 static const struct snd_soc_dapm_route mtk_afe_pcm_routes[] = {
934 {"I05", NULL, "DL1"},
935 {"I06", NULL, "DL1"},
936 {"I2S Playback", NULL, "O03"},
937 {"I2S Playback", NULL, "O04"},
938 {"VUL", NULL, "O09"},
939 {"VUL", NULL, "O10"},
940 {"I17", NULL, "I2S Capture"},
941 {"I18", NULL, "I2S Capture"},
942 { "O03", "I05 Switch", "I05" },
943 { "O04", "I06 Switch", "I06" },
944 { "O09", "I17 Switch", "I17" },
945 { "O10", "I18 Switch", "I18" },
946 };
947
948 static const struct snd_soc_dapm_route mtk_afe_hdmi_routes[] = {
949 {"HDMIO Playback", NULL, "HDMI"},
950 };
951
952 static const struct snd_soc_component_driver mtk_afe_pcm_dai_component = {
953 .name = "mtk-afe-pcm-dai",
954 .dapm_widgets = mtk_afe_pcm_widgets,
955 .num_dapm_widgets = ARRAY_SIZE(mtk_afe_pcm_widgets),
956 .dapm_routes = mtk_afe_pcm_routes,
957 .num_dapm_routes = ARRAY_SIZE(mtk_afe_pcm_routes),
958 };
959
960 static const struct snd_soc_component_driver mtk_afe_hdmi_dai_component = {
961 .name = "mtk-afe-hdmi-dai",
962 .dapm_routes = mtk_afe_hdmi_routes,
963 .num_dapm_routes = ARRAY_SIZE(mtk_afe_hdmi_routes),
964 };
965
966 static const char *aud_clks[MTK_CLK_NUM] = {
967 [MTK_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
968 [MTK_CLK_TOP_PDN_AUD] = "top_pdn_audio",
969 [MTK_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
970 [MTK_CLK_I2S0_M] = "i2s0_m",
971 [MTK_CLK_I2S1_M] = "i2s1_m",
972 [MTK_CLK_I2S2_M] = "i2s2_m",
973 [MTK_CLK_I2S3_M] = "i2s3_m",
974 [MTK_CLK_I2S3_B] = "i2s3_b",
975 [MTK_CLK_BCK0] = "bck0",
976 [MTK_CLK_BCK1] = "bck1",
977 };
978
979 static const struct mtk_afe_memif_data memif_data[MTK_AFE_MEMIF_NUM] = {
980 {
981 .name = "DL1",
982 .id = MTK_AFE_MEMIF_DL1,
983 .reg_ofs_base = AFE_DL1_BASE,
984 .reg_ofs_cur = AFE_DL1_CUR,
985 .fs_shift = 0,
986 .mono_shift = 21,
987 .enable_shift = 1,
988 .irq_reg_cnt = AFE_IRQ_CNT1,
989 .irq_cnt_shift = 0,
990 .irq_en_shift = 0,
991 .irq_fs_shift = 4,
992 .irq_clr_shift = 0,
993 }, {
994 .name = "DL2",
995 .id = MTK_AFE_MEMIF_DL2,
996 .reg_ofs_base = AFE_DL2_BASE,
997 .reg_ofs_cur = AFE_DL2_CUR,
998 .fs_shift = 4,
999 .mono_shift = 22,
1000 .enable_shift = 2,
1001 .irq_reg_cnt = AFE_IRQ_CNT1,
1002 .irq_cnt_shift = 20,
1003 .irq_en_shift = 2,
1004 .irq_fs_shift = 16,
1005 .irq_clr_shift = 2,
1006 }, {
1007 .name = "VUL",
1008 .id = MTK_AFE_MEMIF_VUL,
1009 .reg_ofs_base = AFE_VUL_BASE,
1010 .reg_ofs_cur = AFE_VUL_CUR,
1011 .fs_shift = 16,
1012 .mono_shift = 27,
1013 .enable_shift = 3,
1014 .irq_reg_cnt = AFE_IRQ_CNT2,
1015 .irq_cnt_shift = 0,
1016 .irq_en_shift = 1,
1017 .irq_fs_shift = 8,
1018 .irq_clr_shift = 1,
1019 }, {
1020 .name = "DAI",
1021 .id = MTK_AFE_MEMIF_DAI,
1022 .reg_ofs_base = AFE_DAI_BASE,
1023 .reg_ofs_cur = AFE_DAI_CUR,
1024 .fs_shift = 24,
1025 .mono_shift = -1,
1026 .enable_shift = 4,
1027 .irq_reg_cnt = AFE_IRQ_CNT2,
1028 .irq_cnt_shift = 20,
1029 .irq_en_shift = 3,
1030 .irq_fs_shift = 20,
1031 .irq_clr_shift = 3,
1032 }, {
1033 .name = "AWB",
1034 .id = MTK_AFE_MEMIF_AWB,
1035 .reg_ofs_base = AFE_AWB_BASE,
1036 .reg_ofs_cur = AFE_AWB_CUR,
1037 .fs_shift = 12,
1038 .mono_shift = 24,
1039 .enable_shift = 6,
1040 .irq_reg_cnt = AFE_IRQ_CNT7,
1041 .irq_cnt_shift = 0,
1042 .irq_en_shift = 14,
1043 .irq_fs_shift = 24,
1044 .irq_clr_shift = 6,
1045 }, {
1046 .name = "MOD_DAI",
1047 .id = MTK_AFE_MEMIF_MOD_DAI,
1048 .reg_ofs_base = AFE_MOD_PCM_BASE,
1049 .reg_ofs_cur = AFE_MOD_PCM_CUR,
1050 .fs_shift = 30,
1051 .mono_shift = 30,
1052 .enable_shift = 7,
1053 .irq_reg_cnt = AFE_IRQ_CNT2,
1054 .irq_cnt_shift = 20,
1055 .irq_en_shift = 3,
1056 .irq_fs_shift = 20,
1057 .irq_clr_shift = 3,
1058 }, {
1059 .name = "HDMI",
1060 .id = MTK_AFE_MEMIF_HDMI,
1061 .reg_ofs_base = AFE_HDMI_OUT_BASE,
1062 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
1063 .fs_shift = -1,
1064 .mono_shift = -1,
1065 .enable_shift = -1,
1066 .irq_reg_cnt = AFE_IRQ_CNT5,
1067 .irq_cnt_shift = 0,
1068 .irq_en_shift = 12,
1069 .irq_fs_shift = -1,
1070 .irq_clr_shift = 4,
1071 },
1072 };
1073
1074 static const struct regmap_config mtk_afe_regmap_config = {
1075 .reg_bits = 32,
1076 .reg_stride = 4,
1077 .val_bits = 32,
1078 .max_register = AFE_ADDA2_TOP_CON0,
1079 .cache_type = REGCACHE_NONE,
1080 };
1081
mtk_afe_irq_handler(int irq,void * dev_id)1082 static irqreturn_t mtk_afe_irq_handler(int irq, void *dev_id)
1083 {
1084 struct mtk_afe *afe = dev_id;
1085 unsigned int reg_value, hw_ptr;
1086 int i, ret;
1087
1088 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, ®_value);
1089 if (ret) {
1090 dev_err(afe->dev, "%s irq status err\n", __func__);
1091 reg_value = AFE_IRQ_STATUS_BITS;
1092 goto err_irq;
1093 }
1094
1095 for (i = 0; i < MTK_AFE_MEMIF_NUM; i++) {
1096 struct mtk_afe_memif *memif = &afe->memif[i];
1097
1098 if (!(reg_value & (1 << memif->data->irq_clr_shift)))
1099 continue;
1100
1101 ret = regmap_read(afe->regmap, memif->data->reg_ofs_cur,
1102 &hw_ptr);
1103 if (ret || hw_ptr == 0) {
1104 dev_err(afe->dev, "%s hw_ptr err\n", __func__);
1105 hw_ptr = memif->phys_buf_addr;
1106 }
1107 memif->hw_ptr = hw_ptr - memif->phys_buf_addr;
1108 snd_pcm_period_elapsed(memif->substream);
1109 }
1110
1111 err_irq:
1112 /* clear irq */
1113 regmap_write(afe->regmap, AFE_IRQ_CLR, reg_value & AFE_IRQ_STATUS_BITS);
1114
1115 return IRQ_HANDLED;
1116 }
1117
mtk_afe_runtime_suspend(struct device * dev)1118 static int mtk_afe_runtime_suspend(struct device *dev)
1119 {
1120 struct mtk_afe *afe = dev_get_drvdata(dev);
1121
1122 /* disable AFE clk */
1123 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
1124 AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
1125
1126 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);
1127 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK1]);
1128 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1129 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1130 clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1131 return 0;
1132 }
1133
mtk_afe_runtime_resume(struct device * dev)1134 static int mtk_afe_runtime_resume(struct device *dev)
1135 {
1136 struct mtk_afe *afe = dev_get_drvdata(dev);
1137 int ret;
1138
1139 ret = clk_prepare_enable(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1140 if (ret)
1141 return ret;
1142
1143 ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1144 if (ret)
1145 goto err_infra;
1146
1147 ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1148 if (ret)
1149 goto err_top_aud_bus;
1150
1151 ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK0]);
1152 if (ret)
1153 goto err_top_aud;
1154
1155 ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK1]);
1156 if (ret)
1157 goto err_bck0;
1158
1159 /* enable AFE clk */
1160 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
1161
1162 /* set O3/O4 16bits */
1163 regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
1164 AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
1165
1166 /* unmask all IRQs */
1167 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
1168 return 0;
1169
1170 err_bck0:
1171 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);
1172 err_top_aud:
1173 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1174 err_top_aud_bus:
1175 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1176 err_infra:
1177 clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1178 return ret;
1179 }
1180
mtk_afe_init_audio_clk(struct mtk_afe * afe)1181 static int mtk_afe_init_audio_clk(struct mtk_afe *afe)
1182 {
1183 size_t i;
1184
1185 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
1186 afe->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1187 if (IS_ERR(afe->clocks[i])) {
1188 dev_err(afe->dev, "%s devm_clk_get %s fail\n",
1189 __func__, aud_clks[i]);
1190 return PTR_ERR(afe->clocks[i]);
1191 }
1192 }
1193 clk_set_rate(afe->clocks[MTK_CLK_BCK0], 22579200); /* 22M */
1194 clk_set_rate(afe->clocks[MTK_CLK_BCK1], 24576000); /* 24M */
1195 return 0;
1196 }
1197
mtk_afe_pcm_dev_probe(struct platform_device * pdev)1198 static int mtk_afe_pcm_dev_probe(struct platform_device *pdev)
1199 {
1200 int ret, i;
1201 unsigned int irq_id;
1202 struct mtk_afe *afe;
1203 struct resource *res;
1204
1205 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1206 if (!afe)
1207 return -ENOMEM;
1208
1209 afe->dev = &pdev->dev;
1210
1211 irq_id = platform_get_irq(pdev, 0);
1212 if (!irq_id) {
1213 dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name);
1214 return -ENXIO;
1215 }
1216 ret = devm_request_irq(afe->dev, irq_id, mtk_afe_irq_handler,
1217 0, "Afe_ISR_Handle", (void *)afe);
1218 if (ret) {
1219 dev_err(afe->dev, "could not request_irq\n");
1220 return ret;
1221 }
1222
1223 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1224 afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
1225 if (IS_ERR(afe->base_addr))
1226 return PTR_ERR(afe->base_addr);
1227
1228 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
1229 &mtk_afe_regmap_config);
1230 if (IS_ERR(afe->regmap))
1231 return PTR_ERR(afe->regmap);
1232
1233 /* initial audio related clock */
1234 ret = mtk_afe_init_audio_clk(afe);
1235 if (ret) {
1236 dev_err(afe->dev, "mtk_afe_init_audio_clk fail\n");
1237 return ret;
1238 }
1239
1240 for (i = 0; i < MTK_AFE_MEMIF_NUM; i++)
1241 afe->memif[i].data = &memif_data[i];
1242
1243 platform_set_drvdata(pdev, afe);
1244
1245 pm_runtime_enable(&pdev->dev);
1246 if (!pm_runtime_enabled(&pdev->dev)) {
1247 ret = mtk_afe_runtime_resume(&pdev->dev);
1248 if (ret)
1249 goto err_pm_disable;
1250 }
1251
1252 ret = snd_soc_register_platform(&pdev->dev, &mtk_afe_pcm_platform);
1253 if (ret)
1254 goto err_pm_disable;
1255
1256 ret = snd_soc_register_component(&pdev->dev,
1257 &mtk_afe_pcm_dai_component,
1258 mtk_afe_pcm_dais,
1259 ARRAY_SIZE(mtk_afe_pcm_dais));
1260 if (ret)
1261 goto err_platform;
1262
1263 ret = snd_soc_register_component(&pdev->dev,
1264 &mtk_afe_hdmi_dai_component,
1265 mtk_afe_hdmi_dais,
1266 ARRAY_SIZE(mtk_afe_hdmi_dais));
1267 if (ret)
1268 goto err_comp;
1269
1270 dev_info(&pdev->dev, "MTK AFE driver initialized.\n");
1271 return 0;
1272
1273 err_comp:
1274 snd_soc_unregister_component(&pdev->dev);
1275 err_platform:
1276 snd_soc_unregister_platform(&pdev->dev);
1277 err_pm_disable:
1278 pm_runtime_disable(&pdev->dev);
1279 return ret;
1280 }
1281
mtk_afe_pcm_dev_remove(struct platform_device * pdev)1282 static int mtk_afe_pcm_dev_remove(struct platform_device *pdev)
1283 {
1284 pm_runtime_disable(&pdev->dev);
1285 if (!pm_runtime_status_suspended(&pdev->dev))
1286 mtk_afe_runtime_suspend(&pdev->dev);
1287 snd_soc_unregister_component(&pdev->dev);
1288 snd_soc_unregister_platform(&pdev->dev);
1289 return 0;
1290 }
1291
1292 static const struct of_device_id mtk_afe_pcm_dt_match[] = {
1293 { .compatible = "mediatek,mt8173-afe-pcm", },
1294 { }
1295 };
1296 MODULE_DEVICE_TABLE(of, mtk_afe_pcm_dt_match);
1297
1298 static const struct dev_pm_ops mtk_afe_pm_ops = {
1299 SET_RUNTIME_PM_OPS(mtk_afe_runtime_suspend, mtk_afe_runtime_resume,
1300 NULL)
1301 };
1302
1303 static struct platform_driver mtk_afe_pcm_driver = {
1304 .driver = {
1305 .name = "mtk-afe-pcm",
1306 .of_match_table = mtk_afe_pcm_dt_match,
1307 .pm = &mtk_afe_pm_ops,
1308 },
1309 .probe = mtk_afe_pcm_dev_probe,
1310 .remove = mtk_afe_pcm_dev_remove,
1311 };
1312
1313 module_platform_driver(mtk_afe_pcm_driver);
1314
1315 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
1316 MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
1317 MODULE_LICENSE("GPL v2");
1318