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/arch/powerpc/kernel/
Dfpu.S30 #define __REST_32FPVSRS(n,c,base) \ argument
39 #define __SAVE_32FPVSRS(n,c,base) \ argument
48 #define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) argument
49 #define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) argument
51 #define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) argument
52 #define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) argument
Dtm.S17 #define __SAVE_32FPRS_VSRS(n,c,base) \ argument
25 #define __REST_32FPRS_VSRS(n,c,base) \ argument
34 #define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base) argument
35 #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base) argument
37 #define SAVE_32FPRS_VSRS(n,c,base) \ argument
39 #define REST_32FPRS_VSRS(n,c,base) \ argument
/arch/powerpc/boot/
Dcrt0.S233 #define SAVE_GPR(n, base) std n,8*(n)(base) argument
234 #define REST_GPR(n, base) ld n,8*(n)(base) argument
235 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) argument
236 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) argument
237 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) argument
238 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) argument
239 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) argument
240 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) argument
241 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) argument
242 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) argument
/arch/mips/include/asm/netlogic/
Dhaldefs.h46 nlm_read_reg(uint64_t base, uint32_t reg) in nlm_read_reg()
54 nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) in nlm_write_reg()
71 nlm_read_reg64(uint64_t base, uint32_t reg) in nlm_read_reg64()
98 nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) in nlm_write_reg64()
129 nlm_read_reg_xkphys(uint64_t base, uint32_t reg) in nlm_read_reg_xkphys()
135 nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val) in nlm_write_reg_xkphys()
141 nlm_read_reg64_xkphys(uint64_t base, uint32_t reg) in nlm_read_reg64_xkphys()
147 nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) in nlm_write_reg64_xkphys()
/arch/arm/mm/
Dcache-l2x0.c74 static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) in l2c_write_sec()
89 static inline void l2c_set_debug(void __iomem *base, unsigned long val) in l2c_set_debug()
100 static inline void l2c_unlock(void __iomem *base, unsigned num) in l2c_unlock()
112 static void l2c_configure(void __iomem *base) in l2c_configure()
121 static void l2c_enable(void __iomem *base, unsigned num_lock) in l2c_enable()
143 void __iomem *base = l2x0_base; in l2c_disable() local
152 static void l2c_save(void __iomem *base) in l2c_save()
159 void __iomem *base = l2x0_base; in l2c_resume() local
182 static void __l2c210_cache_sync(void __iomem *base) in __l2c210_cache_sync()
198 void __iomem *base = l2x0_base; in l2c210_inv_range() local
[all …]
/arch/arm/plat-orion/
Dpcie.c55 u32 orion_pcie_dev_id(void __iomem *base) in orion_pcie_dev_id()
60 u32 orion_pcie_rev(void __iomem *base) in orion_pcie_rev()
65 int orion_pcie_link_up(void __iomem *base) in orion_pcie_link_up()
70 int __init orion_pcie_x4_mode(void __iomem *base) in orion_pcie_x4_mode()
75 int orion_pcie_get_local_bus_nr(void __iomem *base) in orion_pcie_get_local_bus_nr()
82 void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr) in orion_pcie_set_local_bus_nr()
92 void __init orion_pcie_reset(void __iomem *base) in orion_pcie_reset()
123 static void __init orion_pcie_setup_wins(void __iomem *base) in orion_pcie_setup_wins()
181 void __init orion_pcie_setup(void __iomem *base) in orion_pcie_setup()
208 int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, in orion_pcie_rd_conf()
[all …]
/arch/mips/ath25/
Dearly_printk.c17 static inline void prom_uart_wr(void __iomem *base, unsigned reg, in prom_uart_wr()
23 static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) in prom_uart_rr()
30 static void __iomem *base; in prom_putchar() local
/arch/mips/alchemy/common/
Dusb.c97 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) in __au1300_usb_phyctl()
122 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) in __au1300_ohci_control()
162 static inline void __au1300_ehci_control(void __iomem *base, int enable) in __au1300_ehci_control()
203 static inline void __au1300_udc_control(void __iomem *base, int enable) in __au1300_udc_control()
234 static inline void __au1300_otg_control(void __iomem *base, int enable) in __au1300_otg_control()
266 void __iomem *base = in au1300_usb_control() local
294 void __iomem *base = in au1300_usb_init() local
315 static inline void __au1200_ohci_control(void __iomem *base, int enable) in __au1200_ohci_control()
329 static inline void __au1200_ehci_control(void __iomem *base, int enable) in __au1200_ehci_control()
345 static inline void __au1200_udc_control(void __iomem *base, int enable) in __au1200_udc_control()
[all …]
Dirq.c291 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_unmask() local
301 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_unmask() local
311 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_mask() local
321 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_mask() local
331 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_ack() local
345 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_ack() local
359 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_maskack() local
371 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_maskack() local
432 void __iomem *base; in au1x_ic_settype() local
715 static inline void ic_init(void __iomem *base) in ic_init()
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/arch/arm/mach-mmp/
Ddevices.c83 static unsigned int u2o_get(void __iomem *base, unsigned int offset) in u2o_get()
88 static void u2o_set(void __iomem *base, unsigned int offset, in u2o_set()
99 static void u2o_clear(void __iomem *base, unsigned int offset, in u2o_clear()
110 static void u2o_write(void __iomem *base, unsigned int offset, in u2o_write()
121 static int usb_phy_init_internal(void __iomem *base) in usb_phy_init_internal()
202 static int usb_phy_deinit_internal(void __iomem *base) in usb_phy_deinit_internal()
/arch/powerpc/net/
Dbpf_jit32.h78 #define PPC_LBZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LBZ(r, base, i); \ argument
82 #define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i); \ argument
86 #define PPC_LWZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LWZ(r, base, i); \ argument
90 #define PPC_LHZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LHZ(r, base, i); \ argument
95 #define PPC_LL_OFFS(r, base, i) do { PPC_LD_OFFS(r, base, i); } while(0) argument
97 #define PPC_LL_OFFS(r, base, i) do { PPC_LWZ_OFFS(r, base, i); } while(0) argument
117 #define PPC_LHBRX_OFFS(r, base, i) \ argument
120 #define PPC_NTOHS_OFFS(r, base, i) PPC_LHBRX_OFFS(r, base, i) argument
122 #define PPC_NTOHS_OFFS(r, base, i) PPC_LHZ_OFFS(r, base, i) argument
/arch/powerpc/include/asm/
Dppc_asm.h78 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) argument
79 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) argument
80 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) argument
81 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) argument
83 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) argument
84 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) argument
85 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ argument
87 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ argument
91 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) argument
92 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) argument
[all …]
/arch/mips/loongson64/common/
Dearly_printk.c16 #define PORT(base, offset) (u8 *)(base + offset) argument
18 static inline unsigned int serial_in(unsigned char *base, int offset) in serial_in()
23 static inline void serial_out(unsigned char *base, int offset, int value) in serial_out()
/arch/mips/include/asm/
Dr4kcache.h229 #define cache16_unroll32(base,op) \ argument
255 #define cache32_unroll32(base,op) \ argument
281 #define cache64_unroll32(base,op) \ argument
307 #define cache128_unroll32(base,op) \ argument
339 #define cache16_unroll32(base,op) \ argument
367 #define cache32_unroll32(base,op) \ argument
397 #define cache64_unroll32(base,op) \ argument
431 #define cache128_unroll32(base,op) \ argument
480 #define cache16_unroll32_user(base,op) \ argument
507 #define cache32_unroll32_user(base, op) \ argument
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/arch/arm/mach-gemini/
Dgpio.c48 static void _set_gpio_irqenable(void __iomem *base, unsigned int index, in _set_gpio_irqenable()
61 void __iomem *base = GPIO_BASE(gpio / 32); in gpio_ack_irq() local
69 void __iomem *base = GPIO_BASE(gpio / 32); in gpio_mask_irq() local
77 void __iomem *base = GPIO_BASE(gpio / 32); in gpio_unmask_irq() local
86 void __iomem *base = GPIO_BASE(gpio / 32); in gpio_set_irq_type() local
157 void __iomem *base = GPIO_BASE(offset / 32); in _set_gpio_direction() local
170 void __iomem *base = GPIO_BASE(offset / 32); in gemini_gpio_set() local
180 void __iomem *base = GPIO_BASE(offset / 32); in gemini_gpio_get() local
/arch/x86/kernel/cpu/mtrr/
Damd.c9 amd_get_mtrr(unsigned int reg, unsigned long *base, in amd_get_mtrr()
59 amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) in amd_set_mtrr()
95 amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type) in amd_validate_add_page()
Dcentaur.c26 centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg) in centaur_get_free_region()
57 centaur_get_mcr(unsigned int reg, unsigned long *base, in centaur_get_mcr()
73 centaur_set_mcr(unsigned int reg, unsigned long base, in centaur_set_mcr()
99 centaur_validate_add_page(unsigned long base, unsigned long size, unsigned int type) in centaur_validate_add_page()
/arch/mips/ath79/
Dearly_printk.c38 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); in prom_putchar_ar71xx() local
47 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE)); in prom_putchar_ar933x() local
63 void __iomem *base; in prom_putchar_init() local
/arch/x86/include/asm/
Dmtrr.h62 static inline int mtrr_add(unsigned long base, unsigned long size, in mtrr_add()
67 static inline int mtrr_add_page(unsigned long base, unsigned long size, in mtrr_add_page()
72 static inline int mtrr_del(int reg, unsigned long base, unsigned long size) in mtrr_del()
76 static inline int mtrr_del_page(int reg, unsigned long base, unsigned long size) in mtrr_del_page()
102 compat_ulong_t base; /* Base address */ member
109 compat_uint_t base; /* Base address */ member
/arch/nios2/kernel/
Dprom.c36 void __init early_init_dt_add_memory_arch(u64 base, u64 size) in early_init_dt_add_memory_arch()
51 int __init early_init_dt_reserve_memory_arch(phys_addr_t base, phys_addr_t size, in early_init_dt_reserve_memory_arch()
114 u64 base = 0; in of_early_console() local
/arch/alpha/kernel/
Dpc873xx.c12 static unsigned int base, model; variable
25 static unsigned char __init pc873xx_read(unsigned int base, int reg) in pc873xx_read()
31 static void __init pc873xx_write(unsigned int base, int reg, unsigned char data) in pc873xx_write()
/arch/arm/mach-ebsa110/include/mach/
Duncompress.h20 unsigned char v, *base = SERIAL_BASE; in putc() local
32 unsigned char v, *base = SERIAL_BASE; in flush() local
/arch/x86/mm/
Diomap_32.c24 static int is_io_mapping_possible(resource_size_t base, unsigned long size) in is_io_mapping_possible()
34 int iomap_create_wc(resource_size_t base, unsigned long size, pgprot_t *prot) in iomap_create_wc()
51 void iomap_free(resource_size_t base, unsigned long size) in iomap_free()
/arch/mips/pci/
Dpci-ar71xx.c112 void __iomem *base = apc->cfg_base; in ar71xx_pci_check_error() local
150 void __iomem *base = apc->cfg_base; in ar71xx_pci_local_write() local
167 void __iomem *base = apc->cfg_base; in ar71xx_pci_set_cfgaddr() local
183 void __iomem *base = apc->cfg_base; in ar71xx_pci_read_config() local
207 void __iomem *base = apc->cfg_base; in ar71xx_pci_write_config() local
232 void __iomem *base = ath79_reset_base; in ar71xx_pci_irq_handler() local
260 void __iomem *base = ath79_reset_base; in ar71xx_pci_irq_unmask() local
277 void __iomem *base = ath79_reset_base; in ar71xx_pci_irq_mask() local
299 void __iomem *base = ath79_reset_base; in ar71xx_pci_irq_init() local
/arch/arm/mach-pxa/
Dirq.c69 void __iomem *base = irq_data_get_irq_chip_data(d); in pxa_mask_irq() local
79 void __iomem *base = irq_data_get_irq_chip_data(d); in pxa_unmask_irq() local
127 void __iomem *base = irq_base(hw / 32); in pxa_irq_map() local
160 void __iomem *base = irq_base(n >> 5); in pxa_init_irq_common() local
189 void __iomem *base = irq_base(i); in pxa_irq_suspend() local
208 void __iomem *base = irq_base(i); in pxa_irq_resume() local

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