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1 /*
2  *  S390 version
3  *    Copyright IBM Corp. 1999
4  *    Author(s): Hartmut Penner (hp@de.ibm.com),
5  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
6  *
7  *  Derived from "include/asm-i386/processor.h"
8  *    Copyright (C) 1994, Linus Torvalds
9  */
10 
11 #ifndef __ASM_S390_PROCESSOR_H
12 #define __ASM_S390_PROCESSOR_H
13 
14 #include <linux/const.h>
15 
16 #define CIF_MCCK_PENDING	0	/* machine check handling is pending */
17 #define CIF_ASCE		1	/* user asce needs fixup / uaccess */
18 #define CIF_NOHZ_DELAY		2	/* delay HZ disable for a tick */
19 #define CIF_FPU			3	/* restore FPU registers */
20 #define CIF_IGNORE_IRQ		4	/* ignore interrupt (for udelay) */
21 #define CIF_ENABLED_WAIT	5	/* in enabled wait state */
22 
23 #define _CIF_MCCK_PENDING	_BITUL(CIF_MCCK_PENDING)
24 #define _CIF_ASCE		_BITUL(CIF_ASCE)
25 #define _CIF_NOHZ_DELAY		_BITUL(CIF_NOHZ_DELAY)
26 #define _CIF_FPU		_BITUL(CIF_FPU)
27 #define _CIF_IGNORE_IRQ		_BITUL(CIF_IGNORE_IRQ)
28 #define _CIF_ENABLED_WAIT	_BITUL(CIF_ENABLED_WAIT)
29 
30 #ifndef __ASSEMBLY__
31 
32 #include <linux/linkage.h>
33 #include <linux/irqflags.h>
34 #include <asm/cpu.h>
35 #include <asm/page.h>
36 #include <asm/ptrace.h>
37 #include <asm/setup.h>
38 #include <asm/runtime_instr.h>
39 #include <asm/fpu/types.h>
40 #include <asm/fpu/internal.h>
41 
set_cpu_flag(int flag)42 static inline void set_cpu_flag(int flag)
43 {
44 	S390_lowcore.cpu_flags |= (1UL << flag);
45 }
46 
clear_cpu_flag(int flag)47 static inline void clear_cpu_flag(int flag)
48 {
49 	S390_lowcore.cpu_flags &= ~(1UL << flag);
50 }
51 
test_cpu_flag(int flag)52 static inline int test_cpu_flag(int flag)
53 {
54 	return !!(S390_lowcore.cpu_flags & (1UL << flag));
55 }
56 
57 /*
58  * Test CIF flag of another CPU. The caller needs to ensure that
59  * CPU hotplug can not happen, e.g. by disabling preemption.
60  */
test_cpu_flag_of(int flag,int cpu)61 static inline int test_cpu_flag_of(int flag, int cpu)
62 {
63 	struct lowcore *lc = lowcore_ptr[cpu];
64 	return !!(lc->cpu_flags & (1UL << flag));
65 }
66 
67 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
68 
69 /*
70  * Default implementation of macro that returns current
71  * instruction pointer ("program counter").
72  */
73 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
74 
get_cpu_id(struct cpuid * ptr)75 static inline void get_cpu_id(struct cpuid *ptr)
76 {
77 	asm volatile("stidp %0" : "=Q" (*ptr));
78 }
79 
80 void s390_adjust_jiffies(void);
81 void s390_update_cpu_mhz(void);
82 void cpu_detect_mhz_feature(void);
83 
84 extern const struct seq_operations cpuinfo_op;
85 extern int sysctl_ieee_emulation_warnings;
86 extern void execve_tail(void);
87 extern void __bpon(void);
88 
89 /*
90  * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
91  */
92 
93 #define TASK_SIZE_OF(tsk)	((tsk)->mm ? \
94 				 (tsk)->mm->context.asce_limit : TASK_MAX_SIZE)
95 #define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
96 					(1UL << 30) : (1UL << 41))
97 #define TASK_SIZE		TASK_SIZE_OF(current)
98 #define TASK_MAX_SIZE		(1UL << 53)
99 
100 #define STACK_TOP		(1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
101 #define STACK_TOP_MAX		(1UL << 42)
102 
103 #define HAVE_ARCH_PICK_MMAP_LAYOUT
104 
105 typedef struct {
106         __u32 ar4;
107 } mm_segment_t;
108 
109 /*
110  * Thread structure
111  */
112 struct thread_struct {
113 	unsigned int  acrs[NUM_ACRS];
114         unsigned long ksp;              /* kernel stack pointer             */
115 	mm_segment_t mm_segment;
116 	unsigned long gmap_addr;	/* address of last gmap fault. */
117 	unsigned int gmap_write_flag;	/* gmap fault write indication */
118 	unsigned int gmap_int_code;	/* int code of last gmap fault */
119 	unsigned int gmap_pfault;	/* signal of a pending guest pfault */
120 	struct per_regs per_user;	/* User specified PER registers */
121 	struct per_event per_event;	/* Cause of the last PER trap */
122 	unsigned long per_flags;	/* Flags to control debug behavior */
123         /* pfault_wait is used to block the process on a pfault event */
124 	unsigned long pfault_wait;
125 	struct list_head list;
126 	/* cpu runtime instrumentation */
127 	struct runtime_instr_cb *ri_cb;
128 	unsigned char trap_tdb[256];	/* Transaction abort diagnose block */
129 	/*
130 	 * Warning: 'fpu' is dynamically-sized. It *MUST* be at
131 	 * the end.
132 	 */
133 	struct fpu fpu;			/* FP and VX register save area */
134 };
135 
136 /* Flag to disable transactions. */
137 #define PER_FLAG_NO_TE			1UL
138 /* Flag to enable random transaction aborts. */
139 #define PER_FLAG_TE_ABORT_RAND		2UL
140 /* Flag to specify random transaction abort mode:
141  * - abort each transaction at a random instruction before TEND if set.
142  * - abort random transactions at a random instruction if cleared.
143  */
144 #define PER_FLAG_TE_ABORT_RAND_TEND	4UL
145 
146 typedef struct thread_struct thread_struct;
147 
148 /*
149  * Stack layout of a C stack frame.
150  */
151 #ifndef __PACK_STACK
152 struct stack_frame {
153 	unsigned long back_chain;
154 	unsigned long empty1[5];
155 	unsigned long gprs[10];
156 	unsigned int  empty2[8];
157 };
158 #else
159 struct stack_frame {
160 	unsigned long empty1[5];
161 	unsigned int  empty2[8];
162 	unsigned long gprs[10];
163 	unsigned long back_chain;
164 };
165 #endif
166 
167 #define ARCH_MIN_TASKALIGN	8
168 
169 #define INIT_THREAD {							\
170 	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
171 	.fpu.regs = (void *) init_task.thread.fpu.fprs,			\
172 }
173 
174 /*
175  * Do necessary setup to start up a new thread.
176  */
177 #define start_thread(regs, new_psw, new_stackp) do {			\
178 	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;	\
179 	regs->psw.addr	= new_psw;					\
180 	regs->gprs[15]	= new_stackp;					\
181 	execve_tail();							\
182 } while (0)
183 
184 #define start_thread31(regs, new_psw, new_stackp) do {			\
185 	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
186 	regs->psw.addr	= new_psw;					\
187 	regs->gprs[15]	= new_stackp;					\
188 	crst_table_downgrade(current->mm);				\
189 	execve_tail();							\
190 } while (0)
191 
192 /* Forward declaration, a strange C thing */
193 struct task_struct;
194 struct mm_struct;
195 struct seq_file;
196 
197 typedef int (*dump_trace_func_t)(void *data, unsigned long address, int reliable);
198 void dump_trace(dump_trace_func_t func, void *data,
199 		struct task_struct *task, unsigned long sp);
200 
201 void show_cacheinfo(struct seq_file *m);
202 
203 /* Free all resources held by a thread. */
204 extern void release_thread(struct task_struct *);
205 
206 /*
207  * Return saved PC of a blocked thread.
208  */
209 extern unsigned long thread_saved_pc(struct task_struct *t);
210 
211 unsigned long get_wchan(struct task_struct *p);
212 #define task_pt_regs(tsk) ((struct pt_regs *) \
213         (task_stack_page(tsk) + THREAD_SIZE) - 1)
214 #define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
215 #define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])
216 
217 /* Has task runtime instrumentation enabled ? */
218 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
219 
current_stack_pointer(void)220 static inline unsigned long current_stack_pointer(void)
221 {
222 	unsigned long sp;
223 
224 	asm volatile("la %0,0(15)" : "=a" (sp));
225 	return sp;
226 }
227 
stap(void)228 static inline unsigned short stap(void)
229 {
230 	unsigned short cpu_address;
231 
232 	asm volatile("stap %0" : "=m" (cpu_address));
233 	return cpu_address;
234 }
235 
236 /*
237  * Give up the time slice of the virtual PU.
238  */
239 void cpu_relax(void);
240 
241 #define cpu_relax_lowlatency()  barrier()
242 
243 #define ECAG_CACHE_ATTRIBUTE	0
244 #define ECAG_CPU_ATTRIBUTE	1
245 
__ecag(unsigned int asi,unsigned char parm)246 static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
247 {
248 	unsigned long val;
249 
250 	asm volatile(".insn	rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */
251 		     : "=d" (val) : "a" (asi << 8 | parm));
252 	return val;
253 }
254 
psw_set_key(unsigned int key)255 static inline void psw_set_key(unsigned int key)
256 {
257 	asm volatile("spka 0(%0)" : : "d" (key));
258 }
259 
260 /*
261  * Set PSW to specified value.
262  */
__load_psw(psw_t psw)263 static inline void __load_psw(psw_t psw)
264 {
265 	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
266 }
267 
268 /*
269  * Set PSW mask to specified value, while leaving the
270  * PSW addr pointing to the next instruction.
271  */
__load_psw_mask(unsigned long mask)272 static inline void __load_psw_mask(unsigned long mask)
273 {
274 	unsigned long addr;
275 	psw_t psw;
276 
277 	psw.mask = mask;
278 
279 	asm volatile(
280 		"	larl	%0,1f\n"
281 		"	stg	%0,%O1+8(%R1)\n"
282 		"	lpswe	%1\n"
283 		"1:"
284 		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
285 }
286 
287 /*
288  * Extract current PSW mask
289  */
__extract_psw(void)290 static inline unsigned long __extract_psw(void)
291 {
292 	unsigned int reg1, reg2;
293 
294 	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
295 	return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
296 }
297 
local_mcck_enable(void)298 static inline void local_mcck_enable(void)
299 {
300 	__load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
301 }
302 
local_mcck_disable(void)303 static inline void local_mcck_disable(void)
304 {
305 	__load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
306 }
307 
308 /*
309  * Rewind PSW instruction address by specified number of bytes.
310  */
__rewind_psw(psw_t psw,unsigned long ilc)311 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
312 {
313 	unsigned long mask;
314 
315 	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
316 	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
317 					  (1UL << 24) - 1;
318 	return (psw.addr - ilc) & mask;
319 }
320 
321 /*
322  * Function to stop a processor until the next interrupt occurs
323  */
324 void enabled_wait(void);
325 
326 /*
327  * Function to drop a processor into disabled wait state
328  */
disabled_wait(unsigned long code)329 static inline void __noreturn disabled_wait(unsigned long code)
330 {
331 	psw_t psw;
332 
333 	psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
334 	psw.addr = code;
335 	__load_psw(psw);
336 	while (1);
337 }
338 
339 /*
340  * Basic Machine Check/Program Check Handler.
341  */
342 
343 extern void s390_base_mcck_handler(void);
344 extern void s390_base_pgm_handler(void);
345 extern void s390_base_ext_handler(void);
346 
347 extern void (*s390_base_mcck_handler_fn)(void);
348 extern void (*s390_base_pgm_handler_fn)(void);
349 extern void (*s390_base_ext_handler_fn)(void);
350 
351 #define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL
352 
353 extern int memcpy_real(void *, void *, size_t);
354 extern void memcpy_absolute(void *, void *, size_t);
355 
356 #define mem_assign_absolute(dest, val) {			\
357 	__typeof__(dest) __tmp = (val);				\
358 								\
359 	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));		\
360 	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));	\
361 }
362 
363 extern int s390_isolate_bp(void);
364 extern int s390_isolate_bp_guest(void);
365 
366 #endif /* __ASSEMBLY__ */
367 
368 #endif /* __ASM_S390_PROCESSOR_H */
369