| /arch/arc/include/asm/ |
| D | perf_event.h | 126 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
129 static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
130 [C(L1D)] = {
131 [C(OP_READ)] = {
132 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
133 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
135 [C(OP_WRITE)] = {
136 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
137 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
139 [C(OP_PREFETCH)] = {
[all …]
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| /arch/sh/kernel/cpu/sh4a/ |
| D | perf_event.c | 112 #define C(x) PERF_COUNT_HW_CACHE_##x macro
119 [ C(L1D) ] = {
120 [ C(OP_READ) ] = {
121 [ C(RESULT_ACCESS) ] = 0x0031,
122 [ C(RESULT_MISS) ] = 0x0032,
124 [ C(OP_WRITE) ] = {
125 [ C(RESULT_ACCESS) ] = 0x0039,
126 [ C(RESULT_MISS) ] = 0x003a,
128 [ C(OP_PREFETCH) ] = {
129 [ C(RESULT_ACCESS) ] = 0,
[all …]
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| /arch/sh/kernel/cpu/sh4/ |
| D | perf_event.c | 87 #define C(x) PERF_COUNT_HW_CACHE_##x macro
94 [ C(L1D) ] = {
95 [ C(OP_READ) ] = {
96 [ C(RESULT_ACCESS) ] = 0x0001,
97 [ C(RESULT_MISS) ] = 0x0004,
99 [ C(OP_WRITE) ] = {
100 [ C(RESULT_ACCESS) ] = 0x0002,
101 [ C(RESULT_MISS) ] = 0x0005,
103 [ C(OP_PREFETCH) ] = {
104 [ C(RESULT_ACCESS) ] = 0,
[all …]
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| /arch/x86/events/intel/ |
| D | p6.c | 27 [ C(L1D) ] = {
28 [ C(OP_READ) ] = {
29 [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
30 [ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */
32 [ C(OP_WRITE) ] = {
33 [ C(RESULT_ACCESS) ] = 0,
34 [ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */
36 [ C(OP_PREFETCH) ] = {
37 [ C(RESULT_ACCESS) ] = 0,
38 [ C(RESULT_MISS) ] = 0,
[all …]
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| D | core.c | 389 [ C(L1D ) ] = {
390 [ C(OP_READ) ] = {
391 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
392 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
394 [ C(OP_WRITE) ] = {
395 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
396 [ C(RESULT_MISS) ] = 0x0,
398 [ C(OP_PREFETCH) ] = {
399 [ C(RESULT_ACCESS) ] = 0x0,
400 [ C(RESULT_MISS) ] = 0x0,
[all …]
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| D | knc.c | 25 [ C(L1D) ] = {
26 [ C(OP_READ) ] = {
31 [ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT,
33 [ C(RESULT_MISS) ] = 0x0003, /* DATA_READ_MISS */
35 [ C(OP_WRITE) ] = {
36 [ C(RESULT_ACCESS) ] = 0x0001, /* DATA_WRITE */
37 [ C(RESULT_MISS) ] = 0x0004, /* DATA_WRITE_MISS */
39 [ C(OP_PREFETCH) ] = {
40 [ C(RESULT_ACCESS) ] = 0x0011, /* L1_DATA_PF1 */
41 [ C(RESULT_MISS) ] = 0x001c, /* L1_DATA_PF1_MISS */
[all …]
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| /arch/powerpc/perf/ |
| D | e6500-pmu.c | 32 #define C(x) PERF_COUNT_HW_CACHE_##x macro
39 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
40 [C(L1D)] = {
42 [C(OP_READ)] = { 27, 222 },
43 [C(OP_WRITE)] = { 28, 223 },
44 [C(OP_PREFETCH)] = { 29, 0 },
46 [C(L1I)] = {
48 [C(OP_READ)] = { 2, 254 },
49 [C(OP_WRITE)] = { -1, -1 },
50 [C(OP_PREFETCH)] = { 37, 0 },
[all …]
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| D | power9-pmu.c | 184 #define C(x) PERF_COUNT_HW_CACHE_##x macro
191 static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
192 [ C(L1D) ] = {
193 [ C(OP_READ) ] = {
194 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
195 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
197 [ C(OP_WRITE) ] = {
198 [ C(RESULT_ACCESS) ] = 0,
199 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
201 [ C(OP_PREFETCH) ] = {
[all …]
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| D | e500-pmu.c | 31 #define C(x) PERF_COUNT_HW_CACHE_##x macro
38 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
43 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
44 [C(OP_READ)] = { 27, 0 },
45 [C(OP_WRITE)] = { 28, 0 },
46 [C(OP_PREFETCH)] = { 29, 0 },
48 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
49 [C(OP_READ)] = { 2, 60 },
50 [C(OP_WRITE)] = { -1, -1 },
51 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
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| D | power8-pmu.c | 269 #define C(x) PERF_COUNT_HW_CACHE_##x macro
276 static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
277 [ C(L1D) ] = {
278 [ C(OP_READ) ] = {
279 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
280 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
282 [ C(OP_WRITE) ] = {
283 [ C(RESULT_ACCESS) ] = 0,
284 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
286 [ C(OP_PREFETCH) ] = {
[all …]
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| D | mpc7450-pmu.c | 354 #define C(x) PERF_COUNT_HW_CACHE_##x macro
361 static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
362 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
363 [C(OP_READ)] = { 0, 0x225 },
364 [C(OP_WRITE)] = { 0, 0x227 },
365 [C(OP_PREFETCH)] = { 0, 0 },
367 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
368 [C(OP_READ)] = { 0x129, 0x115 },
369 [C(OP_WRITE)] = { -1, -1 },
370 [C(OP_PREFETCH)] = { 0x634, 0 },
[all …]
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| D | power6-pmu.c | 480 #define C(x) PERF_COUNT_HW_CACHE_##x macro
488 static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
489 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
490 [C(OP_READ)] = { 0x280030, 0x80080 },
491 [C(OP_WRITE)] = { 0x180032, 0x80088 },
492 [C(OP_PREFETCH)] = { 0x810a4, 0 },
494 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
495 [C(OP_READ)] = { 0, 0x100056 },
496 [C(OP_WRITE)] = { -1, -1 },
497 [C(OP_PREFETCH)] = { 0x4008c, 0 },
[all …]
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| D | power7-pmu.c | 331 #define C(x) PERF_COUNT_HW_CACHE_##x macro
338 static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
339 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
340 [C(OP_READ)] = { 0xc880, 0x400f0 },
341 [C(OP_WRITE)] = { 0, 0x300f0 },
342 [C(OP_PREFETCH)] = { 0xd8b8, 0 },
344 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
345 [C(OP_READ)] = { 0, 0x200fc },
346 [C(OP_WRITE)] = { -1, -1 },
347 [C(OP_PREFETCH)] = { 0x408a, 0 },
[all …]
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| D | ppc970-pmu.c | 432 #define C(x) PERF_COUNT_HW_CACHE_##x macro
439 static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
440 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
441 [C(OP_READ)] = { 0x8810, 0x3810 },
442 [C(OP_WRITE)] = { 0x7810, 0x813 },
443 [C(OP_PREFETCH)] = { 0x731, 0 },
445 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
446 [C(OP_READ)] = { 0, 0 },
447 [C(OP_WRITE)] = { -1, -1 },
448 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
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| D | power4-pmu.c | 552 #define C(x) PERF_COUNT_HW_CACHE_##x macro
559 static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
560 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
561 [C(OP_READ)] = { 0x8c10, 0x3c10 },
562 [C(OP_WRITE)] = { 0x7c10, 0xc13 },
563 [C(OP_PREFETCH)] = { 0xc35, 0 },
565 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
566 [C(OP_READ)] = { 0, 0 },
567 [C(OP_WRITE)] = { -1, -1 },
568 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
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| /arch/arm/kernel/ |
| D | perf_event_v7.c | 178 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
179 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
180 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
181 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
183 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
184 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
186 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
187 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
188 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
189 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
[all …]
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| D | perf_event_v6.c | 95 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
96 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
97 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
98 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
100 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
108 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
109 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
111 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
112 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
158 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
[all …]
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| /arch/arm64/kernel/ |
| D | perf_event.c | 259 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
260 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
261 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
262 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
264 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
265 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
267 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
268 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
270 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
271 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
[all …]
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| /arch/sparc/kernel/ |
| D | perf_event.c | 145 #define C(x) PERF_COUNT_HW_CACHE_##x macro
219 [C(L1D)] = {
220 [C(OP_READ)] = {
221 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
222 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
224 [C(OP_WRITE)] = {
225 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
226 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
228 [C(OP_PREFETCH)] = {
229 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
[all …]
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| /arch/blackfin/kernel/ |
| D | perf_event.c | 81 #define C(x) PERF_COUNT_HW_CACHE_##x macro
87 [C(L1D)] = { /* Data bank A */
88 [C(OP_READ)] = {
89 [C(RESULT_ACCESS)] = 0,
90 [C(RESULT_MISS) ] = 0x9A,
92 [C(OP_WRITE)] = {
93 [C(RESULT_ACCESS)] = 0,
94 [C(RESULT_MISS) ] = 0,
96 [C(OP_PREFETCH)] = {
97 [C(RESULT_ACCESS)] = 0,
[all …]
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| /arch/tile/kernel/ |
| D | perf_event.c | 116 #define C(x) PERF_COUNT_HW_CACHE_##x macro
129 [C(L1D)] = {
130 [C(OP_READ)] = {
131 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
132 [C(RESULT_MISS)] = 0x21, /* RD_MISS */
134 [C(OP_WRITE)] = {
135 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
136 [C(RESULT_MISS)] = 0x22, /* WR_MISS */
138 [C(OP_PREFETCH)] = {
139 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
[all …]
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| /arch/mips/kernel/ |
| D | perf_event_mipsxx.c | 83 #define C(x) PERF_COUNT_HW_CACHE_##x macro
874 [C(L1D)] = {
881 [C(OP_READ)] = {
882 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
883 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
885 [C(OP_WRITE)] = {
886 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
887 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
890 [C(L1I)] = {
891 [C(OP_READ)] = {
[all …]
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| /arch/x86/events/amd/ |
| D | core.c | 15 [ C(L1D) ] = {
16 [ C(OP_READ) ] = {
17 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
18 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
20 [ C(OP_WRITE) ] = {
21 [ C(RESULT_ACCESS) ] = 0,
22 [ C(RESULT_MISS) ] = 0,
24 [ C(OP_PREFETCH) ] = {
25 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
26 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
[all …]
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| /arch/metag/kernel/perf/ |
| D | perf_event.c | 401 static const int metag_pmu_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
402 [C(L1D)] = {
403 [C(OP_READ)] = {
404 [C(RESULT_ACCESS)] = 0x08,
405 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
407 [C(OP_WRITE)] = {
408 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
409 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
411 [C(OP_PREFETCH)] = {
412 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[all …]
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| /arch/frv/include/asm/ |
| D | irc-regs.h | 31 #define __get_RS(C) ({ (__reg(0xfeff9810) >> ((C)+16)) & 1; }) argument
33 #define __clr_RC(C) do { __reg(0xfeff9818) = 1 << ((C)+16); mb(); } while(0) argument
35 #define __get_MASK(C) ({ (__reg(0xfeff9820) >> ((C)+16)) & 1; }) argument
36 #define __set_MASK(C) do { __reg(0xfeff9820) |= 1 << ((C)+16); mb(); } while(0) argument
37 #define __clr_MASK(C) do { __reg(0xfeff9820) &= ~(1 << ((C)+16)); mb(); } while(0) argument
|