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Searched refs:D1Ar3 (Results 1 – 23 of 23) sorted by relevance

/arch/metag/tbx/
Dtbidefr.S51 MOV D1Ar3, D1.5
52 ANDT D1Ar3, D1Ar3, #HI(0xFFFF0000)
53 OR D0Ar4, D1Ar3, #TXSTAT_DEFER_BIT
57 ANDT D1Ar3, D1Ar3, #HI(TXSTAT_BUSERR_BIT | TXSTAT_FPE_BITS)
71 FFB D1Ar3, D1Ar3
72 CMP D1Ar3, #TXSTAT_FPE_INVALID_S
73 MOVLE D1Ar3, D1RtP /* Collapse FPE triggers to a single signal */
75 LSLGT D1Re0, D1RtP, D1Ar3
84 SUB D1Ar3, D1Ar3, #(TXSTAT_FPE_INVALID_S - TBID_SIGNUM_FPE)
85 LSL D0Re0, D1Ar3, #2
[all …]
Dtbipcx.S144 MOV D1Ar3,TXBPOBITS
175 MOV D1Ar3,TXDIVTIME /* Read IRQEnc bits */
183 ANDT D1Ar3,D1Ar3,#HI(TXDIVTIME_IRQENC_BITS)
184 LSR D1Ar3,D1Ar3,#TXDIVTIME_IRQENC_S
204 LSL TXSTATI,D1Ar1,D1Ar3 /* Acknowledge trigger */
207 ADD D1Ar3,D1Ar3,#TBID_SIGNUM_TRT /* Offset into interrupt sigs */
208 LSL D0Re0,D1Ar3,#TBID_SIGNUM_S /* Generate offset from SigNum */
260 MOV D1Ar3,A1.3 /* Copy old TXDIVTIME */
263 ANDST D1Ar3,D1Ar3,#HI(TXDIVTIME_RPMASK_BITS)/* !Z if RPDIRTY */
271 LSRS D1Ar3,D1Ar3,#TXDIVTIME_RPMASK_S+1 /* 2nd RPMASK bit -> bit 0 */
[all …]
Dtbictxfpu.S59 SETD [D1Ar3++], D0Ar4
73 SETD [D1Ar3++], D0Ar6
82 F MSETL [D1Ar3++], FX.0, FX.2, FX.4, FX.6
86 F MSETL [D1Ar3++], FX.8, FX.10, FX.12, FX.14
92 F SETL [D1Ar3++], ACF.0
93 F SETL [D1Ar3++], ACF.1
94 F SETL [D1Ar3++], ACF.2
102 MOV D0Re0, D1Ar3 /* Return end of save area */
139 GETD D0Ar4, [D1Ar3++]
142 GETD D1Ar5, [D1Ar3++]
[all …]
Dtbitimer.S94 ADD D1Re0,D1Ar3,D1Ar5 /* to 64-bit signed extend time */
121 ADD D1Ar3,D1Ar3,D1Re0 /* ... real timer ... */
122 ADDCS D1Ar3,D1Ar3,#1 /* ... with carry */
123 SETL [A0.3],D0Ar4,D1Ar3 /* Update ___TBITime(B/I) */
153 ADD D1Ar3,D1Ar3,D1Re0 /* ... real timer ... */
154 ADDCS D1Ar3,D1Ar3,#1 /* ... with carry */
155 SETL [A0.3],D0Ar4,D1Ar3 /* Update ___TBITime(B/I) */
201 GETL D0Ar4,D1Ar3,[A0.3] /* Read ___TBITime(B/I) */
Dtbicore.S59 GETL D1Ar3,D0Ar4,[A1LbP] /* Read segment list head */
66 MOVNZ D1Ar3,D1Ar1 /* Use pStart if provided */
68 ADDS D0Re0,D1Ar3,#0 /* End of list? Load result into D0Re0 */
70 GETL D1Ar3,D0Ar4,[D1Ar3] /* Read pLink and Id */
Dtbisoft.S84 SETD [D1Ar3],A0StP /* Record pCtx of this thread */
135 OR TXMASKI,D1Ar5,D1Ar3 /* New TXMASKI */
208 MOV D1Ar3,A1LbP /* Same A1LbP */
Dtbictx.S103 MOV A0.2,D1Ar3 /* Save pointer into A0.2 */
257 MOV D0Re0,D1Ar3 /* D1Ar3 is default result */
299 MOV TXL2END,D1Ar3
/arch/metag/kernel/
Duser_gateway.S41 MOV D1Ar3,TXENABLE
42 AND D1Ar3,D1Ar3,#(TXENABLE_THREAD_BITS)
43 LSR D1Ar3,D1Ar3,#(TXENABLE_THREAD_S - 2)
44 GETD D0Re0,[D1Ar1+D1Ar3]
70 0: LNKGETD D0Re0,[D1Ar3]
72 LNKSETDZ [D1Ar3],D0Ar2
79 DCACHE [D1Ar3], D0Re0
85 GETD D0Re0,[D1Ar3]
87 SETDZ [D1Ar3],D0Ar2
Dftrace_stub.S30 GETL D0Ar4, D1Ar3, [A0StP++#(-8)]
43 GET D1Ar3,[D0Re0]
46 CMP D1Ar3,D1Re0
48 MOV D1RtP,D1Ar3
54 GETL D0Ar4, D1Ar3, [A0StP++#(-8)]
Dhead.S15 ! D1Ar3 contains __pTBISegs
23 SETD [D0Re0],D1Ar3
27 MOV D1Ar3,#0
/arch/metag/lib/
Dashrdi3.S13 CMP D1Ar3,#0 ! COUNT == 0
16 MOV D0Ar4,D1Ar3
17 SUBS D1Ar3,D1Ar3,#32 ! N = COUNT - 32
21 NEG D1Ar3,D1Ar3 ! N = - N
23 LSL D0Ar6,D1Re0,D1Ar3 ! TMP= HI << -(COUNT - 32)
25 SWAP D1Ar3,D0Ar4
26 ASR D1Re0,D1Re0,D1Ar3 ! HI = HI >> COUNT
30 ASR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
Dlshrdi3.S13 CMP D1Ar3,#0 ! COUNT == 0
16 MOV D0Ar4,D1Ar3
17 SUBS D1Ar3,D1Ar3,#32 ! N = COUNT - 32
21 NEG D1Ar3,D1Ar3 ! N = - N
23 LSL D0Ar6,D1Re0,D1Ar3 ! TMP= HI << -(COUNT - 32)
25 SWAP D1Ar3,D0Ar4
26 LSR D1Re0,D1Re0,D1Ar3 ! HI = HI >> COUNT
30 LSR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
Ddiv64.S12 ORS A0.3,D1Ar3,D0Ar4
19 CMP D1Ar3,D1Ar1
26 ADD D1Ar5,D1Ar3,D1Ar3
28 CMP D1Ar5,D1Ar3
33 MOV D1Ar3,D1Ar5
37 CMP D1Ar3,D1Ar1
46 CMP D1Ar1,D1Ar3
55 SUB D1Ar1,D1Ar1,D1Ar3
62 LSL A0.3,D1Ar3,#31
64 LSR D1Ar3,D1Ar3,#1
[all …]
Dmemmove.S8 ! D1Ar3 cnt
11 CMP D1Ar3, #0
18 SUB D0Ar4, D1Ar1, D1Ar3
25 ADD D0Ar2, D1Re0, D1Ar3
26 ADD D1Ar1, D1Ar1, D1Ar3
30 CMP D1Ar3, #8
43 LSR D1Ar5, D1Ar3, #3
51 ANDS D1Ar3, D1Ar3, #7
56 SUBS D1Ar3, D1Ar3, #1
71 SUB D1Ar3, D1Ar3, #1
[all …]
Dmemset.S8 ! D1Ar3 cnt
23 CMP D1Ar3,D1Ar5
24 MOVMI D1Ar5,D1Ar3
31 LSRS D0Ar2,D1Ar3,#5
32 AND D1Ar3,D1Ar3,#0x1F
36 CMP D1Ar3,#0
48 LSRS D0Ar2,D1Ar3,#3
49 AND D1Ar3,D1Ar3,#0x7
50 MOV D1Ar5,D1Ar3
53 CMP D1Ar3,#0
[all …]
Ddivsi3.S38 LSR D1Ar3,D1Ar1,#2 ! Calculate (Au & (~3)) >> 2
39 CMPHI D1Re0,D1Ar3 ! OR ( (Au & (~3)) <= (Bu << 2) )?
40 LSLSHI D1Ar3,D1Re0,#1 ! Buq = Bu << 1
46 CMP D1Ar1,D1Ar3 ! ( A >= Buq )?
48 SUBCC D1Ar1,D1Ar1,D1Ar3 ! and A -= Buq
76 FFB D1Ar3,D1Re0 ! Find first bit of Bu
77 ANDN D1Ar3,D1Ar3,#31 ! Handle exceptional case.
78 ORN D1Ar3,D1Ar3,#31 ! if N bit set, set to 31
79 SUBS D1Ar3,D1Ar5,D1Ar3 ! calculate diff, ffbA - ffbB
80 MOV D0Ar2,D1Ar3 ! copy into bank 0
[all …]
Dashldi3.S13 CMP D1Ar3,#0 ! COUNT == 0
16 SUBS D0Ar4,D1Ar3,#32 ! N = COUNT - 32
21 LSL D1Re0,D1Re0,D1Ar3 ! HI = HI << COUNT
24 SWAP D0Ar4,D1Ar3
Dmemcpy.S8 ! D1Ar3 cnt
11 CMP D1Ar3, #16
20 SUBS TXRPT, D1Ar3, #1
43 SUB D1Ar3, D1Ar3, #1 ! decrement count of remaining bytes
53 LSR D1Ar5, D1Ar3, #3 ! D1Ar5 = number of 8 byte blocks
59 LSRS D1Ar5, D1Ar3, #5 ! D1Ar5 = number of 32 byte blocks
75 ANDS D1Ar3, D1Ar3, #0x1f
176 ANDS D1Ar3, D1Ar3, #7
Ducmpdi2.S12 ! u64 b (D0Ar4, D1Ar3)
18 CMP D1Ar1,D1Ar3
Dip_fast_csum.S18 GETD D1Ar3,[D1Ar1++]
19 ADDS D0Re0,D0Re0,D1Ar3
Dcmpdi2.S12 ! s64 b (D0Ar4, D1Ar3)
18 CMP D1Ar1,D1Ar3
Dmuldi3.S11 ! B = D1Ar3:D0Ar4 = w 2^48 + x 2^32 + y 2^16 + z 2^0
19 MULD D0Re0,D0Ar2,D1Ar3 ! (w 2^48 + x 2^32)(c 2^16 + d 2^0)
/arch/metag/include/asm/
Dmetag_regs.h111 #define D1Ar3 D1.2 macro