1! Copyright (C) 2012 Imagination Technologies Ltd. 2! 3! Signed/unsigned 64-bit division routines. 4! 5 6 .text 7 .global _div_u64 8 .type _div_u64,function 9 10_div_u64: 11$L1: 12 ORS A0.3,D1Ar3,D0Ar4 13 BNE $L3 14$L2: 15 MOV D0Re0,D0Ar2 16 MOV D1Re0,D1Ar1 17 MOV PC,D1RtP 18$L3: 19 CMP D1Ar3,D1Ar1 20 CMPEQ D0Ar4,D0Ar2 21 MOV D0Re0,#1 22 MOV D1Re0,#0 23 BHS $L6 24$L4: 25 ADDS D0Ar6,D0Ar4,D0Ar4 26 ADD D1Ar5,D1Ar3,D1Ar3 27 ADDCS D1Ar5,D1Ar5,#1 28 CMP D1Ar5,D1Ar3 29 CMPEQ D0Ar6,D0Ar4 30 BLO $L6 31$L5: 32 MOV D0Ar4,D0Ar6 33 MOV D1Ar3,D1Ar5 34 ADDS D0Re0,D0Re0,D0Re0 35 ADD D1Re0,D1Re0,D1Re0 36 ADDCS D1Re0,D1Re0,#1 37 CMP D1Ar3,D1Ar1 38 CMPEQ D0Ar4,D0Ar2 39 BLO $L4 40$L6: 41 ORS A0.3,D1Re0,D0Re0 42 MOV D0Ar6,#0 43 MOV D1Ar5,D0Ar6 44 BEQ $L10 45$L7: 46 CMP D1Ar1,D1Ar3 47 CMPEQ D0Ar2,D0Ar4 48 BLO $L9 49$L8: 50 ADDS D0Ar6,D0Ar6,D0Re0 51 ADD D1Ar5,D1Ar5,D1Re0 52 ADDCS D1Ar5,D1Ar5,#1 53 54 SUBS D0Ar2,D0Ar2,D0Ar4 55 SUB D1Ar1,D1Ar1,D1Ar3 56 SUBCS D1Ar1,D1Ar1,#1 57$L9: 58 LSL A0.3,D1Re0,#31 59 LSR D0Re0,D0Re0,#1 60 LSR D1Re0,D1Re0,#1 61 OR D0Re0,D0Re0,A0.3 62 LSL A0.3,D1Ar3,#31 63 LSR D0Ar4,D0Ar4,#1 64 LSR D1Ar3,D1Ar3,#1 65 OR D0Ar4,D0Ar4,A0.3 66 ORS A0.3,D1Re0,D0Re0 67 BNE $L7 68$L10: 69 MOV D0Re0,D0Ar6 70 MOV D1Re0,D1Ar5 71 MOV PC,D1RtP 72 .size _div_u64,.-_div_u64 73 74 .text 75 .global _div_s64 76 .type _div_s64,function 77_div_s64: 78 MSETL [A0StP],D0FrT,D0.5 79 XOR D0.5,D0Ar2,D0Ar4 80 XOR D1.5,D1Ar1,D1Ar3 81 TSTT D1Ar1,#HI(0x80000000) 82 BZ $L25 83 84 NEGS D0Ar2,D0Ar2 85 NEG D1Ar1,D1Ar1 86 SUBCS D1Ar1,D1Ar1,#1 87$L25: 88 TSTT D1Ar3,#HI(0x80000000) 89 BZ $L27 90 91 NEGS D0Ar4,D0Ar4 92 NEG D1Ar3,D1Ar3 93 SUBCS D1Ar3,D1Ar3,#1 94$L27: 95 CALLR D1RtP,_div_u64 96 TSTT D1.5,#HI(0x80000000) 97 BZ $L29 98 99 NEGS D0Re0,D0Re0 100 NEG D1Re0,D1Re0 101 SUBCS D1Re0,D1Re0,#1 102$L29: 103 104 GETL D0FrT,D1RtP,[A0StP+#(-16)] 105 GETL D0.5,D1.5,[A0StP+#(-8)] 106 SUB A0StP,A0StP,#16 107 MOV PC,D1RtP 108 .size _div_s64,.-_div_s64 109