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Searched refs:FPU_CSR_RD (Results 1 – 16 of 16) sorted by relevance

/arch/mips/math-emu/
Ddp_simple.c35 ieee754_csr.rm = FPU_CSR_RD; in ieee754dp_neg()
53 ieee754_csr.rm = FPU_CSR_RD; in ieee754dp_abs()
Dsp_simple.c35 ieee754_csr.rm = FPU_CSR_RD; in ieee754sp_neg()
53 ieee754_csr.rm = FPU_CSR_RD; in ieee754sp_abs()
Dieee754sp.c84 case FPU_CSR_RD: /* toward -Infinity */ in ieee754sp_get_rounding()
123 case FPU_CSR_RD: /* toward -Infinity */ in ieee754sp_format()
187 case FPU_CSR_RD: /* toward -Infinity */ in ieee754sp_format()
Dieee754dp.c84 case FPU_CSR_RD: /* toward -Infinity */ in ieee754dp_get_rounding()
123 case FPU_CSR_RD: /* toward -Infinity */ in ieee754dp_format()
188 case FPU_CSR_RD: /* toward -Infinity */ in ieee754dp_format()
Dsp_sub.c95 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD); in ieee754sp_sub()
166 if (ieee754_csr.rm == FPU_CSR_RD) in ieee754sp_sub()
Ddp_add.c95 return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD); in ieee754dp_add()
167 return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD); in ieee754dp_add()
Dsp_add.c95 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD); in ieee754sp_add()
166 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD); in ieee754sp_add()
Ddp_sub.c95 return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD); in ieee754dp_sub()
170 if (ieee754_csr.rm == FPU_CSR_RD) in ieee754dp_sub()
Dsp_fdp.c70 (ieee754_csr.rm == FPU_CSR_RD && xs)) in ieee754sp_fdp()
Dsp_maddf.c122 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD); in _sp_maddf()
233 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD); in _sp_maddf()
Dsp_tlong.c92 case FPU_CSR_RD: /* toward -Infinity */ in ieee754sp_tlong()
Ddp_tint.c90 case FPU_CSR_RD: /* toward -Infinity */ in ieee754dp_tint()
Dsp_tint.c95 case FPU_CSR_RD: /* toward -Infinity */ in ieee754sp_tint()
Ddp_tlong.c95 case FPU_CSR_RD: /* toward -Infinity */ in ieee754dp_tlong()
Ddp_maddf.c153 return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD); in _dp_maddf()
296 return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD); in _dp_maddf()
/arch/mips/include/asm/
Dmipsregs.h1052 #define FPU_CSR_RD 0x3 /* towards -Infinity */ macro