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Searched refs:M (Results 1 – 25 of 191) sorted by relevance

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/arch/mips/mm/
Duasm-mips.c33 #define M(a, b, c, d, e, f) \ macro
52 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
53 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
54 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
55 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
56 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
57 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
58 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
59 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
60 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
[all …]
Duasm-micromips.c33 #define M(a, b, c, d, e, f) \ macro
44 { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD },
45 { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
46 { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD },
47 { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
48 { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
50 { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM },
52 { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM },
54 { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM },
55 { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM },
[all …]
/arch/sparc/kernel/
Dtraps_64.c1069 #define M 147 macro
1071 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1072 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1073 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1074 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1075 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1076 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1077 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1078 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1079 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
[all …]
/arch/m68k/fpsp040/
Dstwotox.S31 | N = 64(M + M') + j, j = 0,1,2,...,63.
34 | 2**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r).
44 | N = 64(M + M') + j, j = 0,1,2,...,63.
50 | 10**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r).
57 | Fact1 := 2**(M) * Fact1
58 | Fact2 := 2**(M) * Fact2
59 | Thus Fact1 + Fact2 = 2**(M) * 2**(j/64).
64 | 4. Let AdjFact := 2**(M'). Return
243 asrl #1,%d0 | ...D0 IS M
244 subl %d0,%d2 | ...d2 IS M', N = 64(M+M') + J
[all …]
Dsetox.S83 | 2.4 Calculate M = (N - J)/64; so N = 64M + J.
85 | 2.6 Create the value Scale = 2^M.
153 | exp(X) = 2^M * 2^(J/64) * exp(R).
159 | |M| <= 16380, and Scale = 2^M. Moreover, exp(X) will
162 | X = (M1+M)log2 + Jlog2/64 + R, |M1+M| >= 16380.
165 | approximately M. Thus 6.2 will never cause over/underflow.
190 | 8.4 K := (N-J)/64, M1 := truncate(K/2), M = K-M1, AdjFlag := 1.
192 | 8.6 Create the values Scale = 2^M, AdjScale = 2^M1.
496 asrl #6,%d0 | ...D0 is M
497 addiw #0x3FFF,%d0 | ...biased expo. of 2^(M)
[all …]
/arch/arm/boot/dts/
Dste-nomadik-stn8815.dtsi197 mxtal: mxtal@19.2M {
209 timclk: timclk@2.4M {
247 clk216: clk216@216M {
254 clk108: clk108@108M {
261 clk72: clk72@72M {
269 clk48: clk48@48M {
277 clk27: clk27@27M {
286 ulpiclk: ulpiclk@60M {
297 hclkdma0: hclkdma0@48M {
303 hclksmc: hclksmc@48M {
[all …]
Dste-u300.dts41 pll13: pll13@13M {
47 slow_clk: slow_clk@13M {
54 uart0_clk: uart0_clk@13M {
61 gpio_clk: gpio_clk@13M {
68 rtc_clk: rtc_clk@13M {
75 apptimer_clk: app_tmr_clk@13M {
82 acc_tmr_clk@13M {
89 pll208: pll208@208M {
94 app208: app_208_clk@208M {
101 cpu_clk@208M {
[all …]
Dintegratorcp.dts23 xtal_codec: xtal24.576@24.576M {
30 aaci_bitclk: aaci_bitclk@12.288M {
39 xtal25mhz: xtal25mhz@25M {
46 uartclk: uartclk@14.74M {
61 cm24mhz: cm24mhz@24M {
68 cmcore: cmosc@24M {
77 cmmem: cmosc@24M {
86 auxosc: auxosc@24M {
95 kmiclk: kmiclk@1M {
104 timclk: timclk@1M {
Dintegratorap.dts23 xtal24mhz: xtal24mhz@24M {
38 uartclk: uartclk@14.74M {
47 cm24mhz: cm24mhz@24M {
54 cmosc: cmosc@24M {
63 auxosc: auxosc@24M {
83 sysclk: apsys@24M {
92 pciclk: pciclk@24M {
/arch/mips/include/asm/
Dmips-r2-to-r6-emul.h46 #define MIPS_R2_STATS(M) \ argument
52 __this_cpu_inc(mipsr2emustats.M); \
56 __this_cpu_inc(mipsr2bdemustats.M); \
61 #define MIPS_R2BR_STATS(M) \ argument
64 __this_cpu_inc(mipsr2bremustats.M); \
70 #define MIPS_R2_STATS(M) do { } while (0) argument
71 #define MIPS_R2BR_STATS(M) do { } while (0) argument
Dfpu_emulator.h52 #define MIPS_FPU_EMU_INC_STATS(M) \ argument
55 __this_cpu_inc(fpuemustats.M); \
60 #define MIPS_FPU_EMU_INC_STATS(M) do { } while (0) argument
/arch/mips/sgi-ip27/
DKconfig7 bool "IP27 M-Mode"
10 in either N-Modes which allows for more nodes or M-Mode which allows
12 M-Mode, so choose M-mode here.
18 in either N-Modes which allows for more nodes or M-Mode which allows
20 M-Mode, so choose M-mode here.
/arch/ia64/kernel/
Dkprobes.c45 enum instruction_type {A, I, M, F, B, L, X, u}; enumerator
47 { M, I, I }, /* 00 */
48 { M, I, I }, /* 01 */
49 { M, I, I }, /* 02 */
50 { M, I, I }, /* 03 */
51 { M, L, X }, /* 04 */
52 { M, L, X }, /* 05 */
55 { M, M, I }, /* 08 */
56 { M, M, I }, /* 09 */
57 { M, M, I }, /* 0A */
[all …]
/arch/mips/boot/dts/netlogic/
Dxlp_rvp.dts46 reg = <0x0 0x100000>; /* 1M */
52 reg = <0x100000 0x100000>; /* 1M */
57 reg = <0x200000 0x500000>; /* 5M */
62 reg = <0x700000 0x800000>; /* 8M */
67 reg = <0xf00000 0x100000>; /* 1M */
Dxlp_gvp.dts46 reg = <0x0 0x100000>; /* 1M */
52 reg = <0x100000 0x100000>; /* 1M */
57 reg = <0x200000 0x500000>; /* 5M */
62 reg = <0x700000 0x800000>; /* 8M */
67 reg = <0xf00000 0x100000>; /* 1M */
Dxlp_evp.dts88 reg = <0x0 0x100000>; /* 1M */
94 reg = <0x100000 0x100000>; /* 1M */
99 reg = <0x200000 0x500000>; /* 5M */
104 reg = <0x700000 0x800000>; /* 8M */
109 reg = <0xf00000 0x100000>; /* 1M */
Dxlp_fvp.dts88 reg = <0x0 0x100000>; /* 1M */
94 reg = <0x100000 0x100000>; /* 1M */
99 reg = <0x200000 0x500000>; /* 5M */
104 reg = <0x700000 0x800000>; /* 8M */
109 reg = <0xf00000 0x100000>; /* 1M */
Dxlp_svp.dts88 reg = <0x0 0x100000>; /* 1M */
94 reg = <0x100000 0x100000>; /* 1M */
99 reg = <0x200000 0x500000>; /* 5M */
104 reg = <0x700000 0x800000>; /* 8M */
109 reg = <0xf00000 0x100000>; /* 1M */
/arch/frv/kernel/
Dirq-mb93093.c30 #define __set_IMR(M) do { __reg16(0x0a) = (M); wmb(); } while(0) argument
32 #define __clr_IFR(M) do { __reg16(0x02) = ~(M); wmb(); } while(0) argument
Dirq-mb93091.c30 #define __set_IMR(M) do { __reg16(0xffc00004) = (M); wmb(); } while(0) argument
32 #define __clr_IFR(M) do { __reg16(0xffc0000c) = ~(M); wmb(); } while(0) argument
/arch/arm/include/asm/
Dhw_breakpoint.h105 #define ARM_DBG_READ(N, M, OP2, VAL) do {\ argument
106 asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
109 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\ argument
110 asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
/arch/arm/configs/
Dneponset_defconfig18 …parts=sa1100:512K(boot),1M(kernel),2560K(initrd),4M(root) load_ramdisk=1 prompt_ramdisk=0 mem=32M …
Dpleb_defconfig16 CONFIG_CMDLINE="console=ttySA0,9600 mem=16M@0xc0000000 mem=16M@0xc8000000 root=/dev/ram initrd=0xc0…
/arch/blackfin/lib/
Dsmulsi3_highpart.S19 R3 = R1.H * R0.L (IS,M);
20 R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M);
/arch/frv/lib/
D__lshrdi3.S31 csub gr5,gr10,gr5 ,cc4,#1 ; M = 32 - N
34 cor.p gr4,gr9,gr9 ,cc4,#1 ; LSW |= MSW << M

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