1/* 2 * Device Tree for the ARM Integrator/CP platform 3 */ 4 5/dts-v1/; 6/include/ "integrator.dtsi" 7 8/ { 9 model = "ARM Integrator/CP"; 10 compatible = "arm,integrator-cp"; 11 12 chosen { 13 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; 14 }; 15 16 /* 17 * The Integrator/CP overall clocking architecture can be found in 18 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which 19 * appear to illustrate the layout used in most configurations. 20 */ 21 22 /* The codec chrystal operates at 24.576 MHz */ 23 xtal_codec: xtal24.576@24.576M { 24 #clock-cells = <0>; 25 compatible = "fixed-clock"; 26 clock-frequency = <24576000>; 27 }; 28 29 /* The chrystal is divided by 2 by the codec for the AACI bit clock */ 30 aaci_bitclk: aaci_bitclk@12.288M { 31 #clock-cells = <0>; 32 compatible = "fixed-factor-clock"; 33 clock-div = <2>; 34 clock-mult = <1>; 35 clocks = <&xtal_codec>; 36 }; 37 38 /* This is a 25MHz chrystal on the base board */ 39 xtal25mhz: xtal25mhz@25M { 40 #clock-cells = <0>; 41 compatible = "fixed-clock"; 42 clock-frequency = <25000000>; 43 }; 44 45 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ 46 uartclk: uartclk@14.74M { 47 #clock-cells = <0>; 48 compatible = "fixed-clock"; 49 clock-frequency = <14745600>; 50 }; 51 52 /* Actually sysclk I think */ 53 pclk: pclk@0 { 54 #clock-cells = <0>; 55 compatible = "fixed-clock"; 56 clock-frequency = <0>; 57 }; 58 59 core-module@10000000 { 60 /* 24 MHz chrystal on the core module */ 61 cm24mhz: cm24mhz@24M { 62 #clock-cells = <0>; 63 compatible = "fixed-clock"; 64 clock-frequency = <24000000>; 65 }; 66 67 /* Oscillator on the core module, clocks the CPU core */ 68 cmcore: cmosc@24M { 69 compatible = "arm,syscon-icst525-integratorcp-cm-core"; 70 #clock-cells = <0>; 71 lock-offset = <0x14>; 72 vco-offset = <0x08>; 73 clocks = <&cm24mhz>; 74 }; 75 76 /* Oscillator on the core module, clocks the memory bus */ 77 cmmem: cmosc@24M { 78 compatible = "arm,syscon-icst525-integratorcp-cm-mem"; 79 #clock-cells = <0>; 80 lock-offset = <0x14>; 81 vco-offset = <0x08>; 82 clocks = <&cm24mhz>; 83 }; 84 85 /* Auxilary oscillator on the core module, clocks the CLCD */ 86 auxosc: auxosc@24M { 87 compatible = "arm,syscon-icst525"; 88 #clock-cells = <0>; 89 lock-offset = <0x14>; 90 vco-offset = <0x1c>; 91 clocks = <&cm24mhz>; 92 }; 93 94 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ 95 kmiclk: kmiclk@1M { 96 #clock-cells = <0>; 97 compatible = "fixed-factor-clock"; 98 clock-div = <3>; 99 clock-mult = <1>; 100 clocks = <&cm24mhz>; 101 }; 102 103 /* The timer clock is the 24 MHz oscillator divided to 1MHz */ 104 timclk: timclk@1M { 105 #clock-cells = <0>; 106 compatible = "fixed-factor-clock"; 107 clock-div = <24>; 108 clock-mult = <1>; 109 clocks = <&cm24mhz>; 110 }; 111 }; 112 113 syscon { 114 compatible = "arm,integrator-cp-syscon", "syscon"; 115 reg = <0xcb000000 0x100>; 116 }; 117 118 timer0: timer@13000000 { 119 /* TIMER0 runs directly on the 25MHz chrystal */ 120 compatible = "arm,integrator-cp-timer"; 121 clocks = <&xtal25mhz>; 122 }; 123 124 timer1: timer@13000100 { 125 /* TIMER1 runs @ 1MHz */ 126 compatible = "arm,integrator-cp-timer"; 127 clocks = <&timclk>; 128 }; 129 130 timer2: timer@13000200 { 131 /* TIMER2 runs @ 1MHz */ 132 compatible = "arm,integrator-cp-timer"; 133 clocks = <&timclk>; 134 }; 135 136 pic: pic@14000000 { 137 valid-mask = <0x1fc003ff>; 138 }; 139 140 cic: cic@10000040 { 141 compatible = "arm,versatile-fpga-irq"; 142 #interrupt-cells = <1>; 143 interrupt-controller; 144 reg = <0x10000040 0x100>; 145 clear-mask = <0xffffffff>; 146 valid-mask = <0x00000007>; 147 }; 148 149 /* The SIC is cascaded off IRQ 26 on the PIC */ 150 sic: sic@ca000000 { 151 compatible = "arm,versatile-fpga-irq"; 152 interrupt-parent = <&pic>; 153 interrupts = <26>; 154 #interrupt-cells = <1>; 155 interrupt-controller; 156 reg = <0xca000000 0x100>; 157 clear-mask = <0x00000fff>; 158 valid-mask = <0x00000fff>; 159 }; 160 161 ethernet@c8000000 { 162 compatible = "smsc,lan91c111"; 163 reg = <0xc8000000 0x10>; 164 interrupt-parent = <&pic>; 165 interrupts = <27>; 166 }; 167 168 fpga { 169 /* 170 * These PrimeCells are at the same location and using 171 * the same interrupts in all Integrators, but in the CP 172 * slightly newer versions are deployed. 173 */ 174 rtc@15000000 { 175 compatible = "arm,pl031", "arm,primecell"; 176 clocks = <&pclk>; 177 clock-names = "apb_pclk"; 178 }; 179 180 uart@16000000 { 181 compatible = "arm,pl011", "arm,primecell"; 182 clocks = <&uartclk>, <&pclk>; 183 clock-names = "uartclk", "apb_pclk"; 184 }; 185 186 uart@17000000 { 187 compatible = "arm,pl011", "arm,primecell"; 188 clocks = <&uartclk>, <&pclk>; 189 clock-names = "uartclk", "apb_pclk"; 190 }; 191 192 kmi@18000000 { 193 compatible = "arm,pl050", "arm,primecell"; 194 clocks = <&kmiclk>, <&pclk>; 195 clock-names = "KMIREFCLK", "apb_pclk"; 196 }; 197 198 kmi@19000000 { 199 compatible = "arm,pl050", "arm,primecell"; 200 clocks = <&kmiclk>, <&pclk>; 201 clock-names = "KMIREFCLK", "apb_pclk"; 202 }; 203 204 /* 205 * These PrimeCells are only available on the Integrator/CP 206 */ 207 mmc@1c000000 { 208 compatible = "arm,pl180", "arm,primecell"; 209 reg = <0x1c000000 0x1000>; 210 interrupts = <23 24>; 211 max-frequency = <515633>; 212 clocks = <&uartclk>, <&pclk>; 213 clock-names = "mclk", "apb_pclk"; 214 }; 215 216 aaci@1d000000 { 217 compatible = "arm,pl041", "arm,primecell"; 218 reg = <0x1d000000 0x1000>; 219 interrupts = <25>; 220 clocks = <&pclk>; 221 clock-names = "apb_pclk"; 222 }; 223 224 clcd@c0000000 { 225 compatible = "arm,pl110", "arm,primecell"; 226 reg = <0xC0000000 0x1000>; 227 interrupts = <22>; 228 clocks = <&auxosc>, <&pclk>; 229 clock-names = "clcdclk", "apb_pclk"; 230 231 port { 232 /* 233 * The VGA connected is implemented with a 234 * THS8134A triple DAC that can be run in 24bit 235 * or 16bit RGB mode. 236 */ 237 clcd_pads: endpoint { 238 remote-endpoint = <&clcd_panel>; 239 arm,pl11x,tft-r0g0b0-pads = <1 7 13>; 240 }; 241 }; 242 243 panel { 244 compatible = "panel-dpi"; 245 246 port { 247 clcd_panel: endpoint { 248 remote-endpoint = <&clcd_pads>; 249 }; 250 }; 251 252 /* Standard 640x480 VGA timings */ 253 panel-timing { 254 clock-frequency = <25175000>; 255 hactive = <640>; 256 hback-porch = <48>; 257 hfront-porch = <16>; 258 hsync-len = <96>; 259 vactive = <480>; 260 vback-porch = <33>; 261 vfront-porch = <10>; 262 vsync-len = <2>; 263 }; 264 }; 265 }; 266 }; 267}; 268