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/arch/powerpc/kernel/
Dcacheinfo.c43 struct cache *cache; member
117 struct cache { struct
123 struct cache *next_local; /* next cache of >= level */ argument
138 static const char *cache_type_string(const struct cache *cache) in cache_type_string() argument
140 return cache_type_info[cache->type].name; in cache_type_string()
143 static void cache_init(struct cache *cache, int type, int level, in cache_init() argument
146 cache->type = type; in cache_init()
147 cache->level = level; in cache_init()
148 cache->ofnode = of_node_get(ofnode); in cache_init()
149 INIT_LIST_HEAD(&cache->list); in cache_init()
[all …]
/arch/mn10300/mm/
DMakefile5 cache-smp-wback-$(CONFIG_MN10300_CACHE_WBACK) := cache-smp-flush.o
7 cacheflush-y := cache.o
8 cacheflush-$(CONFIG_SMP) += cache-smp.o cache-smp-inv.o $(cache-smp-wback-y)
9 cacheflush-$(CONFIG_MN10300_CACHE_INV_ICACHE) += cache-inv-icache.o
10 cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_ICACHE) += cache-flush-icache.o
11 cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_TAG) += cache-inv-by-tag.o
12 cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_REG) += cache-inv-by-reg.o
13 cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_TAG) += cache-flush-by-tag.o
14 cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_REG) += cache-flush-by-reg.o
17 cache-dbg-flush-by-tag.o cache-dbg-inv-by-tag.o
[all …]
DKconfig.cache2 # MN10300 CPU cache options
12 the affected cacheline to be read into the cache first before being
13 operated upon. Memory is not then updated by a write until the cache
14 is filled and a cacheline needs to be displaced from the cache to
19 cacheline is also in cache, it will be updated too.
35 cache. This means that the written data is immediately available for
38 This is not available for use with an SMP kernel if cache flushing
53 prompt "CPU cache flush/invalidate method"
58 This determines the method by which CPU cache flushing and
62 bool "Use the cache tag registers directly"
[all …]
/arch/powerpc/boot/dts/fsl/
Dp4080si-pre.dtsi98 next-level-cache = <&L2_0>;
100 L2_0: l2-cache {
101 next-level-cache = <&cpc>;
108 next-level-cache = <&L2_1>;
110 L2_1: l2-cache {
111 next-level-cache = <&cpc>;
118 next-level-cache = <&L2_2>;
120 L2_2: l2-cache {
121 next-level-cache = <&cpc>;
128 next-level-cache = <&L2_3>;
[all …]
Dmpc8641si-pre.dtsi38 d-cache-line-size = <32>;
39 i-cache-line-size = <32>;
40 d-cache-size = <32768>;
41 i-cache-size = <32768>;
50 d-cache-line-size = <32>;
51 i-cache-line-size = <32>;
52 d-cache-size = <32768>;
53 i-cache-size = <32768>;
Dt104xsi-pre.dtsi78 next-level-cache = <&L2_1>;
80 L2_1: l2-cache {
81 next-level-cache = <&cpc>;
88 next-level-cache = <&L2_2>;
90 L2_2: l2-cache {
91 next-level-cache = <&cpc>;
98 next-level-cache = <&L2_3>;
100 L2_3: l2-cache {
101 next-level-cache = <&cpc>;
108 next-level-cache = <&L2_4>;
[all …]
Dp2041si-pre.dtsi93 next-level-cache = <&L2_0>;
95 L2_0: l2-cache {
96 next-level-cache = <&cpc>;
103 next-level-cache = <&L2_1>;
105 L2_1: l2-cache {
106 next-level-cache = <&cpc>;
113 next-level-cache = <&L2_2>;
115 L2_2: l2-cache {
116 next-level-cache = <&cpc>;
123 next-level-cache = <&L2_3>;
[all …]
Dp3041si-pre.dtsi94 next-level-cache = <&L2_0>;
96 L2_0: l2-cache {
97 next-level-cache = <&cpc>;
104 next-level-cache = <&L2_1>;
106 L2_1: l2-cache {
107 next-level-cache = <&cpc>;
114 next-level-cache = <&L2_2>;
116 L2_2: l2-cache {
117 next-level-cache = <&cpc>;
124 next-level-cache = <&L2_3>;
[all …]
Dp5040si-pre.dtsi106 next-level-cache = <&L2_0>;
108 L2_0: l2-cache {
109 next-level-cache = <&cpc>;
116 next-level-cache = <&L2_1>;
118 L2_1: l2-cache {
119 next-level-cache = <&cpc>;
126 next-level-cache = <&L2_2>;
128 L2_2: l2-cache {
129 next-level-cache = <&cpc>;
136 next-level-cache = <&L2_3>;
[all …]
Dt4240si-pre.dtsi94 next-level-cache = <&L2_1>;
101 next-level-cache = <&L2_1>;
108 next-level-cache = <&L2_1>;
115 next-level-cache = <&L2_1>;
122 next-level-cache = <&L2_2>;
129 next-level-cache = <&L2_2>;
136 next-level-cache = <&L2_2>;
143 next-level-cache = <&L2_2>;
150 next-level-cache = <&L2_3>;
157 next-level-cache = <&L2_3>;
[all …]
/arch/sh/mm/
Dcache-debugfs.c28 struct cache_info *cache; in cache_seq_show() local
49 cache = &current_cpu_data.dcache; in cache_seq_show()
52 cache = &current_cpu_data.icache; in cache_seq_show()
55 waysize = cache->sets; in cache_seq_show()
64 waysize <<= cache->entry_shift; in cache_seq_show()
66 for (way = 0; way < cache->ways; way++) { in cache_seq_show()
76 addr += cache->linesz, line++) { in cache_seq_show()
89 addrstart += cache->way_incr; in cache_seq_show()
DMakefile5 obj-y := alignment.o cache.o init.o consistent.o mmap.o
7 cacheops-$(CONFIG_CPU_J2) := cache-j2.o
8 cacheops-$(CONFIG_CPU_SUBTYPE_SH7619) := cache-sh2.o
9 cacheops-$(CONFIG_CPU_SH2A) := cache-sh2a.o
10 cacheops-$(CONFIG_CPU_SH3) := cache-sh3.o
11 cacheops-$(CONFIG_CPU_SH4) := cache-sh4.o flush-sh4.o
12 cacheops-$(CONFIG_CPU_SH5) := cache-sh5.o flush-sh4.o
13 cacheops-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o
14 cacheops-$(CONFIG_CPU_SHX3) += cache-shx3.o
26 debugfs-$(CONFIG_CPU_SH4) += cache-debugfs.o
/arch/powerpc/boot/dts/
Diss4xx-mpic.dts40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
42 i-cache-size = <32768>;
43 d-cache-size = <32768>;
54 i-cache-line-size = <32>;
55 d-cache-line-size = <32>;
56 i-cache-size = <32768>;
57 d-cache-size = <32768>;
70 i-cache-line-size = <32>;
71 d-cache-line-size = <32>;
[all …]
Dsbc8548-pre.dtsi36 d-cache-line-size = <0x20>; // 32 bytes
37 i-cache-line-size = <0x20>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
43 next-level-cache = <&L2>;
/arch/m68k/kernel/
Dsys_m68k.c67 cache_flush_040 (unsigned long addr, int scope, int cache, unsigned long len) in cache_flush_040() argument
74 switch (cache) in cache_flush_040()
127 switch (cache) in cache_flush_040()
184 switch (cache) in cache_flush_040()
227 cache_flush_060 (unsigned long addr, int scope, int cache, unsigned long len) in cache_flush_060() argument
240 switch (cache) in cache_flush_060()
288 switch (cache) in cache_flush_060()
347 switch (cache) in cache_flush_060()
377 sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len) in sys_cacheflush() argument
382 cache & ~FLUSH_CACHE_BOTH) in sys_cacheflush()
[all …]
/arch/arm/mm/
DMakefile39 obj-$(CONFIG_CPU_CACHE_V4) += cache-v4.o
40 obj-$(CONFIG_CPU_CACHE_V4WT) += cache-v4wt.o
41 obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o
42 obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o
43 obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o
44 obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o
45 obj-$(CONFIG_CPU_CACHE_NOP) += cache-nop.o
46 obj-$(CONFIG_CPU_CACHE_V7M) += cache-v7m.o
104 obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
105 obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o l2c-l2x0-resume.o
[all …]
/arch/arm/boot/dts/
Duniphier-pro5.dtsi60 next-level-cache = <&l2>;
68 next-level-cache = <&l2>;
82 l2: l2-cache@500c0000 {
83 compatible = "socionext,uniphier-system-cache";
86 cache-unified;
87 cache-size = <(2 * 1024 * 1024)>;
88 cache-sets = <512>;
89 cache-line-size = <128>;
90 cache-level = <2>;
91 next-level-cache = <&l3>;
[all …]
Dhighbank.dts37 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
65 next-level-cache = <&L2>;
74 next-level-cache = <&L2>;
119 L2: l2-cache {
120 compatible = "arm,pl310-cache";
123 cache-unified;
124 cache-level = <2>;
Dbcm63138.dtsi27 next-level-cache = <&L2>;
35 next-level-cache = <&L2>;
80 L2: cache-controller@1d000 {
81 compatible = "arm,pl310-cache";
83 cache-unified;
84 cache-level = <2>;
85 cache-size = <524288>;
86 cache-sets = <1024>;
87 cache-line-size = <32>;
/arch/arm64/boot/dts/hisilicon/
Dhip05.dtsi93 next-level-cache = <&cluster0_l2>;
101 next-level-cache = <&cluster0_l2>;
109 next-level-cache = <&cluster0_l2>;
117 next-level-cache = <&cluster0_l2>;
125 next-level-cache = <&cluster1_l2>;
133 next-level-cache = <&cluster1_l2>;
141 next-level-cache = <&cluster1_l2>;
149 next-level-cache = <&cluster1_l2>;
157 next-level-cache = <&cluster2_l2>;
165 next-level-cache = <&cluster2_l2>;
[all …]
/arch/sh/boot/dts/
Dj2_mimas_v2.dts21 d-cache-size = <8192>;
22 i-cache-size = <8192>;
23 d-cache-block-size = <16>;
24 i-cache-block-size = <16>;
56 cache-controller@c0 {
57 compatible = "jcore,cache";
/arch/unicore32/mm/
DKconfig15 Say Y here to disable the processor instruction cache. Unless
21 Say Y here to disable the processor data cache. Unless
25 bool "Force write through D-cache"
27 Say Y here to use the data cache in writethrough mode. Unless you
31 bool "Disable D-cache line ops"
34 Say Y here to disable the data cache line operations.
/arch/s390/kernel/
Dcache.c70 struct cacheinfo *cache; in show_cacheinfo() local
77 cache = this_cpu_ci->info_list + idx; in show_cacheinfo()
79 seq_printf(m, "level=%d ", cache->level); in show_cacheinfo()
80 seq_printf(m, "type=%s ", cache_type_string[cache->type]); in show_cacheinfo()
82 cache->disable_sysfs ? "Shared" : "Private"); in show_cacheinfo()
83 seq_printf(m, "size=%dK ", cache->size >> 10); in show_cacheinfo()
84 seq_printf(m, "line_size=%u ", cache->coherency_line_size); in show_cacheinfo()
85 seq_printf(m, "associativity=%d", cache->ways_of_associativity); in show_cacheinfo()
/arch/powerpc/perf/
Disa207-common.c26 unsigned int unit, pmc, cache, ebb; in isa207_get_constraint() local
36 cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK; in isa207_get_constraint()
77 if (cache & 0x7) in isa207_get_constraint()
82 value |= CNST_L1_QUAL_VAL(cache); in isa207_get_constraint()
145 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; in isa207_compute_mmcr() local
185 cache = event[i] >> EVENT_CACHE_SEL_SHIFT; in isa207_compute_mmcr()
186 mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT; in isa207_compute_mmcr()
187 cache >>= 1; in isa207_compute_mmcr()
188 mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT; in isa207_compute_mmcr()
/arch/metag/kernel/
Dcachepart.c58 static int get_thread_cache_size(unsigned int cache, int thread_id) in get_thread_cache_size() argument
64 isEnabled = (cache == DCACHE ? metag_in32(MMCU_DCACHE_CTRL_ADDR) & 0x1 : in get_thread_cache_size()
70 cache_size = (cache == DCACHE ? get_global_dcache_size() : in get_thread_cache_size()
74 cache_size = (cache == DCACHE ? get_dcache_size() : in get_thread_cache_size()
77 t_cache_part = (cache == DCACHE ? in get_thread_cache_size()

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