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Searched refs:in_be32 (Results 1 – 25 of 83) sorted by relevance

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/arch/powerpc/boot/
Duartlite.c42 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_putc()
50 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_getc()
51 return in_be32(reg_base + ULITE_RX); in uartlite_getc()
56 u32 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_tstc()
Dcpm-serial.c100 while (in_be32(cpcr) & 0x10000) in cpm2_cmd()
105 while (in_be32(cpcr) & 0x10000) in cpm2_cmd()
118 out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) & ~0x30); in scc_disable_port()
129 out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) | 0x30); in scc_enable_port()
Dpq2.c44 sccr = in_be32(&immr[PQ2_SCCR]); in pq2_get_clocks()
45 scmr = in_be32(&immr[PQ2_SCMR]); in pq2_get_clocks()
Dugecon.c60 while (in_be32(cr_reg) & EXI_CR_TSTART) in ug_io_transaction()
66 data = in_be32(data_reg); in ug_io_transaction()
/arch/powerpc/platforms/cell/spufs/
Dhw_ops.c45 mbox_stat = in_be32(&prob->mb_stat_R); in spu_hw_mbox_read()
47 *data = in_be32(&prob->pu_mb_R); in spu_hw_mbox_read()
56 return in_be32(&ctx->spu->problem->mb_stat_R); in spu_hw_mbox_stat_read()
67 stat = in_be32(&spu->problem->mb_stat_R); in spu_hw_mbox_stat_poll()
104 if (in_be32(&prob->mb_stat_R) & 0xff0000) { in spu_hw_ibox_read()
124 if (in_be32(&prob->mb_stat_R) & 0x00ff00) { in spu_hw_wbox_write()
192 return in_be32(&ctx->spu->problem->spu_npc_RW); in spu_hw_npc_read()
202 return in_be32(&ctx->spu->problem->spu_status_R); in spu_hw_status_read()
217 return in_be32(&ctx->spu->problem->spu_runcntl_RW); in spu_hw_runcntl_read()
234 while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING) in spu_hw_runcntl_stop()
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Dswitch.c108 return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0; in check_spu_isolate()
223 csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW); in save_spu_runcntl()
241 if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) { in save_spu_status()
242 csa->prob.spu_status_R = in_be32(&prob->spu_status_R); in save_spu_status()
248 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & in save_spu_status()
253 if ((in_be32(&prob->spu_status_R) & stopped) == 0) in save_spu_status()
256 csa->prob.spu_status_R = in_be32(&prob->spu_status_R); in save_spu_status()
388 csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW); in save_ppu_querymask()
399 csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW); in save_ppu_querytype()
412 csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R); in save_ppu_tagstatus()
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/arch/powerpc/platforms/83xx/
Dsuspend.c126 u32 reg_cfg1 = in_be32(&pmc_regs->config1); in mpc83xx_change_state()
148 u32 event = in_be32(&pmc_regs->event); in pmc_irq_handler()
171 saved_regs.sicrl = in_be32(&syscr_regs->sicrl); in mpc83xx_suspend_save_regs()
172 saved_regs.sicrh = in_be32(&syscr_regs->sicrh); in mpc83xx_suspend_save_regs()
173 saved_regs.sccr = in_be32(&clock_regs->sccr); in mpc83xx_suspend_save_regs()
189 in_be32(&pmc_regs->config1) | PMCCR1_PME_EN); in mpc83xx_suspend_enter()
210 in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF); in mpc83xx_suspend_enter()
217 in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF); in mpc83xx_suspend_enter()
232 in_be32(&pmc_regs->config1) & ~PMCCR1_PME_EN); in mpc83xx_suspend_enter()
311 ret = !(in_be32(&rcw_regs->rcwhr) & RCW_PCI_HOST); in mpc83xx_is_pci_agent()
Dusb.c41 sccr = in_be32(immap + MPC83XX_SCCR_OFFS) & ~MPC83XX_SCCR_USB_MASK; in mpc834x_usb_cfg()
42 sicrl = in_be32(immap + MPC83XX_SICRL_OFFS) & ~MPC834X_SICRL_USB_MASK; in mpc834x_usb_cfg()
43 sicrh = in_be32(immap + MPC83XX_SICRH_OFFS) & ~MPC834X_SICRH_USB_UTMI; in mpc834x_usb_cfg()
/arch/powerpc/platforms/52xx/
Dlite5200.c74 if (in_be32(&cdm->rstcfg) & 0x40) /* Assumes 33Mhz clock */ in lite5200_fix_clock_config()
107 port_config = in_be32(&gpio->port_config); in lite5200_fix_port_config()
118 in_be32(&gpio->port_config), port_config); in lite5200_fix_port_config()
139 out_be32(mbar + 0x1048, in_be32(mbar + 0x1048) & ~0x300); in lite5200_suspend_prepare()
Dmedia5200.c58 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); in media5200_irq_unmask()
70 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); in media5200_irq_mask()
96 status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); in media5200_irq_cascade()
97 enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS); in media5200_irq_cascade()
222 port_config = in_be32(&gpio->port_config); in media5200_setup_arch()
Dmpc52xx_pic.c147 out_be32(addr, in_be32(addr) | (1 << bitno)); in io_be_setbit()
152 out_be32(addr, in_be32(addr) & ~(1 << bitno)); in io_be_clrbit()
194 ctrl_reg = in_be32(&intr->ctrl); in mpc52xx_extirq_set_type()
356 reg = in_be32(&intr->ctrl); in mpc52xx_irqhost_map()
429 intr_ctrl = in_be32(&intr->ctrl); in mpc52xx_init_irq()
492 status = in_be32(&intr->enc_status); in mpc52xx_get_irq()
507 status = in_be32(&sdma->IntPend); in mpc52xx_get_irq()
Dmpc52xx_common.c83 out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); in mpc5200_setup_xlb_arbiter()
198 val = in_be32(&mpc52xx_cdm->clk_enables); in mpc52xx_set_psc_clkdiv()
229 val = in_be32(&mpc52xx_cdm->rstcfg); in mpc52xx_get_xtal_freq()
312 mux = in_be32(&simple_gpio->port_config); in mpc5200_psc_ac97_gpio_reset()
/arch/powerpc/platforms/cell/
Dspider-pic.c87 out_be32(cfg, in_be32(cfg) | 0x30000000u); in spider_unmask_irq()
95 out_be32(cfg, in_be32(cfg) & ~0x30000000u); in spider_mask_irq()
155 old_mask = in_be32(cfg) & 0x30000000u; in spider_set_irq_type()
208 cs = in_be32(pic->regs + TIR_CS) >> 24; in spider_irq_cascade()
310 out_be32(cfg, in_be32(cfg) & ~0x30000000u); in spider_init_one()
317 out_be32(pic->regs + TIR_PIEN, in_be32(pic->regs + TIR_PIEN) | 0x1); in spider_init_one()
330 out_be32(pic->regs + TIR_DEN, in_be32(pic->regs + TIR_DEN) | 0x1); in spider_init_one()
/arch/powerpc/sysdev/
Dfsl_rmu.c213 osr = in_be32(&rmu->msg_regs->osr); in fsl_rio_tx_handler()
228 u32 dqp = in_be32(&rmu->msg_regs->odqdpar); in fsl_rio_tx_handler()
258 isr = in_be32(&rmu->msg_regs->isr); in fsl_rio_rx_handler()
301 dsr = in_be32(&fsl_dbell->dbell_regs->dsr); in fsl_rio_dbell_handler()
318 (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff); in fsl_rio_dbell_handler()
396 epwisr = in_be32(rio_regs_win + RIO_EPWISR); in fsl_rio_port_write_handler()
400 ipwmr = in_be32(&pw->pw_regs->pwmr); in fsl_rio_port_write_handler()
401 ipwsr = in_be32(&pw->pw_regs->pwsr); in fsl_rio_port_write_handler()
461 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR); in fsl_rio_port_write_handler()
467 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR); in fsl_rio_port_write_handler()
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Dcpm_common.c64 while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000) in udbg_putc_cpm()
78 (in_be32(&cpm_udbg_txdesc[1]) - PHYS_IMMR_BASE + in udbg_init_cpm()
83 cpm_udbg_txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]); in udbg_init_cpm()
116 cpm2_gc->cpdata = in_be32(&iop->dat); in cpm2_gpio32_save_regs()
127 return !!(in_be32(&iop->dat) & pin_mask); in cpm2_gpio32_get()
Dfsl_rio.c106 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR)); in fsl_rio_mcheck_exception()
143 *data = in_be32(priv->regs_win + offset); in fsl_local_config_read()
315 riwar = in_be32(&priv->inb_atmu_regs[i].riwar); in fsl_map_inb_mem()
318 win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK)) in fsl_map_inb_mem()
327 riwar = in_be32(&priv->inb_atmu_regs[i].riwar); in fsl_map_inb_mem()
352 riwar = in_be32(&priv->inb_atmu_regs[i].riwar); in fsl_unmap_inb_mem()
356 riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar); in fsl_unmap_inb_mem()
650 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20); in fsl_rio_setup()
653 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) { in fsl_rio_setup()
666 if (in_be32((priv->regs_win in fsl_rio_setup()
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Dcpm2_pic.c174 vold = in_be32(&cpm2_intctl->ic_siexr); in cpm2_set_irq_type()
207 bits = in_be32(&cpm2_intctl->ic_sivec); in cpm2_get_irq()
253 i = in_be32(&cpm2_intctl->ic_sivec); in cpm2_pic_init()
Dfsl_rcpm.c233 !(in_be32(pmcsr_reg) & RCPM_POWMGTCSR_SLP), 10000, 10); in rcpm_v1_plat_enter_state()
264 !(in_be32(pmcsr_reg) & RCPM_POWMGTCSR_LPM20_ST), 10000, 10); in rcpm_v2_plat_enter_state()
293 mask = in_be32(tben_reg); in rcpm_common_freeze_time_base()
300 in_be32(tben_reg); in rcpm_common_freeze_time_base()
/arch/powerpc/sysdev/ge/
Dge_pic.c118 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); in gef_pic_mask()
139 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); in gef_pic_unmask()
234 cause = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_STATUS); in gef_pic_get_irq()
236 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); in gef_pic_get_irq()
/arch/powerpc/platforms/85xx/
Dp1022_ds.c148 u64 lawbar = in_be32(&law[i].lawbar); in lbc_br_to_phys()
149 u32 lawar = in_be32(&law[i].lawar); in lbc_br_to_phys()
233 br0 = in_be32(&lbc->bank[0].br); in p1022ds_set_monitor_port()
234 br1 = in_be32(&lbc->bank[1].br); in p1022ds_set_monitor_port()
235 or0 = in_be32(&lbc->bank[0].or); in p1022ds_set_monitor_port()
236 or1 = in_be32(&lbc->bank[1].or); in p1022ds_set_monitor_port()
289 if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) != in p1022ds_set_monitor_port()
321 in_be32(&guts->pmuxcr); in p1022ds_set_monitor_port()
/arch/powerpc/platforms/44x/
Dwarp.c83 post1 = in_be32(fpga + 0x40); in warp_post_info()
84 post2 = in_be32(fpga + 0x44); in warp_post_info()
158 unsigned reset = in_be32(dtm_fpga + 0x14); in temp_isr()
223 u32 fan = in_be32(fpga + 0x34) & (1 << 14); in pika_dtm_check_fan()
/arch/powerpc/platforms/512x/
Dpdm360ng.c39 reg = in_be32(pdm360ng_gpio_base + 0xc); in pdm360ng_get_pendown_state()
43 reg = in_be32(pdm360ng_gpio_base + 0x8); in pdm360ng_get_pendown_state()
/arch/microblaze/kernel/
Dearly_printk.c39 while (--retries && (in_be32(base_addr + 8) & (1 << 3))) in early_printk_uartlite_putc()
85 !((in_be32(base_addr + 0x14) & BOTH_EMPTY) == BOTH_EMPTY)) in early_printk_uart16550_putc()
/arch/microblaze/include/asm/
Dio.h53 #define in_be32(a) __raw_readl((const void __iomem __force *)(a)) macro
57 #define readl_be(a) in_be32((__force unsigned *)a)
/arch/powerpc/platforms/embedded6xx/
Dflipper-pic.c181 irq_status = in_be32(io_base + FLIPPER_ICR) & in flipper_pic_get_irq()
182 in_be32(io_base + FLIPPER_IMR); in flipper_pic_get_irq()
251 icr = in_be32(io_base + FLIPPER_ICR); in flipper_is_reset_button_pressed()

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