| /arch/sparc/kernel/ |
| D | iommu.c | 51 struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl); in iommu_flushall() local
52 if (iommu->iommu_flushinv) { in iommu_flushall()
53 iommu_write(iommu->iommu_flushinv, ~(u64)0); in iommu_flushall()
58 tag = iommu->iommu_tags; in iommu_flushall()
65 (void) iommu_read(iommu->write_complete_reg); in iommu_flushall()
79 #define IOPTE_IS_DUMMY(iommu, iopte) \ argument
80 ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
82 static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte) in iopte_make_dummy() argument
87 val |= iommu->dummy_page_pa; in iopte_make_dummy()
92 int iommu_table_init(struct iommu *iommu, int tsbsize, in iommu_table_init() argument
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| D | sbus.c | 60 struct iommu *iommu = dev->archdata.iommu; in sbus_set_sbus64() local
75 cfg_reg = iommu->write_complete_reg; in sbus_set_sbus64()
210 struct iommu *iommu = op->dev.archdata.iommu; in sbus_build_irq() local
211 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sbus_build_irq()
272 struct iommu *iommu = op->dev.archdata.iommu; in sysio_ue_handler() local
273 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ue_handler()
346 struct iommu *iommu = op->dev.archdata.iommu; in sysio_ce_handler() local
347 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ce_handler()
425 struct iommu *iommu = op->dev.archdata.iommu; in sysio_sbus_error_handler() local
430 reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_sbus_error_handler()
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| D | pci_sun4v.c | 110 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num; in iommu_batch_flush()
179 struct iommu *iommu; in dma_4v_alloc_coherent() local
205 iommu = dev->archdata.iommu; in dma_4v_alloc_coherent()
206 atu = iommu->atu; in dma_4v_alloc_coherent()
210 tbl = &iommu->tbl; in dma_4v_alloc_coherent()
320 struct iommu *iommu; in dma_4v_free_coherent() local
328 iommu = dev->archdata.iommu; in dma_4v_free_coherent()
330 atu = iommu->atu; in dma_4v_free_coherent()
334 tbl = &iommu->tbl; in dma_4v_free_coherent()
353 struct iommu *iommu; in dma_4v_map_page() local
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| D | psycho_common.c | 206 struct iommu *iommu = pbm->iommu; in psycho_check_iommu_error() local
209 spin_lock_irqsave(&iommu->lock, flags); in psycho_check_iommu_error()
210 control = upa_readq(iommu->iommu_control); in psycho_check_iommu_error()
215 upa_writeq(control, iommu->iommu_control); in psycho_check_iommu_error()
245 spin_unlock_irqrestore(&iommu->lock, flags); in psycho_check_iommu_error()
402 struct iommu *iommu = pbm->iommu; in psycho_iommu_init() local
406 iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL; in psycho_iommu_init()
407 iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE; in psycho_iommu_init()
408 iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH; in psycho_iommu_init()
409 iommu->iommu_tags = pbm->controller_regs + PSYCHO_IOMMU_TAG; in psycho_iommu_init()
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| D | pci_fire.c | 30 struct iommu *iommu = pbm->iommu; in pci_fire_pbm_iommu_init() local
42 iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL; in pci_fire_pbm_iommu_init()
43 iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE; in pci_fire_pbm_iommu_init()
44 iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH; in pci_fire_pbm_iommu_init()
45 iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV; in pci_fire_pbm_iommu_init()
50 iommu->write_complete_reg = pbm->controller_regs + 0x410000UL; in pci_fire_pbm_iommu_init()
55 upa_writeq(~(u64)0, iommu->iommu_flushinv); in pci_fire_pbm_iommu_init()
57 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask, in pci_fire_pbm_iommu_init()
62 upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase); in pci_fire_pbm_iommu_init()
64 control = upa_readq(iommu->iommu_control); in pci_fire_pbm_iommu_init()
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| D | pci_schizo.c | 237 struct iommu *iommu = pbm->iommu; in schizo_check_iommu_error_pbm() local
244 spin_lock_irqsave(&iommu->lock, flags); in schizo_check_iommu_error_pbm()
245 control = upa_readq(iommu->iommu_control); in schizo_check_iommu_error_pbm()
252 upa_writeq(control, iommu->iommu_control); in schizo_check_iommu_error_pbm()
283 iommu->iommu_control); in schizo_check_iommu_error_pbm()
299 upa_writeq(control, iommu->iommu_control); in schizo_check_iommu_error_pbm()
341 spin_unlock_irqrestore(&iommu->lock, flags); in schizo_check_iommu_error_pbm()
1135 struct iommu *iommu = pbm->iommu; in schizo_pbm_iommu_init() local
1168 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; in schizo_pbm_iommu_init()
1169 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE; in schizo_pbm_iommu_init()
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| D | pci_psycho.c | 512 struct iommu *iommu; in psycho_probe() local
527 iommu = pbm->sibling->iommu; in psycho_probe()
529 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); in psycho_probe()
530 if (!iommu) { in psycho_probe()
536 pbm->iommu = iommu; in psycho_probe()
587 kfree(pbm->iommu); in psycho_probe()
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| D | ldc.c | 146 struct ldc_iommu iommu; member
1016 static void ldc_demap(struct ldc_iommu *iommu, unsigned long id, u64 cookie, in ldc_demap() argument
1023 base = iommu->page_table + entry; in ldc_demap()
1038 struct ldc_iommu *ldc_iommu = &lp->iommu; in ldc_iommu_init()
1039 struct iommu_map_table *iommu = &ldc_iommu->iommu_map_table; in ldc_iommu_init() local
1050 iommu->map = kzalloc(sz, GFP_KERNEL); in ldc_iommu_init()
1051 if (!iommu->map) { in ldc_iommu_init()
1055 iommu_tbl_pool_init(iommu, num_tsb_entries, PAGE_SHIFT, in ldc_iommu_init()
1088 kfree(iommu->map); in ldc_iommu_init()
1089 iommu->map = NULL; in ldc_iommu_init()
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| D | pci_sabre.c | 463 struct iommu *iommu; in sabre_probe() local
489 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); in sabre_probe()
490 if (!iommu) { in sabre_probe()
495 pbm->iommu = iommu; in sabre_probe()
578 kfree(pbm->iommu); in sabre_probe()
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| /arch/sparc/mm/ |
| D | iommu.c | 58 struct iommu_struct *iommu; in sbus_iommu_init() local
65 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL); in sbus_iommu_init()
66 if (!iommu) { in sbus_iommu_init()
71 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
73 if (!iommu->regs) { in sbus_iommu_init()
78 control = sbus_readl(&iommu->regs->control); in sbus_iommu_init()
83 sbus_writel(control, &iommu->regs->control); in sbus_iommu_init()
85 iommu_invalidate(iommu->regs); in sbus_iommu_init()
86 iommu->start = IOMMU_START; in sbus_iommu_init()
87 iommu->end = 0xffffffff; in sbus_iommu_init()
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| D | io-unit.c | 65 op->dev.archdata.iommu = iounit; in iounit_iommu_init()
144 struct iounit_struct *iounit = dev->archdata.iommu; in iounit_get_scsi_one()
155 struct iounit_struct *iounit = dev->archdata.iommu; in iounit_get_scsi_sgl()
171 struct iounit_struct *iounit = dev->archdata.iommu; in iounit_release_scsi_one()
185 struct iounit_struct *iounit = dev->archdata.iommu; in iounit_release_scsi_sgl()
205 struct iounit_struct *iounit = dev->archdata.iommu; in iounit_map_dma_area()
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| /arch/powerpc/platforms/cell/ |
| D | iommu.c | 115 struct cbe_iommu *iommu; member
142 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte, in invalidate_tce_cache() argument
149 reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; in invalidate_tce_cache()
206 invalidate_tce_cache(window->iommu, io_pte, npages); in tce_build_cell()
229 __pa(window->iommu->pad_page) | in tce_free_cell()
240 invalidate_tce_cache(window->iommu, io_pte, npages); in tce_free_cell()
246 struct cbe_iommu *iommu = data; in ioc_interrupt() local
248 stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); in ioc_interrupt()
264 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat); in ioc_interrupt()
309 static void cell_iommu_setup_stab(struct cbe_iommu *iommu, in cell_iommu_setup_stab() argument
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| /arch/sparc/include/asm/ |
| D | iommu_64.h | 54 struct iommu { struct
88 int iommu_table_init(struct iommu *iommu, int tsbsize, argument
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| D | device.h | 15 void *iommu; member
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| /arch/x86/include/asm/ |
| D | pci_64.h | 10 return sd->iommu; in pci_iommu()
16 sd->iommu = val; in set_pci_iommu()
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| /arch/powerpc/kernel/ |
| D | dma.c | 137 struct iommu_table *iommu; in dma_direct_alloc_coherent() local
147 iommu = get_iommu_table_base(dev); in dma_direct_alloc_coherent()
148 if (!iommu) in dma_direct_alloc_coherent()
152 return iommu_alloc_coherent(dev, iommu, size, dma_handle, in dma_direct_alloc_coherent()
161 struct iommu_table *iommu; in dma_direct_free_coherent() local
168 iommu = get_iommu_table_base(dev); in dma_direct_free_coherent()
173 if (WARN_ON(!iommu)) in dma_direct_free_coherent()
175 iommu_free_coherent(iommu, size, vaddr, dma_handle); in dma_direct_free_coherent()
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| /arch/arm64/boot/dts/mediatek/ |
| D | mt8173.dtsi | 384 iommu: iommu@10205000 { label
392 #iommu-cells = <1>;
769 iommus = <&iommu M4U_PORT_DISP_OVL0>;
779 iommus = <&iommu M4U_PORT_DISP_OVL1>;
789 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
799 iommus = <&iommu M4U_PORT_DISP_RDMA1>;
809 iommus = <&iommu M4U_PORT_DISP_RDMA2>;
819 iommus = <&iommu M4U_PORT_DISP_WDMA0>;
829 iommus = <&iommu M4U_PORT_DISP_WDMA1>;
1093 iommus = <&iommu M4U_PORT_VENC_RCPU>,
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| /arch/powerpc/boot/dts/fsl/ |
| D | p5020si-post.dtsi | 66 fsl,iommu-parent = <&pamu0>;
95 fsl,iommu-parent = <&pamu0>;
124 fsl,iommu-parent = <&pamu0>;
153 fsl,iommu-parent = <&pamu0>;
178 fsl,iommu-parent = <&pamu0>;
307 iommu@20000 {
382 fsl,iommu-parent = <&pamu0>;
388 fsl,iommu-parent = <&pamu0>;
400 fsl,iommu-parent = <&pamu1>;
413 fsl,iommu-parent = <&pamu1>;
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| D | p2041si-post.dtsi | 66 fsl,iommu-parent = <&pamu0>;
95 fsl,iommu-parent = <&pamu0>;
124 fsl,iommu-parent = <&pamu0>;
149 fsl,iommu-parent = <&pamu0>;
275 iommu@20000 {
368 fsl,iommu-parent = <&pamu0>;
374 fsl,iommu-parent = <&pamu0>;
386 fsl,iommu-parent = <&pamu1>;
400 fsl,iommu-parent = <&pamu1>;
408 fsl,iommu-parent = <&pamu1>;
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| D | p3041si-post.dtsi | 66 fsl,iommu-parent = <&pamu0>;
95 fsl,iommu-parent = <&pamu0>;
124 fsl,iommu-parent = <&pamu0>;
176 fsl,iommu-parent = <&pamu0>;
302 iommu@20000 {
395 fsl,iommu-parent = <&pamu0>;
401 fsl,iommu-parent = <&pamu0>;
413 fsl,iommu-parent = <&pamu1>;
427 fsl,iommu-parent = <&pamu1>;
435 fsl,iommu-parent = <&pamu1>;
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| D | p5040si-post.dtsi | 66 fsl,iommu-parent = <&pamu0>;
94 fsl,iommu-parent = <&pamu0>;
122 fsl,iommu-parent = <&pamu0>;
262 iommu@20000 {
360 fsl,iommu-parent = <&pamu0>;
366 fsl,iommu-parent = <&pamu0>;
378 fsl,iommu-parent = <&pamu2>;
391 fsl,iommu-parent = <&pamu4>;
400 fsl,iommu-parent = <&pamu4>;
408 fsl,iommu-parent = <&pamu4>;
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| /arch/arm/boot/dts/ |
| D | dra74x.dtsi | 61 compatible = "ti,dra7-dsp-iommu";
65 #iommu-cells = <0>;
71 compatible = "ti,dra7-dsp-iommu";
75 #iommu-cells = <0>;
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| D | exynos5250.dtsi | 262 iommu-names = "left", "right";
733 #iommu-cells = <0>;
744 #iommu-cells = <0>;
755 #iommu-cells = <0>;
765 #iommu-cells = <0>;
776 #iommu-cells = <0>;
786 #iommu-cells = <0>;
796 #iommu-cells = <0>;
806 #iommu-cells = <0>;
816 #iommu-cells = <0>;
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| /arch/ia64/include/asm/ |
| D | device.h | 11 void *iommu; /* hook for IOMMU specific extension */ member
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| /arch/arm64/include/asm/ |
| D | device.h | 22 void *iommu; /* private IOMMU data */ member
|